CN1830092A - 应变半导体cmos晶体管的制造结构和方法 - Google Patents

应变半导体cmos晶体管的制造结构和方法 Download PDF

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CN1830092A
CN1830092A CNA2004800219013A CN200480021901A CN1830092A CN 1830092 A CN1830092 A CN 1830092A CN A2004800219013 A CNA2004800219013 A CN A2004800219013A CN 200480021901 A CN200480021901 A CN 200480021901A CN 1830092 A CN1830092 A CN 1830092A
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pfet
nfet
semiconductor
gate stack
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陈华杰
杜里赛蒂·奇达姆巴拉奥
奥莱格·G.·格鲁斯晨科夫
安·L.·斯迪根
海宁·S.·杨
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

本发明提供了一种集成电路的p－型场效应晶体管(PFET)(10)和n－型场效应晶体管(NFET)(12)。经由仅设置在PFET(10)而不是NFET(12)的源极和漏极区(111)中的晶格错配半导体层例如硅锗，将第一应变施加到PFET(10)而不是NFET(12)的沟道区(20)中。本发明提供了一种PFET(10)和NFET(12)的制造方法。在这些区域中蚀刻沟槽，从而变成PFET的源极和漏极区(111)，使晶格错配的硅锗层(121)外延生长在其中，以便将应变施加到与其相邻的PFET的沟道区。使一层硅(14)生长在硅锗层(121)之上，由这层硅形成硅化物(68)，从而提供了低电阻的源极和漏极区(111)。

Description

应变半导体CMOS晶体管的制造结构和方法
技术领域
本发明涉及半导体集成电路的制造，更具体地说，是涉及一种具有晶格错配的源极和漏极区的应变半导体互补金属氧化物半导体(CMOS)晶体管的制造装置和方法。
背景技术
理论和经验研究已经证实，当将应变施加到晶体管的传导沟道中时，晶体管的载流子迁移率就大大增加。在p-型场效应晶体管中，公知的是，将压缩纵向应变施加到传导沟道中，以增大PFET的驱动电流。然而，如果将此相同应变施加到NFET的传导沟道中，其性能则下降。
已经有人提议，将拉伸纵向应变施加到NFET的传导沟道中，将压缩纵向应变施加到PFET的传导沟道中。这些建议都集中在掩蔽工艺上，所述工艺包括掩蔽芯片的PFET或NFET部分，和改变用于浅沟槽分离区的材料以施加应变。这些建议还包括集中于调整间隔件中存在的固有应力的掩蔽工艺。
硅锗是用于形成应变硅晶体管沟道的所需晶格错配的半导体。当第一半导体在第二半导体的单晶上生长时，就产生了应变，此时这两个半导体是彼此晶格错配的。硅和硅锗是彼此晶格错配的，从而二者之一在另一个上的生长就产生能够拉伸或压缩的应变。
硅锗外延生长在硅上，具有与硅晶体结构对准的晶体结构。然而，由于硅锗通常具有比硅大的晶体结构，因此外延生长的硅锗变得在内部被压缩。
在采用应变硅的其它建议中，硅锗形成整个单晶层基片。在这种情况下，硅锗层被称作松弛层，因为通过在硅锗层内形成位错而使应变释放。当单晶硅层在松弛的SiGe晶体区上外延生长时，就在外延生长的硅晶体中产生拉伸应变。这导致电子的迁移率提高，从而能够改善NFET的性能。
然而，这些技术要求SiGe松弛，因此要求SiGe层非常厚，即0.5-1.0μm。由于这个原因，空穴迁移率的提高难以获得，SiGe层要求锗的百分比较大，这导致SiGe晶体中的过度位错，从而产生问题。而且，受限于加工成本。
其它技术例如分级Ge浓度和化学机械抛光法可用来提高膜的质量。然而，这些技术苦恼于高成本和高缺陷密度。
据此，期望在不使用厚SiGe晶体区的前提下于PFET沟道区中产生应变。期望利用相当薄的外延生长SiGe，在器件的沟道区中产生所需的应变。
还期望通过使SiGe外延层生长在PFET的源极和漏极区中，而产生可增大PFET沟道区中的孔迁移率的压缩应变。
还期望提供一种用于在PFET沟道区中施加所需应变而不在NFET沟道区中产生相同应变的工艺。
发明内容
按照本发明的一个方面，提供一种集成电路的p-型场效应晶体管(PFET)和n-型场效应晶体管(NFET)。经由晶格错配的半导体层(例如设置在仅仅PFET而不是NFET的源极和漏极区中的硅锗)将第一应变施加到PFET而不是NFET的沟道区中。提供一种PFET和NFET的制造工艺。在该区域中蚀刻沟槽，从而变成PFET的源极和漏极区，并且使晶格错配的硅锗层在其中外延生长，以便将应变施加到与其相邻的PFET的沟道区中。
在本发明的一个方面，硅层生长在硅锗层之上，并且用此硅层形成硅化物(salicide)，从而提供低电阻的源极和漏极区。同时，硅化物在PFET和NFET栅导体中形成。
附图说明
图1示出按照本发明一个实施例的PFET和NFET。
图2示出按照本发明一个实施例的PFET的应变外形。
图3-9示出按照本发明一个实施例的PFET和NFET的若干制造阶段。
图10-15示出按照本发明另一个实施例的PFET和NFET的若干制造阶段。
图16-18示出按照本发明又一个实施例的PFET和NFET的若干制造阶段。
具体实施方式
图1示出按照本发明一个实施例的p-型场效应晶体管(PFET)和n-型场效应晶体管(NFET)。如图1所示，PFET10和NFET12是在基片16的单晶半导体区14中制造的，用一般由氧化物形成的沟槽分离区17分开。基片16可以是体(bulk)基片或者优选是绝缘体上半导体或绝缘体上硅(SOI)基片，其中在绝缘层18之上形成相当薄的半导体层。当在这样的SOI基片上形成场效应晶体管(FET)时，经常获得比别的方式更快的开关操作，因为晶体管的沟道区与体基片之间的结电容消除了。基片优选是体单晶硅基片，更优选是在绝缘层之上具有单晶硅区的硅SOI基片。正如在此实施例以及随后的实施例中所述，可参考在基片的单晶硅区内制造晶体管，这与其它类型的半导体例如III-V化合物半导体(例如锗砷化物(GeAs))相反。
如图1所示，PFET10包括设置在栅导体的多晶硅部分26下面的沟道区20。多晶硅部分26优选重掺杂到约1019cm-3的浓度。为了使在操作中导通PFET时所存在的p-型传导沟道的功函数匹配，多晶硅部分26优选包括p-型掺杂剂。栅导体优选还包括设置在多晶硅部分26之上的低电阻部分28。低电阻部分28具有比多晶硅部分26低得多的电阻，并优选包括金属、硅化物，或两者都包括。在一个优选实施例中，低电阻部分28包括硅化物例如钴硅化物(CoSi2)。
一对硅化物突起的源极-漏极区11设置在栅导体26两侧上的单晶半导体区中。每个突起的源极-漏极区11通过一对间隔件29，30从栅导体26偏移。间隔件29，30优选用氮化硅形成，尽管间隔件30也可用二氧化硅或氮化硅与二氧化硅层的组合(例如氧氮化硅)形成。
经由设置在PFET的源极-漏极区11下面的第二半导体埋设单晶层21，将第一应变施加到沟道区20中。第二半导体21优选是结合有硅和一个或多个其它族IV元素例如碳(C)或锗(Ge)的晶格错配半导体。第二半导体层21最优选是硅锗。优选是硅的第一半导体层22设置在第二半导体层21之上。优选地，优选是硅化物的低电阻接触层24设置在第一半导体层22之上。该低电阻层优选是硅化物，更优选是钴的硅化物，即CoSi2。
PFET 10的沟道区两侧上晶格错配第二半导体的存在，导致在沟道区20中产生应变。优选地，应变是压缩的。这样的压缩应变在50Mpa(百万帕)至几个Gpa(千兆帕)的范围内。应变对沟道区20内的电荷载流子的迁移率产生积极作用，从而能够达到没有这样的应变施加到其上的PFET沟道区时的迁移率的数倍。
当第一半导体优选地是硅时，晶格错配的第二半导体优选是不同的半导体例如硅锗或碳化硅，更优选是硅锗(SixGey)，其中x和y是百分比，在这里x+y＝100％。x与y之间的变化范围相当大，图示的y在1％-99％的范围内变化，而在这样的情况下，x相应地在99％与1％之间变化。
或者是，基片14的单晶区实质上可包括按照第一分子式Six1Gey1的比例的硅锗，其中x1和y1是百分比，在这里x1+y1＝100％，第二半导体层实质上包括按照第二分子式Six2Gey2的不同比例的硅锗，其中x2和y2是百分比，在这里x2+y2＝100％，x1不等于x2，y1不等于y2。
还是如图1所示，NFET 12配置在晶片的单晶区14中。NFET 12包括设置在栅导体的重掺杂n-型多晶硅部分42之下的沟道区40，而多晶硅部分42又设置在NFET 12的低电阻部分44之下。低电阻部分44与PFET 10的低电阻部分28类似，可包括金属、硅化物，或二者都包括，最优选的是包括钴的硅化物(CoSi2)。
NFET 12也包括一对低电阻、突起的源极-漏极接触区46，每个区优选地包括低电阻材料例如硅化物，最优选的是钴的硅化物(CoSi2)。优选地，每个突起的源极-漏极接触区46通过一对间隔件47，48与栅导体部分42，44分开。间隔件47优选地包括氮化硅，间隔件48优选地包括氮化硅、二氧化硅或氮化硅和二氧化硅的组合。
NFET 12没有第一应变施加到其沟道区40中，即，施加到PFET10的沟道区20中的那种应变类型和大小的应变。这是由于如下原因。首先，NFET 12具有n-型传导沟道，该沟道具有电子作为主载流子。当所有其它事项相等时，NFET 12比PFET 10具有更快的开关速度，因为PFET具有p-型传导沟道，该沟道具有空穴而不是电子作为主载流子。空穴比电子具有更小的迁移率，结果导致NFET 12中的开关速度更快。由此，PFET 10的开关速度必需增大，以便至少与NFET 12匹配。
其次，并没有相同类型和大小的应变施加到PFET 10和NFET 12上，因为其对NFET 12没有相同的作用。施加到NFET 12的沟道区40中的高幅度压缩应变(例如50Mpa至几个GPa)，实际上使其中的电子迁移率减小，从而导致开关速度更慢，而不是按所需的更快开关速度。
图2示出了基片的单晶区114内的PFET 110的应变外形。PFET110具有如上所述的PFET 10的结构，其在栅导体的每侧上具有沟道区120和升高的源极-漏极区，示出了其中一个升高的源极-漏极区111。升高的源极-漏极区111包括设置在硅层122之上的硅化物层124，而硅层122又设置在相当薄的晶格错配的第二半导体层121例如硅锗之上。薄层121又设置在基片的单晶区114之内。
在图2中，基片114内的曲线表示相同大小和类型(即压缩的或拉伸的)的应变存在的部位。由此，线126表示施加到沟道区120中的相等应变的部位。范围在50MPa与2GPa之间的压缩应变优选地施加在PFET 110的沟道区120的这样部位。更优选地，在100MPa与1GPa之间的压缩应变施加到沟道区120中。最优选地，范围在200MPa与600MPa之间的压缩应变施加到其上，因此400MPa是所需的应变目标。在源极-漏极区111中，应变的大小和方向与沟道区120中的应变是非常不同的。在掩埋式SiGe层121中，应变在1-5GPa的范围内，而2.5GPa是所获得的特定几何形状和尺寸的PFET的大概量，以便将所需应变施加到沟道区120中。另一方面，覆盖SiGe层的硅层122具有施加到其上的拉伸应变。源极-漏极区111中应变的具体数量不是如此重要。将所需大小和方向的应变施加到PFET的沟道区120中才是实际目的。通过实施按照本发明实施例的处理方法，而将这样的应变施加到PFET上，而不是NFET上。
图3表示出按照本发明一个实施例的CMOS制造工艺的第一阶段。作为按照该实施例处理的结果，形成p-型场效应晶体管(PFET)和n-型场效应晶体管(NFET)。在PFET中，利用晶格错配的半导体层将第一应变施加到沟道区中。另一方面，在NFET的沟道区中，没有施加第一应变，因为晶格错配的半导体层不在其近端。以这样的方式，PFET的载流子迁移率增大，同时仍然保持NFET中所需的性能。
图3表示出按照本发明一个实施例形成PFET和NFET的处理阶段。如图3所示，所形成的PFET栅极叠层25和NFET栅极叠层45覆盖基片的单晶区。单晶区14实质上包括第一半导体材料例如硅。PFET栅极叠层25包括覆盖单晶区14的栅极电介质13、在栅导体层26的侧壁上形成的一对间隔件29、和绝缘帽50。NFET栅极叠层45包括覆盖单晶区14的栅极电介质13、在栅导体层42的侧壁上形成的一对间隔件47、和绝缘帽52，还优选地通过沉积四乙基原硅酸盐(TEOS)的前体的氧化物来形成。
在此处理阶段，栅导体层26，42优选仅包括重掺杂半导体，最优选是重掺杂多晶硅。优选地，已经用所需类型和浓度的掺杂剂在此阶段制备了各自PFET栅极叠层和NFET栅极叠层的栅导体26，42，从而提供了所需的功能。例如，PFET栅极叠层可配有p+掺杂栅导体层26，而NFET栅极叠层可设有n+掺杂栅导体层42。间隔件29优选地由沉积的氮化物形成，绝缘帽50，52优选地通过沉积四乙基原硅酸盐(TEOS)的前体的氧化物来形成。
其次，如图4所示，将涂层56施加到基片的单晶区14的主表面54上。涂层56是通过沉积可去除材料按需施加的，可去除材料能够限制硅在选择性沉积工艺中的沉积。优选地，材料是氮化硅，并且材料优选地是通过沉积施加的。其次，如图5所示，将掩蔽材料58施加到基片上并进行构图，以覆盖NFET栅极叠层45两侧上的单晶区14的区域，但不覆盖PFET栅极叠层25两侧上的单晶区14的区域。在一个实施例中，掩蔽材料优选是光刻胶。或者是，掩蔽材料是随后能够完全去除的几种公知抗蚀材料中的任一种，例如抗反射涂料(ARC)、旋涂玻璃(spin-on-glass)、TEOS前体的氧化物、或多种掺杂玻璃诸如硼硅酸盐玻璃(BSG)、砷掺杂玻璃(ASG)、磷硅酸盐玻璃(PSG)或硼磷硅酸盐玻璃(BPSG)，这些材料能够沉积并随后去除。
其后，优选地通过各向异性垂直蚀刻工艺例如活性离子蚀刻(RIE)，在PFET栅极叠层25的两侧上蚀刻单晶区14。在这样的蚀刻过程中，PFET栅极叠层25提供了掩模，从而避免PFET栅极叠层25之下的区域比蚀刻。NFET栅极叠层45的两侧上的单晶区14的区域没有被蚀刻，因为它们被掩蔽层58和涂层56保护起来。作为是蚀刻的结果，在PFET栅极叠层25的两侧上的单晶区14中形成沟槽60。蚀刻沟槽60之后，诸如通过定时各向异性蚀刻去除掩蔽层58。这也具有去除单晶硅在沟槽60之内的部分的效果，沟槽60由于RIE蚀刻而被损坏。
其后，如图6所示，第二半导体层62在沟槽60内的单晶区14的第一半导体上外延生长。外延生长过程优选地通过选择性沉积来实施，以便仅有非常少或者根本没有第二半导体沉积在表面上，这与已生长在沟槽60内的单晶半导体上的不同。第二半导体，作为一个与另一半导体的单晶区接触生长的层，是能够产生应变的晶格错配半导体。
其次，如图7所示，利用仍然就地保护NFET中所形成的区域的涂层56，外延生长的第二半导体层62被凹陷到基片14的单晶区的主表面之下的所需层面64。此凹陷步骤优选地通过定时各向异性活性离子蚀刻来实施。或者是，凹陷步骤通过有选择地对硅进行各向同性蚀刻来实施，以便针对暴露的硅锗的蚀刻进行得更快，而蚀刻下面的硅单晶区比较慢。
其次，如图8所示，单晶硅的第二层66在硅锗凹陷层62之上外延生长。第二层66优选地以选择性外延沉积的方式来生长，以便除了沿沟槽60侧壁的硅锗层62的暴露区域和单晶硅的暴露区域上之外，仅有比较少或根本没有硅被沉积。由此，作为选择性外延沉积的结果，仅有比较少或根本没有硅沉积在涂层56和PFET栅极叠层25上。
其次，如图9所示，将涂层56从NFET栅极叠层45的两侧上的单晶区14上除去。其次，在PFET栅极叠层25和NFET栅极叠层45的两侧上形成优选包括氧化物材料的第二对间隔件30。间隔件30优选地通过共形地沉积氧化物材料(例如来自TEOS前体)、随后通过各向异性垂直蚀刻(例如RIE)来形成。优选地有选择地对硅进行蚀刻，以免使硅66的顶层过度凹陷。作为此蚀刻步骤的结果，从PFET栅极叠层25和NFET栅极叠层45上去除绝缘帽50，从而暴露出下面的多晶硅部分26和42。
其后，如图9所示，在NFET栅极叠层45两侧上的暴露半导体层66和暴露单晶区上形成硅化物68。同时，分别在PFET栅极叠层和NFET栅极叠层的暴露多晶硅部分26，42上形成硅化物。硅化物优选是钴的硅化物(CoSi2)，其通过在所处理的基片上沉积一层钴，而优选地以自对准的方式(即“salicide”)来形成。然后，实施退火，以便使钴和与其接触的硅发生反应，从而形成硅化物68。然后从所处理基片的剩余区域(即间隔件29，30和沟槽分离器17)上除去未反应的钴。
图10-14表示出按照另一方法实施例制造具有应变沟道区PFET和NFET的芯片的各个阶段。图10表示出形成PFET栅极叠层125和NFET栅极叠层145之后的处理阶段。这些栅极叠层具有参照图3如上所述的相同结构。例如，PFET栅极叠层具有覆盖栅极电介质113、氮化物侧壁间隔件129和氧化物绝缘帽150的栅导体126。NFET栅极叠层145具有相同的结构。沟槽分离器117位于上面设置有PFET栅极叠层125和NFET栅极叠层145的基片单晶区114的区域之间。
图10表示出与图5所示类似的处理阶段。已经在PFET栅极叠层125和NFET栅极叠层145之上沉积了共形掩蔽层156。共形掩蔽层156优选包括氧化物例如二氧化硅。层156从围绕PFET栅极叠层125的单晶区114的区域上去除。这可通过成批掩蔽围绕NFET栅极叠层145的单晶区114、其后利用各向异性蚀刻(例如RIF)垂直蚀刻单晶区的层156和下面层169，以与参照图5如上所述的相同方式来进行。在此蚀刻过程中，区域160没有蚀刻得象它们在如上所述实施例中的那样深。而是，区域160仅部分进行蚀刻。随后，此蚀刻限定硅顶层的形成层面。
其次，沉积第二共形掩蔽层170，以形成如图所示的结构。此层170优选是作为共形掩蔽层170的氮化硅，其能够终止使晶格错配半导体选择性生长的后序步骤。其次，如图11所示，实施各向异性垂直蚀刻工艺例如RIE，以便从沟槽160的底部除去掩蔽层170。在此工艺过程中，间隔件172保留在沟槽160的侧壁和栅极叠层125，145上。在蚀刻过程中，从围绕NFET栅极叠层145的单晶区114的区域中所有水平表面(例如绝缘帽150上以及的第一掩蔽层156上)除去掩蔽层170。
在此蚀刻之后，如通过有选择地对掩蔽层170的材料进行各向异性垂直RIE，而使沟槽160进一步凹陷，从而导致如图12所示结构的生成。例如，如果掩蔽层170包括氮化硅，那么就有选择地对氮化硅进行蚀刻。或者是，通过有选择地对氮化硅进行各向同性蚀刻来实施此步骤。
其次，如图13所示，晶格错配半导体有选择地在沟槽160中生长。晶格错配半导体优选是硅锗。通过此工艺，硅锗层176在沟槽160的底部和侧壁上外延生长，高达间隔件172的层面水平但没有沉积在其它地方。
其后，如图14所示，如通过有选择地对沟槽160中的硅和硅锗材料进行各向同性湿剥离处理，而除去掩蔽层170和间隔件172。结果，沿沟槽侧壁174的单晶区114暴露。
其次，实施一个步骤，以便使沟槽160中硅外延层178有选择地在硅锗层176之上生长。这导致如图15所示结构的生成，其与以上图8中所示的类似，只是氧化物掩蔽层156保留在NFET栅极叠层145之上，代替图8中的氮化物掩蔽层56。
其后，利用RIE蚀刻除去氧化物掩蔽材料156。通过此蚀刻，除去氧化物绝缘帽150，而就地剩下氮化物侧壁间隔件129。然后优选地利用硅化钴使前述沟槽160和多晶硅栅导体层126和142的顶部之上的源极和漏极区域硅化，如上参照图9所述。
图16-18表示出如上参照图9所述方案的变型实施例。此变型实施例从诸如图8或图15所示的处理阶段进行。如图16所示，在此实施例中，将氧化物掩蔽层156和间隔件29(或129)从多晶硅栅导体26，42(或126，142)中去除，而在它们的位置提供新的间隔件。这样做的目的是避免由于间隔件的特征变化(例如几个种类的结合)而导致器件参数漂移，间隔件的特征变化是由于硅锗和硅外延生长过程的热预算(budget)增大导致的。
如图17所示，第一间隔件230在多晶硅栅导体226，242上形成。这优选地通过共形地沉积氮化硅、其后进行垂直蚀刻(如利用RIE)来实施。然后，在PFET的源极和漏极区内(即，在单晶区114到PFET栅极叠层的间隔件230侧面的区域内)实施延伸和光圈植入。延伸和halo植入也在NFET的源极和漏极区内(即在单晶区114到NFET栅极叠层的间隔件230侧面的区域内)实施。在每种情况中，延伸和halo植入仅用第一间隔件230实施，以便植入到更接近PFET和NFET晶体管的沟道区的区域中。
其后，在间隔件230上形成第二间隔件232，然后在PFET栅极叠层的侧面上实施源极和漏极的植入，从而形成PFET源极和漏极区；在NFET栅极叠层的侧面上实施源极和漏极的植入，从而形成NFET源极和漏极区。以这种方式，源极和漏极植入区与晶体管的沟道区间隔一段所需的距离。
其后，以诸如如上所述的方式，分别在PFET栅极叠层和NFET栅极叠层的源极和漏极区中和多晶硅部分226和242之上形成硅化物。
前面有制造集成电路的PFET和NFET的所述方式，从而经由设置在PFET的源极和漏极区中的晶格错配半导体层，将第一应变施加到PFET的沟道区中。第一应变不施加到NFET的沟道区中，因为晶格错配的半导体层仅设置在PFET的源极和漏极区中，而不设置在NFET的源极和漏极区中。
已经描述了PFET和NFET的制造工艺，其中晶格错配的半导体仅设置在PFET的源极和漏极区中，而不设置在NFET的源极和漏极区中。此工艺，采用在NFET区域之上形成的掩蔽层，依赖于在这些区域中蚀刻沟槽，以变成PFET的源极和漏极区，并使硅锗层在其中外延生长，然后使硅层在该外延生长的硅锗层之上生长。
虽然以上参照本发明的优选实施例对本发明进行了描述，但是本领域的技术人员应该理解，在不脱离仅由所附权利要求书限定的本发明范围和精髓的前提下，能够作出许多修改和增进。

Claims (32)

1、一种具有互补金属氧化物半导体(CMOS)晶体管的集成电路，所述晶体管包括p-型场效应晶体管(PFET)和n-型场效应晶体管(NFET)，其中经由设置在所述PFET而不是NFET的源极和漏极区中的半导体层，将第一应变施加到所述PFET而不是NFET的沟道区中，所述半导体层与设置在所述PFET和所述NFET的所述沟道区中的单晶半导体晶格错配。
2、如权利要求1所述的集成电路，其特征在于，所述PFET和所述NFET的沟道区设置在第一半导体的单晶区中，所述晶格错配的半导体包括一层设置在所述第一半导体的所述单晶区之上的第二半导体。
3、如权利要求2所述的集成电路，其特征在于，所述第一半导体的所述单晶区具有由所述PFET的栅极叠层的栅极电介质层面限定的主表面，所述第二半导体的所述层具有设置在所述主表面之下的顶部表面。
4、如权利要求3所述的集成电路，其特征在于，还包括设置在所述第二半导体的所述层之上的所述第一半导体的单晶层。
5、如权利要求1所述的集成电路，其特征在于，所述第一半导体实质上包括选自由以下物质构成的组中的半导体：硅、硅锗和碳化硅，所述第二半导体实质上包括不同于所述第一半导体的另一半导体，所述另一半导体选自由以下物质构成的组：硅、硅锗和碳化硅。
6、如权利要求1所述的集成电路，其特征在于，所述第一半导体实质上包括硅，所述第二半导体实质上包括硅锗。
7、如权利要求1所述的集成电路，其特征在于，所述第一半导体实质上包括按照第一分子式Six1Gey1的硅锗，其中x1和y1是百分比，x1+y1＝100％，y1至少是1％，所述第二半导体实质上包括按照第二分子式Six2Gey2的硅锗，其中x2和y2是百分比，x2+y2＝100％，y2至少是1％，x1不等于x2，y1不等于y2。
8、如权利要求1所述的集成电路，其特征在于，所述第一应变是压缩应变。
9、如权利要求6所述的集成电路，其特征在于，所述第二半导体实质上包括具有至少1％锗含量的硅锗。
10、如权利要求4所述的集成电路，其特征在于，所述PFET和所述NFET的每一个还包括接触所述PFET和所述NFET之栅导体、源极区和漏极区的硅化物层。
11、如权利要求10所述的集成电路，其特征在于，所述硅化物实质上包括钴的硅化物。
12、一种具有互补金属氧化物半导体(CMOS)晶体管的集成电路，所述晶体管包括p-型场效应晶体管(PFET)和n-型场效应晶体管(NFET)，每个晶体管具有设置在基片的单晶硅区中的沟道区，其中经由设置在所述PFET而不是NFET的源极和漏极区中的实质上包括硅锗的埋入式晶格错配半导体层，将第一应变施加到所述PFET而不是NFET的沟道区中，所述硅锗具有按照分子式SixGey的比例，其中x和y是百分比，每个至少为1％，x+y＝100％。
13、一种p-型场效应晶体管(PFET)和n-型场效应晶体管(NFET)的制造方法，所述PFET和所述NFET均具有沟道区，所述PFET的所述沟道区具有第一应变，所述NFET的所述沟道区没有所述第一应变，所述方法包括：
在第一半导体的单晶区的主表面之上形成PFET栅极叠层和NFET栅极叠层，所述PFET栅极叠层和所述NFET栅极叠层的每一个都包括栅极电介质、在所述栅极电介质上形成的栅导体、在所述栅导体之上形成的帽层，和在所述栅导体的侧壁上形成的第一间隔件；
使所述PFET栅极叠层的侧面上的所述单晶区凹陷，同时避免所述NFET栅极叠层的侧面上的所述单晶区的所述主表面凹陷；
使一层第二半导体生长在通过所述凹陷暴露的所述单晶区的区域中，同时避免所述层生长在所述NFET栅极叠层之侧面上的所述单晶区上，所述第二半导体与所述第一半导体晶格错配，从而将所述第一应变施加到所述PFET的所述沟道区中；以及
在所述PFET栅极叠层的所述侧面上制造源极区和漏极区，从而形成所述PFET，在所述NFET栅极叠层的所述侧面上制造源极区和漏极区，从而形成所述NFET。
14、如权利要求13所述的方法，其特征在于，还包括使所述单晶区的所述主表面之下的所述第二半导体层凹陷。
15、如权利要求14所述的方法，其特征在于，还包括使一层所述第一半导体在所述凹陷的第二半导体层之上生长。
16、如权利要求15所述的方法，其特征在于，还包括在所述PFET和所述NFET的所述源极区和漏极区之上形成自对准硅化物。
17、如权利要求16所述的方法，其特征在于，还包括在所述PFET和所述NFET的所述栅导体的多晶硅部分之上形成自对准硅化物。
18、如权利要求17所述的方法，其特征在于，所述硅化物包括钴的硅化物。
19、如权利要求15所述的方法，其特征在于，所述第一半导体包括硅，所述第二半导体包括硅锗，所述硅锗具有至少1％的锗含量。
20、如权利要求19所述的方法，其特征在于，所述晶格错配的第二半导体将压缩应变施加到所述PFET的所述沟道区中。
21、如权利要求13所述的方法，其特征在于，形成所述源极区和漏极区的所述步骤还包括：从所述PFET栅极叠层和所述NFET栅极叠层上除去所述第一间隔件，并在所述PFET栅极叠层和所述NFET栅极叠层的侧壁上形成第二间隔件。
22、如权利要求21所述的方法，其特征在于，所述第二间隔件比所述第一间隔件厚。
23、如权利要求21所述的方法，其特征在于，还包括将光圈植入所述单晶区的暴露区域和所述第一半导体的所述层。
24、如权利要求21所述的方法，其特征在于，还包括延伸植入所述单晶区的暴露区域和所述第一半导体的所述层。
25、如权利要求22所述的方法，其特征在于，还包括形成侧向接触所述第二间隔件的第三间隔件，并将源极和漏极区植入所述单晶区的所述暴露区域和所述第一半导体的所述层。
26、如权利要求13所述的方法，其特征在于，利用图案化嵌段掩模，避免所述NFET栅极叠层的所述侧面上的所述单晶区凹陷。
27、如权利要求13所述的方法，其特征在于，通过将第一涂层施加到所述NFET栅极叠层的所述侧面上的所述单晶区，避免所述第二半导体层在所述NFET栅极叠层的所述侧面上的所述单晶区上生长。
28、如权利要求27所述的方法，其特征在于，所述涂层是在包括所述PFET栅极叠层和所述NFET栅极叠层之上的所述单晶区的暴露表面之上共形地形成的。
29、如权利要求28所述的方法，其特征在于，还包括终止所述PFET叠层的所述侧面上的所述单晶区的所述凹陷，并在通过所述凹陷暴露的所述单晶区的所述区域上形成第二涂层，然后继续进行所述凹陷，从而使所述第二半导体不在由所述第二涂层保护的区域中生长。
30、如权利要求29所述的方法，其特征在于，还包括在所述第二半导体的所述层上生成一层所述第一半导体。
31、如权利要求30所述的方法，其特征在于，所述第一半导体包括硅，所述第二半导体包括硅锗，所述硅锗具有至少1％的锗含量。
32、如权利要求29所述的方法，其特征在于，所述第二半导体将所述第一应变作为压缩应变来施加。
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WO2005017964A3 (en) 2005-06-02
IL173422A0 (en) 2006-06-11
US20070249114A1 (en) 2007-10-25
KR100791441B1 (ko) 2008-01-04
US7396714B2 (en) 2008-07-08
US20050029601A1 (en) 2005-02-10
WO2005017964A2 (en) 2005-02-24
US20050158931A1 (en) 2005-07-21
JP4808618B2 (ja) 2011-11-02
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