CN1798479A - 包括嵌入式芯片的印刷电路板及其制造方法 - Google Patents
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Abstract
本文公开了制造包括嵌入式芯片的印刷电路板的方法,包括形成供芯片插入的穿过基板的中空部分,将芯片插入到中空部分,使用镀覆工艺将芯片固定在基板上,以形成具有嵌入式芯片的中央层,然后在中央层上层叠未固化树脂层和具有电路图案的电路层。另外,还提供了使用上述方法制造的包括嵌入式芯片的PCB。
Description
发明领域
本发明一般涉及包括嵌入式芯片的印刷电路板(PCB)及其制造方法。更具体地,本发明涉及制造包括嵌入式芯片的PCB的方法,包括形成供芯片插入的穿过基板的中空部分;将芯片插入到中空部分;使用镀覆工艺将芯片固定在基板上,以形成具有嵌入式芯片的中央层;然后在中央层上层叠未固化树脂层和具有电路图案的电路层;以及使用上述方法制造的包括嵌入式芯片的PCB。
发明背景
随着电子工业的快速发展,为了符合电子产品对小型化和高功能性的要求,电子技术已经发展到将电阻器、电容器、IC(集成电路)等插入到基板中。
长期以来,虽然分立式芯片电阻器或分立式芯片电容器已经被安装到PCB上,但只是最近才开发了包括嵌入式芯片如电阻器或电容器的PCB。
在制造包括嵌入式芯片的技术中,使用新材料和工艺将芯片如电阻器或电容器插入到基板的外层或内层中,从而替代传统的芯片电阻器和芯片电容器。
也就是说,包括嵌入式芯片的PCB是指将芯片如电容器嵌入到基板自身的内层中或其外层中。不考虑基板本身的尺寸,如果芯片被引入到PCB中,则称其为“嵌入式芯片”。这种基板被称作“嵌入芯片的PCB”。
嵌入芯片的PCB的主要特征是在PCB内部提供芯片,而不需要将芯片安装到基板上。
通常,嵌入芯片的PCB的制造技术大致分为三种。
其一,提供了制造聚合物厚膜型电容器的方法,包括涂覆聚合物电容器糊,然后将该糊进行热固化,也就是干燥。具体地,该方法包括将聚合物电容器糊涂覆到PCB的内层上,然后干燥聚合物电容器糊,随后在其上印刷并干燥铜浆,以形成电极,从而获得嵌入的电容器。
其二,提供了制造嵌入式分立电容器的方法,包括用填充陶瓷的(ceramic filled)光敏树脂涂布PCB,美国Motorola有限公司申请了该方法的专利。上述方法包括在基板上涂布含陶瓷粉的光敏树脂,在树脂层上层叠铜箔层,以形成上电极和下电极,形成电路图案,然后对光敏树脂进行蚀刻,从而获得分立电容器。
其三,提供了制造嵌入电容器的方法,包括将具有电容特性的电介质层插入到PCB的内层中,以替代安装在PCB上的去耦电容器,该方法由美国Sanmina有限公司申请专利。在该方法中,将具有电源电极和接地电极的电介质层插入到PCB的内层中,从而获得功率分配(power distributed)的去耦电容器。
为了满足电子产品的各种功能和优越性能,日益需要更高速的电子元件。而且,为了提高元件的速度,将封装接合方式从典型的接合方式,如引脚框架(lead frame)、打线接合(wire bonding)、引脚型接合等改变为小球型接合方式或芯片倒装接合方式。
对于采用芯片倒装接合方式的高速产品,或对于CPU或图像处理芯片组,时钟脉冲(clock)以2GHz或更高的速度工作。
这种CPU或芯片组需要短的信号生成时间和高电流,还被设计用来进一步减小IC、芯片倒装封装的信号线和用来高速运行的主板之间的间隙。
但是,随着元件速度的增加,发生电源线的电压波动,导致产生大量的高频噪声,如SSN(同步切换噪声)或Δ-I(ΔI)。
高频噪声(如SSN)导致系统延迟或逻辑错误,从而降低系统的性能和可靠性。
因此,在器件工作所需的电流和切换速度不可变时,通过降低电源线的电感(inductance),可以有效地减少SSN。此外,使用去耦电容器来减小电源线的电压波动。
将去耦电容器安装在电源线上,由此可以直接供应切换电路所需的电流。这样,电源线电感得以屏蔽,因而明显减少电压降现象并且也可减少SSN。
图1A~1F依次说明根据第一种传统技术制造包括嵌入式芯片的PCB的工艺,所述的第一种传统技术公开在日本专利公开公告No.2004-7006中。
在图1A中,绝缘层1被加工成具有贯穿其中的中空部分3,而且穿过绝缘层1形成贯通孔2并填充导电墨。
在图1B中,在保护膜6上进行电路形成工艺,从而在其上形成预定的电路图案4。
在图1C中,在电路图案4上安装电气元件5。
在图1D中,将具有填充导电墨的贯通孔2的绝缘层1粘合到电路图案4上。
在图1E中,将保护膜6从电路图案4上除去,以形成中央层1。
在图1F中,形成具有预定电路图案9和填充导电墨的通孔11的电路层7和8,然后将其层叠到中央层1的两个表面上。
图2A~2D依次说明根据第二种传统技术制造包括嵌入式芯片的PCB的工艺,所述的第二种传统技术公开在日本专利公开公告No.2004-7006中。
在图2A中,形成具有预定图案22和贯通孔21的电路层20。
在图2B中,将电气元件23安装在电路层20的预定电路图案22上。
在图2C中,形成中央层25的中空部分,然后加工中央层25以具有预定电路图案26和贯通孔27,并将其层叠在电路层20上。
在图2D中,形成具有预定电路图案29和贯通孔30的电路层28,并将其层叠在中央层25上。
这种情况下,因为电气元件和作为中央层的绝缘层之间的间隙大,因而所得的产品具有大尺寸,所以第一种和第二种传统技术是不利的。
另外,因为芯片和铜箔层之间的间隙大,因而不能获得有效的辐射效果,所以第一种和第二种传统技术是不利的。
另外,因为用来层叠的堆焊工艺需要很长时间,所以第二种传统技术是不利的。
至于图3A,示意性说明了根据第三种传统技术层叠时包括嵌入式芯片的PCB的结构层。另外,图3B~3F依次说明形成图3A中各层核心的工艺。上述技术公开在日本专利公开公告No.2004-153084中。
在图3A中,下电路层包括具有预定电路图案3和辐射图案6的膜8,其中将导电墨涂覆到辐射图案6上。
然后,通过膜8形成中空部分,并将膜8进一步加工成具有预定图案3和填充导电墨的贯通孔6,即得中央层。这样,膜8被提供在与将插入到其中空部分的电气元件5厚度相对应的多个层中。
最后,通过将膜8加工成具有预定电路图案3和填充导电墨的贯通孔9来形成上电路层,然后将上电路层和下电路层一次性层叠到具有插入的电气元件5的中央层上。
在图3B中,为了形成各层的核心,将铜箔层10层叠到膜8上。
在图3C中,将膜8上的铜箔层10经历一般的电路形成工艺,以形成电路图案3。将保护膜11涂覆到膜8的下表面上。
在图3D中,在对应于膜8和保护膜11上的上电路图案3的位置上形成贯通孔8a。
在图3E中,用导电墨9填充贯通孔8a。
在图3F中,将保护膜11从膜8去除。
但是,第三种传统技术的缺点在于在同时叠加时填充导电墨的贯通孔粘合到芯片上,因而不能够准确控制层的对齐。
此外,因为使用辐射图案产生辐射,故由于形成发射辐射图案所需的通道,导致对高密度电路的制造施加限制。
从这一方面讲,WO 01/19148公开了将芯片电容器嵌入在核心层中以减小IC芯片和芯片电容器之间距离的方法。但是,由于芯片电容器只是简单地通过导电胶粘剂嵌入在核心层中,因此上述方法具有与制造包括嵌入式芯片的PCB的传统制造方法相似的问题。
发明内容
因此,本发明牢记现有技术中存在的上述问题,并且本发明的目的是提供制造包括嵌入式芯片的PCB的方法,其中在形成中央层时使用镀覆工艺将芯片固定在中央层上,从而使后续工艺易于进行。
本发明的另一个目的是提供制造包括嵌入式芯片的方法,其中在将其他层层叠到中央层上之前,对中央层的芯片的连接状态进行电检查,以易于改正错误。
本发明的另一个目的是提供包括嵌入式芯片的PCB及其制造方法,其中不需要使用焊料进行芯片的电连接,因此不产生由焊料所导致的噪声。
本发明的另一个目的是提供包括嵌入式芯片的PCB及其制造方法,其中,嵌入在PCB中的芯片的电连接特性得以改进。
为了实现上述目的,本发明提供了制造包括嵌入式芯片的PCB的方法,包括形成穿过覆铜板(copper clad laminate)的供芯片插入的中空部分和通孔;将芯片插入到中空部分;对基板的整个表面进行镀覆;在基板的两个表面上形成电路图案,以形成中央层;并在基板上层叠一个或多个电路层和一个或多个绝缘层。
另外,本发明还提供了包括嵌入式芯片的PCB,包括中央层,穿过该层形成贯通孔和中空部分,所述中央层具有利用镀覆工艺固定且插入到中空部分的芯片和在所述中央层的两个表面上形成的电路图案;绝缘层,其层叠在中央层的一个或两个表面上,并具有填充导电墨的贯通孔;和电路层,其层叠在绝缘层上,并具有通孔和通过贯通孔电连接到中央层的镀覆层上的电路图案。
附图说明
从结合附图的下文详述中将更清楚地理解本发明的上述和其他目的、特征和优点,其中:
图1A~1F是依次说明根据第一种传统技术制造包括嵌入式芯片的PCB的工艺的截面图。
图2A~2D是依次说明根据第二种传统技术制造包括嵌入式芯片的PCB的工艺的截面图。
图3A是示意性说明根据第三种传统技术叠加时包括嵌入式芯片的PCB的构层的截面图。
图3B~3F是说明制造图3A中各层核心的工艺的截面图。
图4A~4G是依次说明根据本发明在包括嵌入式芯片的PCB的制造方法中形成电路层的工艺的截面图。
图5A~5E是依次说明根据本发明在中央层的两个表面上层叠非固化树脂层和电路层的工艺的截面图。
具体实施方式
下文中将参照附图进行本发明的详细描述。
图4A~4G依次说明根据本发明在包括嵌入式芯片的PCB的制造方法中形成电路层的工艺。
在图4A中,制作覆铜层压板(CCL)400,其具有绝缘树脂层401和在其两个表面上形成的铜箔层402。这里,CCL 400优选示例为玻璃/环氧树脂CCL,其具有由浸于玻璃纤维中的环氧树脂(树脂和固化剂的混合物)形成的绝缘层和形成于其上的铜箔层。
在图4B中,穿过CCL400形成待插入芯片的中空部分403和通孔404。优选通过机械打孔工艺如CNC打孔工艺来完成中空部分403和通孔404的形成。另外,也可以采用常用于制造PCB的激光打孔工艺。但是,由于激光不能够透过铜箔层402,因此激光打孔工艺还需要通过蚀刻工艺将要形成中空部分403和通孔404处的部分铜箔层402预先去除的工艺。打孔之后,优选进行用来去除由打孔所产生的污渍的去污工艺。
在图4C中,将由树脂形成的粘合片408附着到具有中空部分403的CCL 400的一个表面上,并将芯片405插入到中空部分403中。
这样,由主体部分407和电极引脚406组成的芯片405包括无源元件如电容器或电感器(inductor),或有源元件如IC芯片。如图4C所示,芯片405的电极引脚406应该位于芯片405的两侧。另外,由于芯片405构成PCB的一层,优选很薄地形成。
当将芯片405插入到中空部分403时,它与粘合片408粘附。也就是说,粘合片408用来临时固定芯片405。如图4C所示,优选将芯片405插入到中空部分403,并且与中空部分403的内壁之间有小的间隙。
在图4D中,在基板的整个表面上进行镀覆工艺。涂覆除附着有充当绝缘物的粘合片层408的基板表面以外的基板表面。具体地,通过无电镀覆和随后的铜电镀进行镀覆工艺,这是因为基板是由绝缘材料形成的。因而,在未附着粘合片408的表面上、芯片405和插入芯片的中空部分403的间隙中以及通孔404的内壁上形成镀覆层409。在镀覆之前,优选进行清洗工艺,以便从包括芯片405的暴露表面的基板的整个表面去除杂质和残余物。
在图4E中,将粘合片408从CCL 400上剥离。从而将CCL 400的部分铜箔层402和部分镀覆层409暴露在外。
在图4F中,去除粘合层408之后,使表面经历无电镀和随后的电镀,以形成镀覆层409’。形成镀覆层409’以提供能够电传导芯片405的电极引脚406的电接触。如果对电极引脚406提供了电接触,则不需要形成镀覆层409’。
在图4G中,对基板的两个表面上形成的镀覆层409和铜箔层402进行选择性蚀刻,以形成电路图案,产生包括插入芯片405的中央层410。
这样,蚀刻工艺包括将光敏抗蚀剂涂覆到基板的两个表面上,将设计为电路图案的掩膜放置在抗蚀层上,使基板曝光,从而仅去除未固化部分,在基板上形成抗蚀图案,然后将其浸入到蚀刻溶液中,即得所需的电路图案。
如图4G所示,在形成电路图案时,应该注意芯片405的主体部分407的上表面和下表面暴露在外,而其电极引脚406未暴露在外。此外,如下所述,芯片405的电极引脚406借助镀覆层409而电连接于层叠层。
在通过图4A~4G所示工艺形成的中央层410的两个表面上,将所需数目的未固化树脂层和电路层依次层叠,然后,进行真空加热的压缩工艺,即得包括嵌入式芯片的PCB。
图5A~5E依次说明根据本发明在中央层410的两个表面上层叠未固化树脂层和电路层的工艺。
在图5A中,将未固化树脂层412a、412b和412c和在其两个表面上具有电路图案的电路层413以及铜箔层411a和411b层叠在由图4A~4G所示工艺形成的中央层的两个表面上。
仅为本发明优选实施方案的图5所示的层叠工艺包括:在中央层410的两个表面上层叠未固化树脂层和每个具有电路图案的电路层,并层叠铜箔层作为最外层。
在图5B中,在真空中对层叠的基板进行加热,并从其上表面和下表面对其进行压缩,以形成包括嵌入式芯片405的基板。通过在真空中加热和压缩,使未固化树脂层412a、412b和412c在固化时与中央层410、电路层413和铜箔层411a与411b彼此附着。在该情况下,基板的电路层的数目随如图5A所层叠的电路层的数目而变化。
在图5C中,通过机械打孔工艺如CNC打孔工艺穿过基板形成贯通孔414和盲通孔415。在打孔工艺后,优选进行去污工艺来去除污渍。
为了更精确地打孔,可以通过激光打孔来形成盲通孔415。但是,由于激光不能够穿透铜箔层411a和411b,因此,先通过蚀刻去除待形成盲通孔415处的部分铜箔,然后进行激光打孔。
在图5D中,在基板的整个表面上进行镀覆工艺,以在基板外层和盲通孔415与贯通孔414的内壁上形成镀覆层416。在镀覆之前,优选进行清洗工艺来去除杂质或残余物。
在图5E中,在基板的最外层411a、411b、416上形成电路图案。在电路图案的形成方法中,优选采用蚀刻工艺。通过蚀刻形成电路图案的工艺包括形成抗蚀图案,然后进行蚀刻,如图4G所示形成的电路图案。
如上所述,本发明提供了包括嵌入式芯片的PCB和使用镀覆工艺的其制造方法。根据本发明的制造PCB的方法,由于在形成中央层时使用镀覆工艺将芯片固定在中央层上,因此在后续工艺中可以容易地操作。
根据本发明的制造PCB方法,在中央层上进行层叠之前,对中央层中芯片的连接状态进行电检查来改正错误。
根据本发明的制造PCB方法,由于不需要使用焊料进行芯片的电连接,因而防止了由焊料所致的噪声的产生。
根据本发明的制造PCB方法,由于在使用镀覆工艺时,与使用焊料的传统连接工艺相比芯片具有更宽的连接面积,因而改进了电性能和辐射性能。
根据本发明的制造PCB方法,由于包括插入芯片的基板在镀覆之前先进行清洗,省略了单独洗涤芯片的传统步骤,从而减少了全部工艺的数目。
另外,本发明的PCB的制造方法可以用于将能够以薄板形式制造的所有类型芯片插入到PCB中。
虽然为了说明目的公开了本发明的优选实施方案,本领域的技术人员将理解:在不背离所附权利要求公开的本发明范围和实质的条件下,可以进行各种修改、添加和替换。
Claims (9)
1.一种制造包括嵌入式芯片的印刷电路板的方法,包括:
形成要插入芯片的中空部分和穿过覆铜层压板的通孔;
将芯片插入到中空部分;
对基板的整个表面进行镀覆;
在基板的两个表面上形成电路图案,以形成中央层;和
在基板上层叠一个或多个电路层和一个或多个绝缘层。
2.权利要求1所述的方法,其中将芯片插入中空部分还包括在芯片插入中空部分之前将粘合片附着到基板的一个表面上。
3.权利要求2所述的方法,其中镀覆基板整个表面包括去除粘合片。
4.权利要求3所述的方法,其中镀覆基板整个表面还包括在去除粘合片之后进行镀覆工艺。
5.权利要求1所述的方法,其中在基板的两个表面上形成电路图案来形成中央层包括蚀刻基板的两个表面,以在其上形成电路图案。
6.权利要求1所述的方法,其中层叠一个或多个电路层和一个或多个绝缘层包括:
可替代地在中央层上层叠一个或多个未固化树脂层和一个或多个电路层;
在基板的两个最外层上层叠铜箔层;
加热并压缩所层叠的未固化树脂层、电路层和铜箔层;和
在基板的铜箔层上形成电路图案。
7.一种包括嵌入式芯片的印刷电路板,包括:
中央层,穿过该层形成贯通孔和中空部分,其具有利用镀覆工艺固定且插入到中空部分的芯片和形成在中央层的两个表面上的电路图案;
绝缘层,其层叠在中央层的一个或两个表面上,并具有填充导电墨的贯通孔;和
电路层,其层叠在绝缘层上,并具有通孔以及通过贯通孔来电连接到中央层的镀覆层的电路图案。
8.权利要求7所述的方法,其中所述的绝缘层包括固化树脂层和未固化树脂层。
9.权利要求7所述的方法,其中所述的芯片包括无源元件或有源元件。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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KR1020040116809A KR100688769B1 (ko) | 2004-12-30 | 2004-12-30 | 도금에 의한 칩 내장형 인쇄회로기판 및 그 제조 방법 |
KR10-2004-0116809 | 2004-12-30 | ||
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- 2005-05-30 CN CN2005100730448A patent/CN1798479B/zh not_active Expired - Fee Related
- 2005-07-07 JP JP2005198737A patent/JP4061318B2/ja not_active Expired - Fee Related
- 2005-07-11 US US11/179,864 patent/US7282394B2/en not_active Expired - Fee Related
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CN101609830B (zh) * | 2008-06-16 | 2011-07-27 | 三星电机株式会社 | 包括嵌入其中的电子部件的印刷电路板及其制造方法 |
CN101998772A (zh) * | 2009-08-25 | 2011-03-30 | 三星电机株式会社 | 加工芯板的空腔的方法 |
CN101998772B (zh) * | 2009-08-25 | 2013-03-27 | 三星电机株式会社 | 加工芯板的空腔的方法和电子器件埋入式印刷电路板 |
CN103857173A (zh) * | 2012-10-18 | 2014-06-11 | 英飞凌科技奥地利有限公司 | 高效嵌入技术 |
CN103196593A (zh) * | 2013-03-22 | 2013-07-10 | 中国科学院电子学研究所 | 谐振式微机械压力传感器及传感器芯片的低应力组装方法 |
CN104284522A (zh) * | 2013-07-03 | 2015-01-14 | 太阳诱电株式会社 | 具空腔的基板的制造方法 |
CN104284522B (zh) * | 2013-07-03 | 2017-09-19 | 太阳诱电株式会社 | 具空腔的基板的制造方法 |
CN108617089A (zh) * | 2016-12-10 | 2018-10-02 | 宏启胜精密电子(秦皇岛)有限公司 | 内埋元件柔性电路板及其制造方法 |
CN108617089B (zh) * | 2016-12-10 | 2020-12-22 | 宏启胜精密电子(秦皇岛)有限公司 | 内埋元件柔性电路板及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20060145331A1 (en) | 2006-07-06 |
JP4061318B2 (ja) | 2008-03-19 |
JP2006190953A (ja) | 2006-07-20 |
US7282394B2 (en) | 2007-10-16 |
CN1798479B (zh) | 2011-06-15 |
KR100688769B1 (ko) | 2007-03-02 |
KR20060078118A (ko) | 2006-07-05 |
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