CN1398149A - 具有散热元件的印刷电路板,其制作方法和包含它的器件 - Google Patents

具有散热元件的印刷电路板,其制作方法和包含它的器件 Download PDF

Info

Publication number
CN1398149A
CN1398149A CN02124471A CN02124471A CN1398149A CN 1398149 A CN1398149 A CN 1398149A CN 02124471 A CN02124471 A CN 02124471A CN 02124471 A CN02124471 A CN 02124471A CN 1398149 A CN1398149 A CN 1398149A
Authority
CN
China
Prior art keywords
alloy sheets
circuit board
printed circuit
pcb
heating panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN02124471A
Other languages
English (en)
Other versions
CN100417310C (zh
Inventor
李圣揆
金容一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Innotek Co Ltd
Original Assignee
LG Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Electronics Inc filed Critical LG Electronics Inc
Publication of CN1398149A publication Critical patent/CN1398149A/zh
Application granted granted Critical
Publication of CN100417310C publication Critical patent/CN100417310C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0315—Oxidising metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1536—Temporarily stacked PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

公布了一种具有散热元件的印刷电路板，制作该印刷电路板的方法，以及包含该印刷电路板的半导体器件。该印刷电路板包括一个金属的散热板，具有设定硬度和用于接地和散热的合金板，在合金板的一个表面形成的电路图案层，该电路图案层具有电路图案并电气连接到合金板的通孔，以及通过在电路图案层和合金板上穿孔而形成的孔腔，其中半导体芯片通过该孔腔安装在散热板上。在合金板的表面或者散热板的表面有多个散热突起，合金板通过散热突起直接安装在散热板上。根据本发明，由半导体芯片产生的热量有效地散发到外面，并且降低了印刷电路板的高度。

Description

具有散热元件的印刷电路板，其制作方法和包含它的器件
技术领域
本发明涉及一种印刷电路板(PCB)，具体而言，涉及一种印刷电路板，其中半导体芯片通过在印刷电路上打孔形成的孔直接安装到散热板上，在散热板上整体地形成接地面，从而有效地将半导体芯片的热量散发到外面，同时降低印刷电路板的高度；一种制作该印刷电路板的方法；和包括该印刷电路板的半导体封装件。
背景技术
在工作过程中，很多半导体芯片产生热量。尤其是，用于高频和包含大规模集成电路的半导体芯片，在工作过程中产生大量的热量。产生的热量必需散发到外面，因此，在电子器件上安装散热器以将产生的热量散发到外面。
图1显示的是使用传统印刷电路板2的器件1的示意图。此器件1通常指的是球栅阵列(BGA)器件。下面参照图1详细描述使用传统印刷电路板2的器件1。
在印刷电路板2上安装有半导体芯片3。使用密封剂4对半导体芯片3进行胶边以防止其受周围环境的影响。焊球5安装在印刷电路板2的下表面。焊球5用于从外部设备传输信号和电能。半导体芯片3通过金线6在电气上连接到印刷电路板2，从而在半导体芯片3和印刷电路板2之间传输电信号。
散热器7安装在半导体芯片3的上表面。散热器用于将半导体芯片3产生的热量散发到外面。散热器7由诸如铝之类的导热金属制成。散热器7的下表面安装在半导体芯片3的上表面。散热器7的上表面露在外面。为了更有效地将所产生的热量散发到外面，在散热器7的上表面上形成多个散热突起，从而具有很大的表面积，将热量散发到外面。
在小型的半导体芯片3上集成了很多的功能设备。因此，在工作过程中，从具有多个功能设备的半导体芯片产生大量的热量。因此，散热器7用于散发产生的热量。
如果没有适当地散发热量，此热量会带走电子。从而半导体芯片3不能实现其特定的功能。因此，必须使用散热器7将半导体芯片3产生的热量散发到外面。
然而，带有散热器的传统器件具有如下的问题。
由于散热器7与印刷电路板2是分别形成的，散热器7安装在印刷电路板2上以形成器件1。因此，增加了器件1的高度。因此，很难使器件1小型化。
在制作印刷电路板2时，在印刷电路板2上形成的用于接地电路的接地板必须另外形成，因此增加了印刷电路板2的层数和使用印刷电路板2的器件1的高度。
由于具有半导体芯片3的印刷电路板2成为多层格式，增加了印刷电路板2的高度，从而增加了使用印刷电路板2的器件1的高度。
对于使用多层印刷电路板的情况，需要通过用于连接焊球到接地板的通孔。通过在印刷电路板上打孔形成通孔。通孔连接到接地板。因此，印刷电路板需要大面积用于形成通孔，从而限制了印刷电路板设计的多样性。
还有，对于没有将多层印刷电路板的散热层直接连接到半导体芯片的情况，还需要用于将半导体芯片产生的热量传输到热传导层的通孔。当然，印刷电路板需要附加的面积以形成用于传输热量的通孔，从而设计印刷电路板时也限制了多样性。
发明内容
因此，本发明致力于上述问题，本发明的目的是提供一种印刷电路板，一种制作该印刷电路板的方法，和一个包含该印刷电路板的半导体器件。在此印刷电路板中，一个合金板可导热地电气连接于在合金板上形成的信号层。合金板用作接地和散热，从而能够自由地设计印刷电路板和使得使用所述印刷电路板的器件小型化。
根据本发明的一个方面，可以通过具有散热元件的印刷电路板实现上述和其它的目的。印刷电路板包括金属制成的散热板，连接到散热板一个表面的合金板，所述的合金板具有指定的硬度，用来接地和散热，在合金板的一个表面形成有电路图案层，所述的电路图案层具有电路图案和电气连接到合金板的通孔，和一个通过在电路图案层和合金板打孔形成的孔腔。在此，通过该孔腔将半导体芯片安装在散热板上。
优选的是，能够在合金板的表面或者散热板的表面形成很多散热突起。合金板直接通过散热突起安装在散热板上。
根据本发明的另外一个方面，提供了一种制作具有散热元件的印刷电路板的方法。该方法包括如下步骤：使用一个插在中间的绝缘载体层将两个合金板彼此连接在一起，合金板用于接地和散热，将绝缘层和导电层连接在所述合金板的一个表面上，通过在绝缘层和导电层上打孔形成通孔，通过通孔将导电层电连接到合金板而形成镀层，在所述的导电层上形成一个电路图案层，通过分割绝缘载体层将带有电路图案层的两个合金板彼此分开，将一个散热板连接到合金板的其它表面上。
优选的是，制作具有散热元件的印刷电路板的方法还包括在将散热板连接到合金板的其它表面之前，通过在带有电路图案层的合金板上打孔形成孔腔。
优选的是，制作具有散热元件的印刷电路板的方法还包括在将散热板连接到合金板其它表面之前，在散热板的连接表面或合金板的连接板上形成多个散热突起。
根据本发明的另外一个方面，提供了一种半导体器件，包括：金属的散热板；连接到散热板一个表面的合金板，所述的合金板具有指定的硬度，并且用来接地和散热；在合金板的一个表面形成电路图案层，所述的电路图案层具有电路图案、多个连接焊盘，以及电连接到合金板的通孔；通过在电路图案层和合金板上打孔形成的用于露出散热板表面的孔腔；通过所述孔腔安装在散热板露出的表面上的半导体元件；用于将半导体元件电连接到电路图案层的连接焊盘的导电元件；以及用于填充孔腔的密封剂。
优选的是，可以在合金板的表面或者散热板的表面形成多个散热突起。合金板通过散热突起直接安装在散热板上。
本发明降低了印刷电路板的高度。还有，半导体芯片安装在孔腔中，从而降低了器件的整体高度。
散热板用作印刷电路板的一层。绝缘层和电路图案连续叠放在合金板上，散热板安装在合金板的下表面，从而制作了印刷电路板。由于电路图案与合金板电连接，合金板用于接地和散热。散热板用于散发半导体芯片所产生的热量，以及通过合金板将热量传输到外面。
还有，在散热板的表面形成散热突起。散热板通过散热突起直接安装在合金板的下表面。因此，具有散热突起的散热板用于接地，同时散热器将通过合金板传输的热量散发到外面，从而无需另外的接地板，并且使得印刷电路板的整体高度最小。
本发明有效地利用了印刷电路板的各层空间，并且使得印刷电路板的层数最少，从而简化了制作过程和降低了产品成本。
附图说明
由以下的详细说明，结合附图，可以更清楚地理解本发明上述和其它的目的、特征和其它优点。附图中：
图1显示的是使用传统印刷电路板的器件的示意图；
图2a到2i显示的是根据本发明一个优选实施例的印刷电路板的制作过程；
图3显示的是根据本发明一个优选实施例的使用印刷电路板的器件结构的截面图；
图4a到4d显示的是根据本发明另外一个优选实施例，在印刷电路板中所使用的散热板的制作过程；
图5显示的是根据本发明另外一个优选实施例，使用包含散热板的印刷电路板的器件的截面图；
图6显示的是根据本发明另外一个优选实施例，使用包含散热板的印刷电路板的器件的截面图。
优选实施例详细说明
图2a到2i显示的是根据本发明一个优选实施例的印刷电路板的制作过程。
下面，参照图2a到2i详细描述根据本发明一个优选实施例的印刷电路板的制作过程。
图2a显示的是两个合金板10，在其表面上，每一个都具有在其表面上形成的氧化层12。准备好由铜合金和铝合金制成的合金板10。合金板10用于接地和散热。如图2a所示，在金属板10的表面形成有氧化层12。在此，在金属板10的表面形成氧化层12的原因是氧化层12的形成使得金属板10的表面粗糙，从而可以轻易的安装到绝缘层30(图2b)或者绝缘载体20上(图2b)。
两个合金板10彼此联结。即，通过在合金板10和绝缘载体20之间插入释放膜25，将合金板10安装在绝缘载体20的上表面和下表面。从而，能够同时制作两个印刷电路板。此处，使用释放膜25能够容易地将两个印刷电路板彼此分开。
与合金板10相比，释放膜25的尺寸较小。即，释放膜25不是安装在合金板10的边缘。因此，两个合金板10的边缘直接安装到绝缘载体20，而两个合金板10的其它区域，例如，合金板10的中部，通过在其间插入的释放膜25安装到绝缘载体20。即，合金板10的中部没有和绝缘载体20接触。
在合金板10露出的氧化层12上形成绝缘层30。在绝缘层30上附着一层薄的铜层32。可选的是，可以在合金板10上安装具有在其一个表面上形成的铜层32的铜叠层板。
在铜层32上覆盖着蚀刻保护层40。蚀刻保护层40包括用于露出铜层32的窗口。这些窗口指的是蚀刻窗口34。随后，通过蚀刻去除由蚀刻窗口34露出的铜层32。当然，由蚀刻保护层40覆盖的铜层32没有被去除，仍然保留。
图2c显示的是合金板10，在其上，由蚀刻保护层的蚀刻窗口34露出的铜层32被去除，从而露出绝缘层30，而由蚀刻保护层40覆盖的铜层32没有被去除。
通过剥离的方法去除剩下的蚀刻保护层40。然后，去除由蚀刻窗口34所露出的绝缘层30，从而形成通孔36。通过去除露出的绝缘层30露出合金板10。图2d显示的是合金板10，其上已经形成通孔36。
这些通孔36可以通过光刻法形成，光刻法包括以下步骤：曝光步骤，显影步骤，和蚀刻步骤，或者使用激光形成。否则，可以通过钻孔使用机械方法形成通孔36。
在包含通孔36的绝缘层30上形成镀层50。随后，镀层50和铜层32一起用作电路图案。因此，优选的是，镀层50可以由铜制成。图2e显示的是合金板10，其中在绝缘层30和通孔36上形成镀层50。
此时，可以使用导电胶填充通孔36而不是镀层50，从而将通孔36电连接到合金板10上。
下一步，形成电路图案52。在镀层50上覆盖蚀刻保护层60。可以选择性地对覆盖的蚀刻保护层60进行去除或者蚀刻，从而去除电路图案52区域之外的镀层50和铜层32。
即，使用曝光胶片选择性地将蚀刻保护层60曝光，从而去除电路图案52之外的其它的蚀刻保护层60。去除通过选择性地去除蚀刻保护层60而露出镀层50和铜层32，从而，在合金板10的中部形成用于安装半导体芯片的孔腔82的窗口57(图2h)。图2f显示的是合金板10，其中选择性地去除了镀层和铜层32，并且形成了用于安装半导体芯片的孔腔的窗口57。
通过剥离去除覆盖在镀层50的电路图案上的蚀刻保护层60，而后，电路图案52保留在绝缘层30上。
为了形成多层的印刷电路板，在具有电路图案52的绝缘层30上形成第二绝缘层30’，然后，在第二绝缘层30’上形成镀层，通过重复图2b到2f的步骤形成印刷电路板的另一层，从而，可以在印刷电路板上形成多层。
在合金板10上覆盖光敏阻焊剂70，光敏阻焊剂70用于绝缘和保护最上面的电路图图案52。在合金板10上形成用于引线焊接的焊盘54和用于焊球焊接的球焊盘56。使用金(Au)对焊盘54的表面和球焊盘56的表面进行电镀。此处，在焊盘54和球焊盘56上没有覆盖光敏阻焊剂70。否则，在包含电路图案52，焊盘54和球焊盘56的合金板的整个表面覆盖光敏阻焊剂。然后，从焊盘54和球焊盘56上去除光敏阻焊剂。图2g显示的合金板10，其中，形成了焊盘54和球焊盘56，通过光敏阻焊剂70对电路图案52’进行绝缘。
在绝缘层20的上、下表面形成的两个印刷电路板80，通过分割绝缘载体20而彼此分开。由于合金板10的中部通过插入的剥离膜25安装到绝缘载体20，通过沿着图2h中的虚线分割绝缘载体20，即可容易地使得合金板10彼此分开。此方法由已经授予本发明申请人的美国专利第6,210,518号所揭示。
使用刳刨钻在各个印刷电路板80的中部形成用于安装半导体芯片的孔腔82。此处，通过在印刷电路板的中部打孔而形成孔腔82。图2h显示的印刷电路板80，在其上形成孔腔82。
在形成孔腔82之后，在合金板10的下表面安装散热板75，从而完成根据本发明一个优选实施例的印刷电路板的制作。此处，散热板75通过聚酯胶片77或者导电粘合剂安装在合金板10的下表面。散热板75用于将印刷电路板80和半导体芯片100(图3)产生的热量散发到外面。在散热板75露出的表面上形成涂层76。图2i显示的印刷电路板80，其中，散热板75安装在合金板10的下表面。
图3显示的是根据本发明的优选实施例，使用印刷电路板的器件结构的截面图。
参照图3详细描述根据本发明的优选实施例，使用印刷电路板80的器件。半导体芯片100通过印刷电路板80上的孔腔82安装在散热板75的上表面。
通过使用引线101将半导体芯片100的芯片焊盘(未示出)连接到印刷电路板80的焊盘54，从而将半导体芯片100电连接到印刷电路板80。使用密封剂将半导体芯片100、引线101和连接到引线101的焊盘54封闭起来，从而防止外界环境的干扰。然后，将焊球104连接到相应的球焊盘56。焊球104用于将本发明的器件电连接到外部设备。
在本发明的这个实施例中，印刷电路板80的散热板75用于将器件接地和将半导体芯片100产生的热量散发出去。
图4a到4d显示的是根据本发明另外一个优选实施例，在印刷电路板中所使用的散热板的制作过程。
下面，结合图4a到4d详细描述根据本发明另外一个优选实施例，印刷电路板所使用的散热板的制作过程。
准备好散热板175，在散热板175的下表面和侧表面形成涂层176。然后，如图4a所示，在散热板175的上表面形成干膜180。
如图4b所示，选择性地将干膜180曝光和显影，从而选择性地去除干膜而露出散热板175的表面。此处，在形成散热突起178的部分保留干膜180。
通过选择性去除干膜180，散热板175的露出的表面以指定的厚度蚀刻，从而形成散热突起178。图4c显示的散热板175，其中形成了多个散热突起178。
去除干膜180。使用绝缘材料177填充散热板175上表面散热突起之间的空隙。此处，利用不同的方法使用绝缘材料177填充这些空隙。例如，在散热板175的上表面覆盖绝缘材料177，然后在高温下熔化，从而填充散热突起178之间的空隙。还有，在散热板175的上表面安装绝缘膜，然后使用滚子之类的物体滚压，从而填充散热突起178之间的空隙。
填充了绝缘材料177的散热板175安装到图2所示过程制作的印刷电路板的下表面。图5和图6分别显示使用具有散热突起的散热板175的印刷电路板80的器件。
图5显示的是散热板177，其中在散热板177上表面的芯片安装区域没有形成散热突起178。图6显示的是散热板177，其中在散热板177的整个上表面的芯片安装区域形成了散热突起178。
尽管在本发明优选实施例的散热板175的表面上形成了散热突起178，但也可以在合金板的表面上形成散热突起。
如上所述，在散热板175的表面形成的散热突起178或者在合金板表面上形成的散热突起用于提高热传导。如果在散热板175或者合金板上没有形成任何散热突起，在散热板175和合金板之间插入粘合剂，从而降低热传导。
即，散热板175的散热突起178直接连接到芯片100或者合金板10，从而提高了热传导，并且有效地接地。
根据本发明的优选实施例，使用聚酯胶片177或者导电粘合剂填充散热板175的散热突起178之间的空隙。使用聚酯胶片177或者导电粘合剂将散热板175安装在合金板10的下表面。
下面，详细描述本发明的上述印刷电路板80的操作。
在印刷电路板80的中部形成用于安装半导体芯片100孔腔82。通过孔腔82将半导体芯片100安装在散热板75上。此处，在印刷电路板80上形成孔腔82之后，将散热板75安装在印刷电路板80的下表面。在此，在印刷电路板80上形成孔腔82的步骤非常简单。
即，由于只需通过在印刷电路板80上打孔形成孔腔82，因而形成孔腔82的步骤是很容易的。
根据本发明的优选实施例，通过在其间插入聚酯胶片77，将散热板75安装在印刷电路板80的下表面。因此，和使用粘合剂的传统印刷电路板相比，散热板75和印刷电路板80之间的粘合强度更为坚固。还有，在散热板75和印刷电路板80之间不会产生空隙，从而提高了器件的可靠性。
半导体芯片100安装在孔腔82中，从而使得器件的高度最小。
在制作印刷电路板80的过程中，合金板10和在合金板的上表面上形成的各层通过通孔36形成内部电连接和导热性，从而，合金板10用作接地和散热。
因此，通过使用本发明的合金板10，提高了接地能力，从而降低了合金板上形成的接地层的数目并且降低了印刷电路板80的整体高度。
通过散热板75，更有效的将半导体产生的热量和通过合金板传输的热量散发到外面。
根据图4到图6的本发明优选实施例，在散热板175的表面形成散热突起178。散热板175的散热突起178直接和合金板10的下表面接触。因此，具有散热突起178的散热板175用于接地，同时将通过合金板10传输的热量散发到外面，从而使得印刷电路板80的整体高度最小。
根据本发明的优选实施例，用于接地的合金板10通过通孔36与合金板10上形成的电路图案52进行电和热连接。因此，无需用于将焊球连接到接地板的传统通孔，从而更有效地利用了印刷电路板的空间。
还有，使得印刷电路板的层数最少，从而简化了制作过程和降低了产品成本。
虽然出于示例的目的公开了上述的本发明优选实施例，本领域的技术人员可以理解，在不脱离所附权利要求限定的本发明的范围和宗旨的情况下，可以进行各种改进、添加和替换。

Claims (13)

1.一种具有散热元件的印刷电路板，所述的印刷电路板(PCB)包括：
散热板；
连接到散热板一个表面的合金板，所述的合金板具有指定的硬度；
在合金板的一个表面上形成的电路图案层，所述的电路图案层具有电路图案和与合金板电连接的通孔；以及
电路图案层和合金板中的孔腔，用于露出散热板的一部分。
2.根据权利要求1的具有散热元件的印刷电路板，其特征在于，在合金板的下表面形成有多个散热突起，其中合金板通过散热突起直接连接在散热板上。
3.根据权利要求1的具有散热元件的印刷电路板，其特征在于，散热板将热量从电路图案传到合金板。
4.根据权利要求1的具有散热元件的印刷电路板，其特征在于，散热板的露出部分在散热板的一个表面上，半导体芯片安装所述孔腔中的散热板部分上。
5.根据权利要求1的具有散热元件的印刷电路板，其特征在于，合金板的高度至少是半导体元件高度的一半。
6.根据权利要求1的具有散热元件的印刷电路板，其特征在于，合金板用作印刷电路板的电气接地，并散发热量。
7.一种制作具有散热元件的印刷电路板的方法，包括：
使用一个插入的绝缘载体层将两个合金板彼此连接在一起，每一个所述的合金板用于散热；
将绝缘层和导电层连接在所述每个合金板的一个表面上；
通过在绝缘层和导电层上打孔形成通孔；
形成镀层，其通过所述的通孔将各个导电层连接到合金板；
在所述的每个导电层上形成电路图案层；
通过分割绝缘载体层将两个带有电路图案层的合金板彼此分开；以及
将散热板连接到至少一个合金板的另一表面上。
8.根据权利要求7的制作具有散热元件的印刷电路板的方法，其特征在于，使用绝缘载体层将两个合金板彼此连接在一起的步骤包括：
提供粘性部件；
在粘性元件的一侧或者多侧放置释放部件；以及
在释放元件上放置至少一个合金部件，所述至少一个合金部件的放置使得其一部分延伸到释放单元以外而接触粘性部件。
9.根据权利要求7的制作具有散热元件的印刷电路板的方法，其特征在于，绝缘载体层包括位于粘性部件两侧的释放部件，其中粘性部件延伸到释放部件以外而接触两个合金板中的每一个。
10.根据权利要求7的制作具有散热元件的印刷电路板的方法，其特征在于，将在导电层形成电路图案层的步骤重复预定的次数，其中所述预定的次数等于电路图案层的所需数目。
11.根据权利要求7的制作具有散热元件的印刷电路板的方法，其特征在于还包括，在将散热板连接到所述至少一个合金板的另一表面之前，通过在电路图案层和合金板上打孔而形成孔腔。
12.根据权利要求7的制作具有散热元件的印刷电路板的方法，其特征在于还包括，在连接散热板之前，在散热板的连接表面和合金板的另一表面中的一个上形成多个散热突起。
13.一种半导体器件，包括：
金属制成的散热板；
连接到散热板一个表面的合金板，所述的合金板作为参考电压电平，并且用来散热；
在合金板的一个表面上形成电路图案层，所述的电路图案层具有电路图案、多个连接焊盘、以及与合金板电连接的通孔；
在电路图案层和合金板中用于露出散热板一个表面的孔腔；
安装在孔腔中散热板露出的表面上的半导体元件；以及
用于将半导体元件电连接到电路图案层的连接焊盘的导电元件。
CNB021244715A 2001-07-18 2002-06-28 具有散热元件的印刷电路板,其制作方法和包含它的器件 Expired - Fee Related CN100417310C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR43220/2001 2001-07-18
KR10-2001-0043220A KR100432715B1 (ko) 2001-07-18 2001-07-18 방열부재를 갖는 인쇄회로기판 및 그 제조방법

Publications (2)

Publication Number Publication Date
CN1398149A true CN1398149A (zh) 2003-02-19
CN100417310C CN100417310C (zh) 2008-09-03

Family

ID=19712261

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB021244715A Expired - Fee Related CN100417310C (zh) 2001-07-18 2002-06-28 具有散热元件的印刷电路板,其制作方法和包含它的器件

Country Status (4)

Country Link
US (2) US6803257B2 (zh)
KR (1) KR100432715B1 (zh)
CN (1) CN100417310C (zh)
TW (1) TW551003B (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102595768A (zh) * 2011-01-14 2012-07-18 亚旭电脑股份有限公司 电路板
CN103021877A (zh) * 2012-12-22 2013-04-03 中国船舶重工集团公司第七0九研究所 一种采用双路径传热的高密度芯片散热方法
CN103972229A (zh) * 2013-01-31 2014-08-06 飞思卡尔半导体公司 形成带有散热器的半导体器件组合件的方法
TWI505765B (zh) * 2010-12-14 2015-10-21 Unimicron Technology Corp 線路板及其製造方法
CN105682358A (zh) * 2014-12-05 2016-06-15 英飞凌科技奥地利有限公司 包括印刷电路板和金属工件的器件
CN113284863A (zh) * 2021-07-09 2021-08-20 惠州市金百泽电路科技有限公司 一种用于芯片的嵌入式封装结构及其制作方法
CN114980573A (zh) * 2021-02-25 2022-08-30 深南电路股份有限公司 电路板的制作方法、电路板及电子装置

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040004277A1 (en) * 2002-07-03 2004-01-08 Chung-Che Tsai Semiconductor package with reinforced substrate and fabrication method of the substrate
JP2004273968A (ja) * 2003-03-12 2004-09-30 Fujitsu Ltd 記録ディスク駆動装置およびフレキシブルプリント基板ユニット
TWI239603B (en) * 2003-09-12 2005-09-11 Advanced Semiconductor Eng Cavity down type semiconductor package
US7135357B2 (en) * 2003-10-06 2006-11-14 E. I. Du Pont De Nemours And Company Process for making an organic electronic device having a roughened surface heat sink
US8395253B2 (en) * 2004-01-28 2013-03-12 International Rectifier Corporation Hermetic surface mounted power package
KR100585227B1 (ko) 2004-03-12 2006-06-01 삼성전자주식회사 열 방출 특성이 개선된 반도체 적층 패키지 및 이를이용한 메모리 모듈
JP4575147B2 (ja) * 2004-12-28 2010-11-04 株式会社東芝 半導体装置
US7344915B2 (en) * 2005-03-14 2008-03-18 Advanced Semiconductor Engineering, Inc. Method for manufacturing a semiconductor package with a laminated chip cavity
KR100744993B1 (ko) * 2006-01-25 2007-08-02 삼성전기주식회사 다층 인쇄회로기판 및 그 제작방법
US7952834B2 (en) * 2008-02-22 2011-05-31 Seagate Technology Llc Flex circuit assembly with thermal energy dissipation
DE102008001414A1 (de) * 2008-04-28 2009-10-29 Robert Bosch Gmbh Substrat-Schaltungsmodul mit Bauteilen in mehreren Kontaktierungsebenen
JP5352437B2 (ja) * 2009-11-30 2013-11-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8492911B2 (en) * 2010-07-20 2013-07-23 Lsi Corporation Stacked interconnect heat sink
US8669777B2 (en) 2010-10-27 2014-03-11 Seagate Technology Llc Assessing connection joint coverage between a device and a printed circuit board
TWI408837B (zh) * 2011-02-08 2013-09-11 Subtron Technology Co Ltd 封裝載板及其製作方法
US20120286416A1 (en) * 2011-05-11 2012-11-15 Tessera Research Llc Semiconductor chip package assembly and method for making same
US9230899B2 (en) * 2011-09-30 2016-01-05 Unimicron Technology Corporation Packaging substrate having a holder, method of fabricating the packaging substrate, package structure having a holder, and method of fabricating the package structure
JP6021504B2 (ja) * 2012-08-08 2016-11-09 キヤノン株式会社 プリント配線板、プリント回路板及びプリント回路板の製造方法
US10433413B2 (en) * 2014-08-15 2019-10-01 Unimicron Technology Corp. Manufacturing method of circuit structure embedded with heat-dissipation block
DE102015104956A1 (de) 2015-03-31 2016-10-06 Infineon Technologies Ag Gedruckte Leiterplatte mit einem Leiterrahmen mit eingefügten gehäusten Halbleiterchips
US10849234B2 (en) 2016-04-15 2020-11-24 3M Innovative Properties Company Preparation of electrical circuits by adhesive transfer
US10718963B1 (en) 2016-11-16 2020-07-21 Electro-Optics Technology, Inc. High power faraday isolators and rotators using potassium terbium fluoride crystals
KR102040493B1 (ko) 2017-05-31 2019-11-05 (주)제이엠씨 인쇄회로기판용 방열장치 및 이의 제조방법
WO2021074978A1 (ja) * 2019-10-15 2021-04-22 三菱電機株式会社 半導体装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6097089A (en) * 1998-01-28 2000-08-01 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package
US4280409A (en) * 1979-04-09 1981-07-28 The United States Of America As Represented By The Secretary Of The Navy Molten metal-liquid explosive device
JP2796636B2 (ja) * 1989-10-30 1998-09-10 イビデン株式会社 電子部品搭載用基板
US5158912A (en) * 1991-04-09 1992-10-27 Digital Equipment Corporation Integral heatsink semiconductor package
US5388027A (en) * 1993-07-29 1995-02-07 Motorola, Inc. Electronic circuit assembly with improved heatsinking
JPH07302866A (ja) * 1994-04-28 1995-11-14 Nippon Steel Corp 半導体装置および該装置用ヒートスプレッダー
FR2735648B1 (fr) * 1995-06-13 1997-07-11 Bull Sa Procede de refroidissement d'un circuit integre monte dans un boitier
US5633533A (en) * 1995-07-26 1997-05-27 International Business Machines Corporation Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
US5844168A (en) * 1995-08-01 1998-12-01 Minnesota Mining And Manufacturing Company Multi-layer interconnect sutructure for ball grid arrays
JP3382482B2 (ja) * 1996-12-17 2003-03-04 新光電気工業株式会社 半導体パッケージ用回路基板の製造方法
US6020637A (en) * 1997-05-07 2000-02-01 Signetics Kp Co., Ltd. Ball grid array semiconductor package
US6395582B1 (en) * 1997-07-14 2002-05-28 Signetics Methods for forming ground vias in semiconductor packages
KR19990070625A (ko) * 1998-02-23 1999-09-15 구본준 반도체 패키지 및 그 제조방법
JPH11274355A (ja) * 1998-03-19 1999-10-08 Sumitomo Metal Electronics Devices Inc 放熱板付きプラスチックパッケージ
KR100302652B1 (ko) * 1998-09-11 2001-11-30 구자홍 플렉시블인쇄회로기판의제조방법및그방법으로생산한플렉시블인쇄회로기판
KR100319624B1 (ko) * 1999-05-20 2002-01-09 김영환 반도체 칩 패키지 및 그 제조방법
US6184580B1 (en) * 1999-09-10 2001-02-06 Siliconware Precision Industries Co., Ltd. Ball grid array package with conductive leads
JP2001168226A (ja) * 1999-12-14 2001-06-22 Shinko Electric Ind Co Ltd 半導体パッケージ及び半導体装置
KR20010057046A (ko) * 1999-12-17 2001-07-04 이형도 캐비티를 갖는 패키지 기판

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI505765B (zh) * 2010-12-14 2015-10-21 Unimicron Technology Corp 線路板及其製造方法
CN102595768A (zh) * 2011-01-14 2012-07-18 亚旭电脑股份有限公司 电路板
CN103021877A (zh) * 2012-12-22 2013-04-03 中国船舶重工集团公司第七0九研究所 一种采用双路径传热的高密度芯片散热方法
CN103021877B (zh) * 2012-12-22 2016-03-09 中国船舶重工集团公司第七0九研究所 一种采用双路径传热的高密度芯片散热方法
CN103972229A (zh) * 2013-01-31 2014-08-06 飞思卡尔半导体公司 形成带有散热器的半导体器件组合件的方法
CN105682358A (zh) * 2014-12-05 2016-06-15 英飞凌科技奥地利有限公司 包括印刷电路板和金属工件的器件
US10117321B2 (en) 2014-12-05 2018-10-30 Infineon Technologies Austria Ag Device including a printed circuit board and a metal workpiece
CN105682358B (zh) * 2014-12-05 2019-08-13 英飞凌科技奥地利有限公司 包括印刷电路板和金属工件的器件
CN114980573A (zh) * 2021-02-25 2022-08-30 深南电路股份有限公司 电路板的制作方法、电路板及电子装置
CN113284863A (zh) * 2021-07-09 2021-08-20 惠州市金百泽电路科技有限公司 一种用于芯片的嵌入式封装结构及其制作方法

Also Published As

Publication number Publication date
US6803257B2 (en) 2004-10-12
US20050023030A1 (en) 2005-02-03
KR20030008530A (ko) 2003-01-29
KR100432715B1 (ko) 2004-05-24
CN100417310C (zh) 2008-09-03
US7098533B2 (en) 2006-08-29
US20030015348A1 (en) 2003-01-23
TW551003B (en) 2003-09-01

Similar Documents

Publication Publication Date Title
CN1398149A (zh) 具有散热元件的印刷电路板,其制作方法和包含它的器件
TWI437949B (zh) A wiring board provided with an electronic component, and a heat dissipation method of a wiring board provided with an electronic component
EP1761119B1 (en) Ceramic capacitor
US6219253B1 (en) Molded electronic package, method of preparation using build up technology and method of shielding
CN100345466C (zh) 元件内置型多层基板
KR100912051B1 (ko) 인쇄기판 및 인쇄기판의 제조방법
CN1230894C (zh) 半导体封装及其制造方法
KR100751995B1 (ko) 인쇄회로기판 및 그 제조방법
CN1543674A (zh) 带有埋设电感器的无引线芯片承载器的制造结构和方法
CN1798479A (zh) 包括嵌入式芯片的印刷电路板及其制造方法
CN1925722A (zh) 包括嵌入的陶瓷电容器的布线板结构
JP2008103615A (ja) 電子部品搭載多層配線基板及びその製造方法
US20070057375A1 (en) Multilayered wiring substrate and manufacturing method thereof
CN1332598A (zh) 具有用于安装电子部件的空腔的印刷线路板及其制造方法
JP3953122B2 (ja) 回路カード及びその製造方法
CN1332597A (zh) 电子元件设备及其制造方法
CN1489429A (zh) 制造电路板和通信设备的方法
CN1314071A (zh) 电路形成基板制造方法及电路形成基板及碳系列片
JP4987231B2 (ja) 熱伝導性基板パッケージ
CN111031687A (zh) 制备散热电路板的方法
JP2010062199A (ja) 回路基板
JP7131740B2 (ja) プリント回路基板及びパッケージ
CN101069283A (zh) 封装的热能管理装置以及制造这种装置的方法
US11545412B2 (en) Package structure and manufacturing method thereof
CN2662455Y (zh) 电气封装体

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: LG INNOTEK CO., LTD.

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20100603

Address after: Seoul, South Kerean

Co-patentee after: IG Innotek Co., Ltd.

Patentee after: LG Electronics Inc.

Address before: Seoul, South Kerean

Patentee before: LG Electronics Inc.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080903

Termination date: 20190628

CF01 Termination of patent right due to non-payment of annual fee