TW551003B - Printed circuit board with a heat dissipation element, method for manufacturing the printed circuit board, and package comprising the printed circuit board - Google Patents

Printed circuit board with a heat dissipation element, method for manufacturing the printed circuit board, and package comprising the printed circuit board Download PDF

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Publication number
TW551003B
TW551003B TW091115755A TW91115755A TW551003B TW 551003 B TW551003 B TW 551003B TW 091115755 A TW091115755 A TW 091115755A TW 91115755 A TW91115755 A TW 91115755A TW 551003 B TW551003 B TW 551003B
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TW
Taiwan
Prior art keywords
circuit board
printed circuit
heat
heat sink
sheet
Prior art date
Application number
TW091115755A
Other languages
English (en)
Inventor
Sung-Gue Lee
Yong-Il Kim
Original Assignee
Lg Electronics Inc
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Filing date
Publication date
Application filed by Lg Electronics Inc filed Critical Lg Electronics Inc
Application granted granted Critical
Publication of TW551003B publication Critical patent/TW551003B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
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    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

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Description

551003 A7 一 ~ ------------— __ 五'發明説明（1) 【發明背景】 2^_發明領域 本發明有關一種印刷電路板（PCB )，尤其有關一種印 刷電路板、其製造方法、及包含此種印刷電路板之半導體 封裝。此種印刷電路板上經由打孔而形成一空腔，通過空 腔可將一半導體晶片直接安裝在一熱沉薄板上；熱沉薄板 上並一體形成一接地面，藉此將半導體晶片之生熱有效散 逸至外側，並減少印刷電路板高度。 1·相關技術說明 許多半導體晶片在操作期間產生熱量。更明確地說， 以高頻狀態使用並包括大型積體電路的半導體晶片，會在 操作期間產生大量的熱。所產生的熱必須逸散到外侧。因 此，電子封裝上接設有熱沉，以使生熱逸散到外側。 圖1為一使用習式印刷電路板2之封裝1的概略圖。 此種封裝1通常稱為球拇陣列（B G A)封裝。以下參照圖1 詳細說明此種使用習式印刷電路板2的封裝1。 經濟部智慧財產局員工消費合作社印製 印刷電路板2上安裝一半導體晶片3。半導體晶片3 係用密封劑4洗鑄，以防周遭環境的侵害。印刷電路板2 之下表面接設多數焊球5，用以傳輸來自外部器件之信號 及電力。半導體晶片3係利用金絲引線6而與印刷電路 板2導通，藉此在半導體晶片3與印刷電路板2間傳輸 電訊。 半¥體曰曰片3之上表面上’安裝一熱沉7。熱沉7可 將半導體晶片3產生的熱逸散到外側。熱沉7係用諸如 4 551003 五、發明説明（2) ，等之導熱金屬製成。熱沉7之下表面係接設在半導體 片之上表面，其上表面則暴露在外。為了更有效地 將生熱逸散到外侧，熱沉7之上表面上可形成複數個散 熱突體8以具備大表面積，使熱量逸散到外侧。 小型的半導體晶片3上整合了大量的功能性器件。因 此，具有功能性器件的半導體晶片3在操作期間產生高 量的熱。熱沉7即是用來逸散所產生的熱量。 若未適當散熱，熱量將會激勵電子，使半導體晶片3 無法發揮其特定的效能。因此，必須使用熱沉7使晶片3 產生的熱逸散到外側。 然而’包括熱沉的習式封裝有以下數種缺點。 由於熱沉7係與印刷電路板2分開形成，所以熱沉7 疋接設在印刷電路板2以形成封裝1。因此，封裝χ的高 度增加而不易微型化。 製造印刷電路板2時，必須另外形成一接地面，以使 印刷電路板2上形成的電路接地。如此將增加印刷電路 板2的層數及使用此種印刷電路板2的封裝1的高度。 由於具有半導體晶片3的印刷電路板2變成多層式， 其高度增加’也因此增加使用此種印刷電路板2的封裝工 的高度。 若是使用多層式印刷電路板時，需要穿孔連接焊球與 接地面。穿孔係經由印刷電路板上打孔而形成的，並與接 地面連通。因此，印刷電路板需要較大的面積以形成穿孔， 使印刷電路板的設計多樣性受到限制。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 請ί 先丨 閲 讀 ft 面「 之 注 再 % 本 經濟部智慧財產局員工消費合作社印製 551003 A7 —-----------B7 __ 五、發明説明（3) 此外’若多層式印刷電路板的散熱層並非直接與半導 體晶片連接時’還進一步需要其他穿孔，以使晶片產生的 熱傳运到散熱層。當然，印刷電路板需要額外的面積以形 成傳熱的穿孔，也因此限制了印刷電路板的設計多樣性。 【發明概要】 因此’本發明係針對上述問題而提出，且其目的在於 提供一種印刷電路板、其製造方法、及包含此種印刷電路 板之半導體封裝。在此種印刷電路板中，係包括一合金薄 板’此合金薄板與設於其上方的信號層連接而可導電與導 熱。合金薄板可供接地與散熱之用，因此印刷電路板的設 计不受限制，使用此種印刷電路板的封裝亦可微型化。 根據本發明層面之一，藉由提供具有散熱元件之印刷 電路板，可以達成上述及其他目的。此種印刷電路板包括 一金屬製熱沉薄板，一接設在熱沉薄板表面之一、具有一 指定硬度、並可用於接地和散熱的合金薄板，一設在合金 薄板表面之一上、具有與合金薄板導通之電路圖案及辅助 孔的電路圖案層，及一藉由電路圖案層與合金薄板打孔而 形成的空腔。其中，一半導體晶片經由該空腔安裝在該熱 沉薄板上。 較佳是’該合金薄板之表面或該熱沉薄板之表面上可 形成多數散熱突體。該合金薄板係利用散熱突體直接與熱 沉薄板連接。 根據本發明另一層面，其中提供一種方法，用以製造 具有散熱元件之印刷電路板。此方法包括之步驟為：將二 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） " --- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 551003 A7 經濟部智慧財產局員工消費合作社印製 五、發明説明（4 ) 片可用於接地與散熱的合金薄板，利用其間夾設之絕緣載 體層彼此連接；將一絕緣層與一鋼層接設在該合金薄板之 一表面；在絕緣層與銅層上打孔以形成輔助孔；形成一電 鍍層以經由輔助孔導通銅層與合金薄板；在銅層上形成一 電路圖案層；分割絕緣載體層以分開具有電路圖案層的二 片合金薄板；以及，將一熱沉薄板接設在合金薄板之另一 表面。 較佳是，以上印刷電路板製造方法，可在該熱沉薄板 接設於合金薄板之另一表面前，進而包括下列步驟··將具 有電路圖案層的合金薄板打孔，以形成一空腔。 此外，以上印刷電路板製造方法，最好可在該熱沉薄 板接設於合金薄板之另一表面前，進而包括下列步驟：在 熱沉薄板之可連接表面或在合金薄板之可連接表面上形成 多數散熱突體。 根據本發明再一層面，其中提供一種半導體封裝。此 種封裝包括一金屬製熱沉薄板，一接設在熱沉薄板之一表 面、具有一指定硬度、並可用於接地和散熱的合金薄板， 一設在合金薄板之一表面上、具有與合金薄板導通之電路 圖案、多數連接墊及輔助孔的電路圖案層，一藉由電路圖 案層與合金薄板打孔而形成、並用以露出熱沉薄板表面的 空腔，一經由空腔安裝在熱沉薄板外露表面上之半導體晶 片，一導通半導體元件與電路圖案層連接墊之導電元件， 及充填空腔之密封劑。較佳是，合金薄板之表面或熱沉薄板之表面上設有多
(請先閱讀背面之注意事項存填寫本頁)
-41T 4. 乃1〇〇3 A7 --- - _ 五、發明説明（5 ) ^ ---- 數散熱突體。合金薄板係以散熱突體直接與熱沉薄板連 接。 根據本發明製作之印刷電路板，其高度減少。此外， 半導體晶片係安裝在空腔内，因而減少封裝的整體高度。 /熱沉薄板係用作印刷電路板的一層◊絕緣層與電路圖 案係連、$堆疊在合金薄板上，熱沉薄板則接設在合金薄板 之下表面從而製出印刷電路板。由於電路圖案係與合金 薄板導通，所以合金薄板可用來接地及散熱。熱沉薄板則 則可將半導體晶片的生熱與經由合金薄板傳導的熱逸散至 外側。 此外，政熱突體係設在熱沉薄板之表面上。熱沉薄板 則以散熱突體直接與合金薄板之下表面連接。因此，具有 散熱突體之熱沉薄板可作為接地及熱沉，使經由合金薄板 傳導的熱逸散至外側而不需額外的接地面，並使印刷電路 板之整體高度最小化。 根據本發明之印刷電路板，其各層的空間獲得更有效 的利用，而且印刷電路板的層數減至最少，使製程簡化並 降低生產成本。 【圖式簡要說明】 本發明上述及其他目的、特徵與優點，可藉以下參照 附圖所作之詳細說明而更加清晰。附圖包括： 圖1為使用習式印刷電路板之封裝的概略圖； 圖2 a至圖2 i顯示根據本發明一實施例之印刷電路 板製程； _^____ 8 本紙張尺度適财關家辟（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本買) 訂 經濟部智慧財產局員工消費合作社印製 551003 A7 ---—-—---------------Β7 五、發明説明（6 ) " ———〜 ---- 圖3為-封裝構造剖視圖，其中使用根據本發明一實 施例之印刷電路板； (請先閲讀背面之注意事項再填寫本頁) Θ 至圖4 d顯示根據本發明另一實施例之印刷電 路板中，其使用的熱沉薄板之製程； 圖5為一封裝之剖視圖’其中使用根據本發明另一實 施例中包括熱沉薄板之印刷電路板；以及 經濟部智慧財產局員工消費合作社印製 圖6為一封裝之剖視圖，其中使用根據本發明再一實 施例中包括熱沉薄板之印刷電路板。 【圖號說明】 1 封裝 2 印刷電路板 3 半導體晶片 4 密封劑 5 烊球 6 金絲引線 7 熱沉 8 散熱突體 10 合金薄板 12 氧化物層 20 絕緣載體 25 離形膜 30 絕緣層 30f 第二絕緣層 32 銅層 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 551003 A7 B7 經濟部智慧財產局員工消費合作社印製 、發明説明（7) 34 浸蝕開窗 36 輔助孔 40 抗#劑 50 電鍍層 52 電路圖案 52 f 電路圖案 54 接合塾 56 焊球墊 57 開窗 60 抗姓劑 70 光致焊錫保護層 75 熱沉薄板 7 6 披覆層 77 預浸物 80 印刷電路板 82 空腔 100 半導體晶片 101 引線 102 密封劑 104 焊球 17 5 熱沉薄板 17 6 彼覆層 177 絕緣材料 178 散熱突體 (請先閲讀背面之注意事項再填寫本頁)
本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 551003 A7 _______B7 五、發明説明（8 ) " 180 乾膜 【較佳實施例說明】 圖2 a至圖2 i顯示根據本發明一實施例之印刷電路 板製程。 以下參照圖2a至圖2i詳細說明根據本發明一實施 例之印刷電路板製程。 圖2a顯示二片合金薄板1〇,每片薄板之表面上形成 一氧化物層12。首先備製以銅合金與鋁合金製成之合金 薄板10。合金薄板10可用於接地及散熱。如圖2a所示， 合金薄板10的表面上形成一氧化物層12。在合金薄板10 上形成乳化物層12的原因在於’氧化物層12的形成可 使合金薄板10表面粗糙而較易與絕緣層30 (見圖2b)或 絕緣載體20 (見圖2b)連接。 將兩片合金薄板1 0彼此接合。亦即，在合金薄板1〇 與絕緣載體2 0間夾設一離形膜2 5，將合金薄板i Q接設 於絕緣載體20之上表面及下表面。藉此可同時製造兩塊 印刷電路板。利用離形膜25可使兩塊印刷電路板輕易分 離形膜25之尺寸略小於合金薄板之尺寸ό亦即， 離形膜25並未附著在合金薄板1〇的邊緣。因此，兩片 合金薄板10的邊緣係直接接設於絕緣載體2◦，而兩片 合金薄板10的其餘部位，亦即，兩片合金薄板10的中 央，則隔著夾設之離形膜25而與絕緣載體20連接。亦 即，合金薄板1 〇的中央並不接觸絕緣載體2〇。 11 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閲讀背面之注意事項再填寫本頁)
551003 五、發明説明（9 ) 在合金薄板10之外露 在板1Q上連接設有鋼層32表面之鋼層壓板。 數巧广層32上披覆一層抗钱劑40。抗兹劑4。包括多 數開窗，以便露出銅層^ 匕祜夕 ^ 2。以下將此等開窗稱為浸蝕開 ^湘魏去除從浸㈣窗34外露的鋼舞32。 被抗_ 4(3坡㈣_ 32並未去除 圖&顯示的合金薄板1〇中，從抗姓劑_、留二 34外露的銅層32已祜以 -Η0次蝕開窗 ^ Α 被去除，因此露出絕緣層30，而被 抗姓劑40披覆的銅層32則並未去除。 將殘㈣抗_ 4Q新除。然後，去除從浸㈣窗％ =絕緣層3。，藉此形成多數輔助孔％。去除外露的 、、錄層30可使合金薄板1〇外露。圖2續示的合金薄板 10中，已形成輔助孔36。 利用光_處理法可形成此等輔助孔36。光刻餘處 理法包括曝光步驟、顯影步驟 '及浸餘步驟。或者亦可使 用雷射形成辅助孔36。否則，亦可利用鑽孔器以機械方 式形成輔助孔3 6。 經 濟 部 智 慧 財 產 局 消 費 合 作 社 印 製 在絕緣層30包括辅助孔36的部位上，形成一電鐘 層50。電鍍層50稍後將與銅層32 —同作為電路圖案。 因此’電鍍層50最好可用銅製成。w 2e顯示的合金薄 板1〇中*，已於絕緣層30及輔助孔36上形成電鑛層5〇。 此袼，可用一種導電貧而非電鍍層5〇來充填辅助孔 3 6 ’使輔助孔3 6與合金薄板1 〇導通。
551003 經濟部智慧財產局員工消費合作社印製 A7 五、發明説明（10) 其次’形成電路圖案52。在電鍍層50上彼覆一層抗 蝕劑60。選擇性地去除與浸蝕所披覆的抗蝕劑6Q，藉此 去除電路圖案之外的電鍍層50與鋼層32部位。 亦即’使用一曝光膜讓抗蝕劑60選擇性地暴露在光 線中，然後使抗蝕劑60顯影，藉此去除抗蝕劑6Q在電 路圖案52以外的部位。然後去除經由選擇性去除抗蚀劑 而外露的電锻層50與銅層32。如此可在合金薄板1〇 之中央部位上，形成一開窗5 7。開窗5 7係用以形成一 空腔82(見圖2h)，以供安裝一半導體晶片。圖2f顯示 的a金溥板iq中’已選擇性地去除電鍍層5〇與銅層32， 並已开> 成半導體晶片安裝空腔用的開窗57。 接著剝除電鍍層50之電路圖案52上披覆的抗蝕劑 60°於是，將電路圖案52留在絕緣層30上。， 為了形成多層式印刷電路板，所以在設有電路圖案5 2 之絕緣層30上形成第二絕緣層3〇,。然後在第二絕緣層 3〇’上形成一電鍍層。重複圖2b至圖2f所示步驟，即 可形成另一層印刷電路板。藉此可在印刷電路板上形成多 層。 接著在合金薄板10上披覆一光致焊鍚保護層7〇。光 致焊鍚保護層7〇可隔絕與保護最上層的電路圖案52。 並在合金薄板10上形成引線接合用的接合墊與焊球 接合用的焊球墊56。接合墊54的表面與焊球墊56的表 面都鍍上黃金（Au)。此處，接合墊54與焊球墊56上並 未彼覆光致焊錫保護層7 〇。否則，合金薄板1 〇的整體 (請先閲讀背面之注意事項再填寫本頁)
551003 A7 ,____ B7 五、發明説明（11) 表面上，包括電路圖案52、接合墊54及焊球墊56,都 要彼覆光致焊錫保護層。然後，從接合墊5 4與烊球墊5 6 去除光致焊錫保護層。圖2g顯示的合金薄板1〇中，已 形成接合墊54與焊球墊56，並已用光致焊錫保護層7〇 隔絕電路圖案52f。 分割絕緣載體2 0，將絕緣載體2 0上、下表面上形成 兩塊印刷電路板80彼此分開。由於合金薄板1〇的中央 部位係隔著夾設於合金薄板與絕緣載體2〇間的可剝 除膜25而與絕緣載體連接，所以沿著圖2h所示之點線 分割絕緣載體2〇，即可輕易分開二片合金薄板。授予 本發明申請人之美國專利號6/21〇,518，即揭示上述方 法。 用於安裝半導體晶片的空腔82,係使用起槽鑽設於 每一印刷電路板80之中央。此處是在印刷電路板8〇的 中央打孔而形成空腔8 2。圖2h顯示的印刷電路板8 〇中 已形成空腔8 2。 形成空腔82後，在合金薄板之下表面接設一熱 >儿薄板7 5 ’完成根據本發明一實施例印刷電路板8 〇之 製造。在此，熱沉薄板75係利用一種預浸物（prepreg) 77 或導電黏劑接設在合金薄板丄〇之下表面^熱沉薄板7 5 之作用係將印刷電路板8 Q及半導體晶片1 0 0 (見圖3 )的 生熱逸散至外側。在熱沉薄板75之外露表面上形成一坡 覆層76。圖2i顯示之印刷電路板8〇中，已於合金薄板 1 0之下表面接設熱沉薄板7 5。 14 本紙張尺見格(-- (請先閱讀背面之注意事項再填寫本頁) _ |_ —τι. 訂 經濟部智慧財產局員工消費合作社印製 551003 A7 . _— B7 五、發明説明（12) ' --一~*-- 圖3為-剖視圖，其中顯示使用根據本發明一實施例 之印刷電路板的封裝構造。 ，…、Η 3詳細說明使用根據本發明一實施例印刷 電路板之封裝。半導體晶片丄Q Q係經由印刷電路板8 〇之 空腔82，安裝在熱沉薄板75之上表面。 藉由引線101連接半導體晶片1〇〇之晶片塾（圖中未 示）與印刷電路板8〇之接合塾54，使半導體晶片1〇〇與 印刷電路板80導通。使用密封劑1〇2澆禱半導體晶片 1〇〇、引線ιοί、及與引線101連接之接合墊54，以免 它們受到周遭環境的侵害。接著將焊球1〇4接設在對應 的烊球墊56上。焊球1〇4係用於導通本發明之封裝與一 外部器件。 在本發明此一實施例中，印刷電路板8〇之熱沉薄板 75係用於封裝接地及半導體晶片之生熱逸散。 圖4 a至圖4 d顯示根據本發明另一實施例之印刷電 路板中使用的熱沉薄板之製程。 以下參照圖4 a至圖4 d詳細說明根據本發明另一實 施例之印刷電路板中使用的熱沉薄板之製程。 首先備製一熱沉薄板I75。在熱沉薄板175之下表 面及側表面上形成一披覆層1 7 6。然後，如圖4 a所示， 在熱沉薄板I75之上表面形成一乾膜180。 如圖4b所示，讓乾膜180選擇性地曝光與顯影，藉 此選擇性地去除乾膜180並露出熱沉薄板175之表面。 此處係讓乾膜180留在欲形成散熱突體178的部位。 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)
、1T 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 551003 A7 --------- B7___ 五、發明說明（13) 經由選擇性去除乾膜180而外露的熱沉薄板175表 面’經浸蝕一指定深度而形成多數散熱突體178。圖化 顯不的熱沉薄板n5中，已形成多數散熱突體178。 去除乾膜180。使用一絕緣材料177充填熱沉薄板 175上表面各散熱突體1?8間的空間。此處可使用多種 不同方法將絕緣材料177充填在此等空間内。例如，可 將絕緣材料177披覆在熱沉薄板175之上表面，然後在 高溫下溶解之，使它充填在散熱突體178間的空間。接 著，在熱沉薄板175之上表面安裝一絕緣膜，並用輥子 之類的物件按壓，充填散熱突體1 7 8間的空間。 將填妥絕緣材料1 7 7的熱沉薄板1 7 5，接設在以圖2 製程製造的印刷電路板8 〇下表面。圖5、6分別顯示使 用包括散熱突體1 7 8與熱沉薄板1 7 5之印刷電路板所製 成的封裝。 圖5顯示的熱沉薄板175中，其上表面之晶片安裝 區上並未形成散熱突體178。圖6顯示的熱沉薄板175 ，中’其整個上表面，包括晶片安裝區，都設有散熱突體 178 〇 在本發明之較佳實施例中，雖然是將散熱突體1 7 8 設於熱沉薄板1 7 5之表面上，但是亦可將其設於合金薄 板1 0之表面上。 如上所述，設於熱沉薄板I75或合金薄板表面上 的散熱突體1了8,係用於改進熱傳導。若熱沉薄板ι75 或合金薄板10表面上未設任何散熱突體D 8，可在熱沉 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^--------- si (請先閲讀背面之注意事項再填寫本頁) 551〇〇3 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（14) 薄板1 7 5與合金薄板1 0之間夾設一黏著劑，藉此降低熱 傳導。 亦即’熱沉薄板1 7 5之散熱突體1 7 8係直接與晶片 1〇〇或合金薄板1〇連接，以改進熱傳導並有效接地。 根據本發明之較佳實施例，熱沉薄板1 7 5之散熱突 體17 8間的空間，係充填預浸物丄7 7或導電黏劑。熱沉 薄板I75係用預浸物m或導電黏劑接設在合金薄板1〇 之下表面。 以下詳細說明本發明前述印刷電路板8 〇之操作。 用於安裝半導體晶片100的空腔82，係設在印刷電 路板80的中央。半導體晶片1〇〇係經由空腔82安裝在 熱沉薄板7 5上。此處係於印刷電路板8 〇上形成空腔8 2 後’將熱沉薄板7 5接設在印刷電路板8 0的下表面。在 印刷電路板8 0上形成空腔8 2之步驟極為簡單。 亦即’由於只要在印刷電路板8 〇上打孔，即可形成 空腔82，所以形成空腔82之步驟極為容易。 根據本發明之較佳實施例，熱沉薄板75係利用夾設 於印刷電路板80與熱沉薄板75間之預浸物77，而接二 在印刷電路板8 0之下表面。因此，與習式使用黏劑的情 況比較時，熱沉薄板75與印刷電路板8◦間的黏著強^ 更為優異。此外，熱沉薄板75與印刷電路板8〇間並二 產生空洞，所以可改進封裝的可靠性。 半導體晶片100係安裝在空腔82内，所以可使封裝 高度最小化。 17 ^張^度適用中國國家標準（CNS)A4規袼（21G X --------------- (請先閱讀背面之注意事項再填寫本頁) --------訂---- 551003
經濟部智慧財產局員工消費合作社印製 五、發明說明（15) 在印刷電路板80之製造過程中，合金薄板1〇及其 上表面上形成的各層，都經由輔助孔36而互相導電與導 熱。因此，合金薄板10既可作為接地，亦可作為熱沉。 因此’利用本發明之合金薄板10，可增加接地能力 並因而減少合金薄板10上所需形成的接地層數，亦可減 少印刷電路板8 0之整體高度。 半導體晶片100之生熱，及經由合金薄板10傳輸之 熱量，可經由熱沉薄板75更有效地散逸至外側。 根據圖4至圖6顯示的本發明較佳實施例，散熱突 體1 7 8係設在熱沉薄板1 7 5的表面上。熱沉薄板丄7 5的 散熱突體17 8係直接接觸合金薄板1〇之下表面。因此， 具有散熱突體D8之熱沉薄板175，既可作為接地，亦 可作為熱沉，將經由合金薄板1〇傳輸之熱量散逸至外側， 並藉此最小化印刷電路板8 0之整體高度。 根據本發明之較佳實施例，可作為接地之合金薄板工〇 係經由輔助孔3β而與設在合金薄板1〇上的電路圖案52 導電與導熱。因此不需習式連接焊球與接地面的通孔，使 印刷電路板80之空間獲得更有效的利用。 此外’印刷電路板之層數減至最少，因而簡化製程並 降低生產成本。 以上雖然揭示本發明之較佳實施例作為舉例說明之 用’但熟悉此類技術之人士可以理解，其中可作多種化改 與增減而不離本發明依所附申請專利範圍揭示之範圍與精 神。 、 18 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝·------丨訂--------- (請先閱讀背面之注意事項再填寫本頁)

Claims (1)

  1. 551003 A8 B8 C8 D8 申請專利範圍 工· 一種具散熱元件之印刷電路板，該印刷電路板包括： 一熱沉薄板； ：----------%-I (請先閱讀背面之注意事項再填寫本頁) 一合金薄板，係接設在該熱沉薄板之一表面，並 具有指定之硬度； 一電路圖案層，係設於合金薄板之一表面上，並 具有與合金薄板導通之電路圖案及輔助孔；以及 一空腔’係設於電路圖案層與合金薄板内，以露 出熱沉薄板的一部份。 2. 如申請專利範圍第i項之具散熱元件之印刷電路板， 其中該合金薄板之下表面設有複數個散熱突體，其中， 該合金薄板係以該等散熱突體直接與熱沉薄板連接。 3. 如申請專利範圍第丄項之具散熱元件之印刷電路板， 其中該熱沉薄板可逸散從電路圖案傳送至合金薄板的 熱量。 f •如申明專利範圍第丄項之具散熱元件之印刷電路板， 其中該熱沉薄板之外露部份係在熱沉薄板之一表面 經濟部智慧財產局員工消費合作社印製 上，且該熱沉薄板之外露部份上，有一半導體晶片安 裝於該空腔内。 如申明專利範圍帛！項之具散熱元件之印刷電路板， 其中該合金薄板之高度至少為該半導體元件高度之一 半。 6·如申料利範圍第i項之具散熱元件之印刷電路板， 其中該合金薄板係作為該印刷電路板之導電接地，並
    551003 A8 B8 C8 D8 六、申請專利範圍 可散逸熱量。 7 · —種具散熱元件之印刷電路板製造方法，此方法包括： -- (請先閱讀背面之注意事項再填寫本頁) 在二片合金薄板間夾設一絕緣載體層，以使該二 片合金薄板彼此接合，其中，每一合金薄板均可用於 散熱； 在每一合金薄板之一表面上，接設一絕緣層與一 導電層； 在該絕緣層與導電層上打孔，以形成多數辅助孔； 形成一電鍍層，以經由該等輔助孔連接每層導電 層與該合金薄板； 在每一導電層上形成一電路圖案層； 分割該絕緣載體層，使二片具有電路圖案層之合 金薄板彼此分開；以及 將一熱沉薄板接設在至少該合金薄板之一之另一 表面。 *1. .如申請專利範圍帛7項之具散熱元件之印刷電路板製 經濟部智慧財產局員工消費合作社印製 造方法，其中使用絕緣載體層使二片合金薄板彼此連 接之步驟’包括： 提供一種黏著構件； 在該黏著構件之一或多侧上放置一離形構件；以 及 一人在該離形構件上放置至少一合金構件；使該至少 一合金構件定位時，有一部份延伸至離形構件之 以與該黏著構件接觸。
    551003 々、申請專利範圍 造方法用專利1&圍第7項之具散熱元件之印刷電路板製 之離报进其中該絕緣载體層包括設於—黏著構件兩侧 、二件，其中該黏著構件延伸至離形構件之外， 以與二片合金薄板之每一片接觸。 10·、Λ中請專利範圍第7項之具散熱㈣之印刷電路板 、法其中重複在導電層上形成電路圖案層之步 驟達一指定次數，其中，該指定次數等於所要的電路 圖案層數目。 』申明專利範圍第7項之具散熱元件之印刷電路板 製造方法，進而包括以下步驟：於該至少一合金薄板 之另表面上接設該熱沉薄板前，在電路圖案層與合 金薄板上打孔，以形成一空腔。 請專利範圍第7項之具散熱元件之印刷電路板 製返方法，進而包括以下步驟：於接設該熱沉薄板前， 在熱沉薄板之連接表面或合金薄板之另一表面上，形 成複數個散熱突體。 13· 一種半導體封裝，其包括： 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 一金屬製熱沉薄板； 該 一合金薄板，接設在該熱沉薄板之一表面上 合金薄板之操作如一基準電壓電平，並用以散熱； 其 一電路圖案層，設於該合金薄板之一表面上 上具有與合金薄板導通之電路圖案、複數個連接墊、 及辅助孔； 一空腔，設於該電路圖案層與該合金薄板内，以 21 本紙張尺度適用中國國家標準（CNS ) Μ規格（21()χ297公羡） 551003 A8 B8 C8 D8 六、申請專利範圍 露出熱沉薄板之一表面； 一半導體元件，安裝在該熱沉薄板之外露表面上， 位於該空腔内；以及 一導電元件，用以接合及導通該半導體元件與該 電路圖案層之連接墊。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 22 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）
TW091115755A 2001-07-18 2002-07-16 Printed circuit board with a heat dissipation element, method for manufacturing the printed circuit board, and package comprising the printed circuit board TW551003B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI413222B (zh) * 2010-07-20 2013-10-21 Lsi Corp 堆疊互連散熱器
TWI760868B (zh) * 2019-10-15 2022-04-11 日商三菱電機股份有限公司 半導體裝置

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040004277A1 (en) * 2002-07-03 2004-01-08 Chung-Che Tsai Semiconductor package with reinforced substrate and fabrication method of the substrate
JP2004273968A (ja) * 2003-03-12 2004-09-30 Fujitsu Ltd 記録ディスク駆動装置およびフレキシブルプリント基板ユニット
TWI239603B (en) * 2003-09-12 2005-09-11 Advanced Semiconductor Eng Cavity down type semiconductor package
US7135357B2 (en) * 2003-10-06 2006-11-14 E. I. Du Pont De Nemours And Company Process for making an organic electronic device having a roughened surface heat sink
US8395253B2 (en) * 2004-01-28 2013-03-12 International Rectifier Corporation Hermetic surface mounted power package
KR100585227B1 (ko) 2004-03-12 2006-06-01 삼성전자주식회사 열 방출 특성이 개선된 반도체 적층 패키지 및 이를이용한 메모리 모듈
JP4575147B2 (ja) * 2004-12-28 2010-11-04 株式会社東芝 半導体装置
US7344915B2 (en) * 2005-03-14 2008-03-18 Advanced Semiconductor Engineering, Inc. Method for manufacturing a semiconductor package with a laminated chip cavity
KR100744993B1 (ko) * 2006-01-25 2007-08-02 삼성전기주식회사 다층 인쇄회로기판 및 그 제작방법
US7952834B2 (en) * 2008-02-22 2011-05-31 Seagate Technology Llc Flex circuit assembly with thermal energy dissipation
DE102008001414A1 (de) * 2008-04-28 2009-10-29 Robert Bosch Gmbh Substrat-Schaltungsmodul mit Bauteilen in mehreren Kontaktierungsebenen
JP5352437B2 (ja) * 2009-11-30 2013-11-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8669777B2 (en) 2010-10-27 2014-03-11 Seagate Technology Llc Assessing connection joint coverage between a device and a printed circuit board
TWI505765B (zh) * 2010-12-14 2015-10-21 Unimicron Technology Corp 線路板及其製造方法
TW201230897A (en) * 2011-01-14 2012-07-16 Askey Computer Corp Circuit board
TWI408837B (zh) * 2011-02-08 2013-09-11 Subtron Technology Co Ltd 封裝載板及其製作方法
US20120286416A1 (en) * 2011-05-11 2012-11-15 Tessera Research Llc Semiconductor chip package assembly and method for making same
US9230899B2 (en) * 2011-09-30 2016-01-05 Unimicron Technology Corporation Packaging substrate having a holder, method of fabricating the packaging substrate, package structure having a holder, and method of fabricating the package structure
JP6021504B2 (ja) 2012-08-08 2016-11-09 キヤノン株式会社 プリント配線板、プリント回路板及びプリント回路板の製造方法
CN103021877B (zh) * 2012-12-22 2016-03-09 中国船舶重工集团公司第七0九研究所 一种采用双路径传热的高密度芯片散热方法
US9111878B2 (en) * 2013-01-31 2015-08-18 Freescale Semiconductor, Inc Method for forming a semiconductor device assembly having a heat spreader
US10433413B2 (en) * 2014-08-15 2019-10-01 Unimicron Technology Corp. Manufacturing method of circuit structure embedded with heat-dissipation block
DE102014117943B4 (de) 2014-12-05 2022-12-08 Infineon Technologies Austria Ag Vorrichtung mit einer Leiterplatte und einem Metallwerkstück
DE102015104956A1 (de) * 2015-03-31 2016-10-06 Infineon Technologies Ag Gedruckte Leiterplatte mit einem Leiterrahmen mit eingefügten gehäusten Halbleiterchips
CN109076703A (zh) 2016-04-15 2018-12-21 3M创新有限公司 通过粘合剂转移制备电子电路
US10718963B1 (en) 2016-11-16 2020-07-21 Electro-Optics Technology, Inc. High power faraday isolators and rotators using potassium terbium fluoride crystals
KR102040493B1 (ko) 2017-05-31 2019-11-05 (주)제이엠씨 인쇄회로기판용 방열장치 및 이의 제조방법
CN114980573A (zh) * 2021-02-25 2022-08-30 深南电路股份有限公司 电路板的制作方法、电路板及电子装置
CN113284863A (zh) * 2021-07-09 2021-08-20 惠州市金百泽电路科技有限公司 一种用于芯片的嵌入式封装结构及其制作方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6097089A (en) 1998-01-28 2000-08-01 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package
US4280409A (en) * 1979-04-09 1981-07-28 The United States Of America As Represented By The Secretary Of The Navy Molten metal-liquid explosive device
JP2796636B2 (ja) * 1989-10-30 1998-09-10 イビデン株式会社 電子部品搭載用基板
US5158912A (en) * 1991-04-09 1992-10-27 Digital Equipment Corporation Integral heatsink semiconductor package
US5388027A (en) * 1993-07-29 1995-02-07 Motorola, Inc. Electronic circuit assembly with improved heatsinking
JPH07302866A (ja) * 1994-04-28 1995-11-14 Nippon Steel Corp 半導体装置および該装置用ヒートスプレッダー
FR2735648B1 (fr) * 1995-06-13 1997-07-11 Bull Sa Procede de refroidissement d'un circuit integre monte dans un boitier
US5633533A (en) * 1995-07-26 1997-05-27 International Business Machines Corporation Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
US5844168A (en) * 1995-08-01 1998-12-01 Minnesota Mining And Manufacturing Company Multi-layer interconnect sutructure for ball grid arrays
JP3382482B2 (ja) 1996-12-17 2003-03-04 新光電気工業株式会社 半導体パッケージ用回路基板の製造方法
US6020637A (en) * 1997-05-07 2000-02-01 Signetics Kp Co., Ltd. Ball grid array semiconductor package
US6395582B1 (en) * 1997-07-14 2002-05-28 Signetics Methods for forming ground vias in semiconductor packages
KR19990070625A (ko) * 1998-02-23 1999-09-15 구본준 반도체 패키지 및 그 제조방법
JPH11274355A (ja) * 1998-03-19 1999-10-08 Sumitomo Metal Electronics Devices Inc 放熱板付きプラスチックパッケージ
KR100302652B1 (ko) * 1998-09-11 2001-11-30 구자홍 플렉시블인쇄회로기판의제조방법및그방법으로생산한플렉시블인쇄회로기판
KR100319624B1 (ko) * 1999-05-20 2002-01-09 김영환 반도체 칩 패키지 및 그 제조방법
US6184580B1 (en) * 1999-09-10 2001-02-06 Siliconware Precision Industries Co., Ltd. Ball grid array package with conductive leads
JP2001168226A (ja) * 1999-12-14 2001-06-22 Shinko Electric Ind Co Ltd 半導体パッケージ及び半導体装置
KR20010057046A (ko) * 1999-12-17 2001-07-04 이형도 캐비티를 갖는 패키지 기판

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI413222B (zh) * 2010-07-20 2013-10-21 Lsi Corp 堆疊互連散熱器
TWI760868B (zh) * 2019-10-15 2022-04-11 日商三菱電機股份有限公司 半導體裝置

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