CN1832664A - 具有嵌入式多层无源器件的印刷电路板的制造方法 - Google Patents
具有嵌入式多层无源器件的印刷电路板的制造方法 Download PDFInfo
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Abstract
本发明涉及制造具有嵌入式多层无源器件的印刷电路板的方法,具体而言,涉及制造具有嵌入式多层电容器的印刷电路板的方法,其中在PCB中形成具有多层的电容器以增加电容。
Description
技术领域
一般而言,本发明涉及制造具有嵌入式多层无源器件的印刷电路板(PCB)的方法,更具体而言,涉及制造具有嵌入式多层电容器的PCB的方法,其中在PCB中形成具有多层的电容器以增加电容。
背景技术
尽管分立的片式电阻器或分立的片式电容器已经广泛安装在迄今为止几乎所有的PCB上,但是最近开发了嵌入无源器件如电阻器或电容器的PCB。
在制造包含嵌入式无源器件的PCB的技术中,采用新的材料和方法,将无源器件如电阻器或电容器插入到基板的外层或内层,以取代传统的片式电阻器和片式电容器。
也就是说,包含嵌入式无源器件的PCB是指无源器件例如电容器插入在基板的内层或外层。无论基板本身的尺寸如何,如果将用作无源器件的电容器引入到PCB中,就称作“嵌入式电容器”。这种基板称作“嵌入式电容器PCB”。
嵌入式无源器件PCB的最重要特征是无源器件整体提供在PCB中,而不需要将其安装在基板上。
一般地,嵌入式无源器件PCB的制造技术大体分为三种。
第一种是制造聚合物厚膜型电容器的方法,包括涂覆聚合物电容器糊(polymercapacitor paste),随后加热固化,即干燥,从而制成电容器。
具体地,该方法包括在PCB内层涂覆聚合物电容器糊,并干燥所涂覆的聚合物电容器糊,随后在其上印刷铜糊(copper paste)并干燥以形成电极,由此得到嵌入的电容器。
第二种是制造嵌入式分立型电容器的方法,包括用陶瓷填充的感光性介电树脂(photodielectric resin)涂覆PCB,这已由美国摩托罗拉有限公司取得专利权。
以上方法包括将含有陶瓷粉末的感光性介电树脂层涂覆在基板的上表面和下表面,将铜箔层压于树脂层上以形成上电极和下电极,形成电路图案,然后蚀刻感光性介电树脂,由此获得分立电容器。
第三种是制造嵌入式电容器的方法,包括将具有电容特性的介电层单独插入到PCB的内层,以取代安装在PCB上的去耦电容器,这已由美国Sanmina有限公司取得专利权。
在这点上,授权给美国Sanmina有限公司的美国专利No.5,079,069公开了包含两导电层和插入到该两层之间的绝缘材料层(介电层)的嵌入式电容器PCB和包含该嵌入式电容器PCB的PCB。
嵌入式电容器PCB的介电层具有至少0.5密耳(12.5μm)、通常为1-2密耳(25-50μm)的厚度。导电层的重量分布为至少0.5盎司/平方英尺(厚度:约18μm),通常为1盎司/平方英尺。
另外,授权给美国Sanmina有限公司的美国专利No.5,155,655和5,161,086公开了通过表面处理导电箔而得到的导电层用于确保粘合和电容密度的用途。
另外,授权给美国Sanmina有限公司的美国专利No.5,162,977公开了使用高电容粉末的电容芯元件。在以上专利中,介电层中包含具有500或更大(至少为环氧树脂的10倍)的高介电常数的预烧陶瓷粉末,以增加去耦能力。
但是,由于电容非常低,因此使得这种传统技术的实际可用性降低。为了解决这些问题,尽管已经尝试使用具有高电容的组分材料,但是它们仍然达不到希望的产品要求。
发明内容
因此,考虑到现有技术中出现的以上问题,提出本发明,本发明的目的是提供具有嵌入式多层无源器件的PCB,其中嵌入式电容器制成为包含多个导电层和多个介电层以提高电容。
为了实现上述目的,本发明提供制造具有嵌入式多层无源器件的PCB的方法,包括以下步骤:第一步,将绝缘层叠置在构成芯层的基板上,随后将具有下电极层的RCC层压在绝缘层上;第二步,除去RCC的上层铜箔,随后形成内电极层;第三步,将第一步和第二步中的RCC层压过程重复几次,以形成多个介电层和多个内电极层;第四步,形成穿过具有多个介电层和多个内电极层的PCB的多个导通孔,随后镀覆导通孔内壁以导电连接内电极层,从而完成多层无源器件。
附图说明
图1A-1J是根据本发明第一实施方案依次示出制造包含嵌入式多层电容器的PCB的方法的截面图;和
图2A-2J是根据本发明第二实施方案依次示出制造包含嵌入式多层电容器的PCB的方法的截面图。
具体实施方式
下文中,参照附图说明本发明的优选实施方案。
根据本发明第一实施方案,图1A-1J依次描述制造包含嵌入式多层电容器的PCB的方法。
如图1A所示,对构成芯层的基板100的铜箔102进行成像过程,以形成电路图案。
用作基板100的覆铜箔层压板(CCL)根据其应用分为玻璃/环氧树脂CCL、耐热树脂CCL、纸/酚CCL、高频CCL、挠性CCL、复合CCL等。在这些CCL中,优选使用包含用铜箔102、103包覆的绝缘树脂层101的玻璃/环氧树脂CCL 100,以制造双面PCB或多层PCB。
在基板100上叠置干膜(未示出)之后,利用具有预定印刷图案的布线图膜使干膜曝光并显影,由此使干膜形成为预定图案。喷涂蚀刻剂,由此除去对应于受干膜保护区域之外的区域的铜箔102。除去所使用的干膜,形成铜箔102的最终布线图。
干膜由三层组成,即覆盖膜、光刻胶膜和迈拉膜,其中光刻胶膜实际上用作抗蚀层。
通过使具有预定图案的布线图膜与干膜上表面紧密结合并随后将UV光辐照在布线图膜上,来进行干膜的曝光和显影。
如此,UV光未透过对应于布线图膜的印刷图案的黑色部分,但是它透过布线图膜没有图案的部分,从而固化布线图膜下方的干膜。
当将具有固化干膜的CCL 102浸入到显影剂中时,利用显影剂除去干膜的非固化部分,只保留固化的干膜以形成抗蚀图案。显影剂包括例如碳酸钠(Na2CO3)或碳酸钾(K2CO3)水溶液。
利用成像过程在基板100上形成抗蚀图案后,喷涂蚀刻剂以除去对应于除受抗蚀图案保护区域之外的区域的铜箔102,并除去所使用的抗蚀图案,形成铜箔102的最终布线图。
如图1B所示,半固化片104、105层压在具有电路图案的基板100的两个表面上。每一个仅在其任意一个表面上具有电路图案的CCL 110、120分别层压在半固化片104、105上。
在每个CCL 110、120的任意一个表面上形成电路图案的方法与上述在基板100上形成电路图案的方法相同,前提是CCL 110、120的绝缘层111、121优选由具有高介电常数的材料形成,以制成具有高电容的电容器。
如图1C所示,从CCL 110、120上除去最外层铜箔112、122。从CCL 110、120上除去最外层铜箔112、122的原因是常用CCL的铜箔很厚。如果CCL的铜箔用作多层电容器的电极层,那么所得PCB随着其后的介电层的层压而变得很厚。另外,由于用以形成图案并随后除去的导电部分应填充树脂,因此难以满足产品要求。
如图1D所示,提供种层(seed layer)131、132以形成嵌入在PCB内的多层电容器的内电极层。
种层131、132可以利用无电镀过程形成。不是通过带电离子反应,而是通过沉积反应,尤其是利用催化剂加速的沉积反应,来对绝缘材料进行无电镀过程。
进行无电镀时,催化剂应与待镀材料的表面结合,从而使铜从镀液中沉积出来。这意味着无电镀需要许多预处理程序。
例如,无电镀过程包括清洗、软蚀刻、预催化、催化、加速、无电镀铜和预防氧化等步骤。
无电镀铜过程得到的物理性能不如电镀铜过程,因此可以用于形成薄的铜镀层。
如图1E所示,利用电镀过程形成用于形成嵌入在PCB内的多层电容器的内电极层的内导电层133、134。
如图1F所示,内导电层133、134利用成像过程形成图案,以形成内电极层。
如图1F和1G所示,根据需要,重复图1B-1F所示的使电镀层形成图案的程序,以形成所希望的多层电容器。
也就是说,根据需要重复以下程序:i)层压半固化片以形成介电层,ii)层压具有下图案的CCL,iii)除去上层铜箔,和iv)利用无电镀和电镀形成多层电容器的内电极层。
在内导电层133、134利用成像过程形成图案而形成内电极层之后,层压RCC以形成介电层161、171,如图1H所示,随后使RCC的铜箔162、172形成图案,以形成上电极层,如图1G所示。
如图1I所示,在多层PCB中形成导通孔(未示出)或通孔,之后镀覆导通孔或通孔的内壁以形成镀层180,以导电连接多层结构的内电极层,从而制成所希望的多层电容器。
导通孔或通孔优选以如下方式形成:利用激光或CNC(计算机数字控制)钻孔机在预定位置形成导通孔或通孔。
CNC钻孔机适用于在双面PCB中形成导通孔或在多层PCB中形成通孔。
利用CNC钻孔机加工导通孔或通孔后,优选进行去毛刺过程以除去钻孔时所形成的铜箔毛刺、导通孔中灰尘和铜箔上的灰尘。在该步骤中,铜箔表面变得粗糙,由此增加在随后的镀铜工艺中与铜的附着。
激光适用于在多层PCB中形成微导通孔。利用激光、尤其是YAG(钇铝石榴石)激光同时加工铜箔和绝缘树脂层。另外,可以蚀刻对应于导通孔部分的铜箔,随后可以利用二氧化碳激光加工绝缘树脂层。
形成导通孔之后,优选进行去污过程以除去污渍,所述污渍是由于形成导通孔时生热致使基板的绝缘树脂层熔融而形成在导通孔侧壁上。
如图1J所示,将IC芯片190、191安装在具有多层电容器的PCB上,以完成半导体芯片封装。
现在来看图2A-2J,根据本发明第二实施方案,依次说明了制造包含嵌入式多层电容器的PCB的方法。
如图2A所示,对构成芯层的基板200的铜箔202、203进行成像过程,以形成电路图案。基板200与第一实施方案中所用的基板100相同,根据其应用,实例有玻璃/环氧树脂CCL、耐热树脂CCL、纸/酚CCL、高频CCL、挠性CCL、复合CCL等。在这些CCL中,优选使用玻璃/环氧树脂CCL。
如图2B所示,半固化片204、205层压在具有电路图案的基板200的两个表面上。此后,均为嵌入在PCB中的多层电容器的下电极的薄箔206、207分别层压在半固化片204、205上。随后,提供电路图案,如图2C所示。
在箔206、207上形成电路图案的方法与上述在基板200上形成电路图案的方法相同。
如图2D所示,层压包含具有高介电常数的介电层211、221的超薄箔载体210、220,在介电层211、221上层压非常薄的箔212、222和在箔212、222上层压载体213、223。
载体213、223用于承载由介电层211、221和箔212、222形成的RCC,然后在RCC与形成下电极的箔206、207结合之后除去,如图2E所示。
如图2F所示,箔212、222利用成像过程形成图案,并因此可以作为内电极层。利用载体(未示出),还可以层压多个RCC(在本实施方案中,上RCC 230和下RCC240分别层压在上表面和下表面),以满足产品要求,即形成多层介电层和内电极层。
图2G示出由此形成的多层电容器。加工导通孔251、252以电连接内电极层。
导通孔优选以如下方式形成:如上所述利用CNC钻孔机或激光在预定位置形成导通孔。
CNC钻孔机适用于在双面PCB中形成导通孔或在多层PCB中形成通孔。
激光适用于在多层PCB中形成微导通孔。利用激光、尤其是YAG(钇铝石榴石)激光可以同时加工铜箔和绝缘树脂层。作为替代方案,可以蚀刻对应于导通孔部分的铜箔,随后可以利用二氧化碳激光来加工绝缘树脂层。
如图2H和2I所示,层压RCC 260、270,然后最外层箔262、272利用成像过程形成图案,以形成外电极层。
另外,形成多个导通孔281、282,使得内电极层可以导电连接至外电极层,并且内电极层可以相互电连接,由此形成多层电容器。
如图2J所示,安装IC芯片,以完成半导体芯片封装。
在本发明的具有嵌入式多层电容器的PCB中,电容器导电层的数目可以是三个或更多,其绝缘层的数目可以是两个或更多。
此外,可以通过集体层压法(collective lamination process)或堆积法(building-upprocess)使具有电容的RCC或CCL型层形成为多层的。
随着多层电容器绝缘层厚度的减小和绝缘层数目的增加,电容增加。另外,多层电容器的内导电层应尽可能薄地形成,以减小所得PCB的厚度,并实现绝缘层的厚度均匀。
为了减小内导电层的厚度,可以利用原本就薄的箔(0.5盎司/平方英尺≈18μm或更小、3-9μm的箔)形成导电层。另外,可以通过层压RCC或CCL、除去最外层的厚导电箔、通过无电镀形成种层以及随后通过电镀形成所希望的导电层来形成导电层(5μm或更薄)。另外,可以通过层压经表面处理的RCC或CCL并随后部分除去最外层的厚导电箔来形成导电层。
如上所述,本发明提供制造包含嵌入式多层无源器件的PCB的方法,其可以利用相同材料(具有诸如介电常数、厚度等性质)在相同板面积上表现出更高的性能(去耦或匹配)。
根据本发明的方法,在形成图案用于设计反相电流的情况下,可以制造由于电感的补偿效应而具有良好高频性能的嵌入式电容器PCB。
根据本发明的方法,可以充分表现出多层结构的优点,以获得将去耦极大改变至理想水平的电容密度。
根据本发明的方法,当为了信号匹配而使用介电填料来确保预定水平或更高的介电常数时,由于会出现诸如不良温度性能等问题,因此将具有优异性能只是介电常数低的聚合物材料设计为多层形式,由此电容可以增加至所需水平或更高,而不会使其它性能变差。
尽管为了说明目的公开了本发明的优选实施方案,但是本领域的技术人员应理解,可以在不背离如所附权利要求书所公开的本发明的范围和精神的情况下进行各种改变、添加或替代。
Claims (6)
1.制造包含嵌入式多层无源器件的印刷电路板的方法,包括以下步骤:
第一步,将绝缘层叠置在构成芯层的基板上,随后将具有下电极层的RCC层压在绝缘层上;
第二步,除去RCC的上层铜箔,随后形成内电极层;
第三步,将第一步和第二步中的RCC层压过程重复几次,以形成多个介电层和多个内电极层;和
第四步,形成穿过具有多个介电层和多个内电极层的印刷电路板的多个导通孔,随后镀覆导通孔内壁以导电连接内电极层,从而制成多层无源器件。
2.权利要求1的方法,其中第二步包括:
除去层压在绝缘层上的RCC的上层铜箔;
通过无电镀,在没有上层铜箔的RCC绝缘层上形成种层;和
通过电镀,在种层上形成内电极层。
3.权利要求2的方法,其中通过电镀在种层上形成的内电极层具有0.1-5μm的厚度。
4.制造包含嵌入式多层无源器件的印刷电路板的方法,包括以下步骤:
第一步,将绝缘层叠置在构成芯层的基板上,随后形成下电极层;
第二步,利用超薄箔载体在下电极层上形成绝缘层和内电极层;
第三步,加工导通孔,使其穿过具有绝缘层和内电极层的印刷电路板,以电连接内电极层;和
第四步,重复第二步和第三步,以形成多个绝缘层和多个内电极层,从而制成多层无源器件。
5.权利要求4的方法,其中第一步包括:
将半固化片层压在构成芯层的基板上,以形成绝缘层;和
将箔层压在绝缘层上,然后利用成像过程形成下电极层。
6.权利要求4的方法,其中第二步包括:
利用超薄箔载体将包含由薄膜包覆的绝缘层的RCC层压在下电极层上;
从超薄箔载体中除去载体,以暴露RCC薄膜;和
对薄膜进行成像过程,以形成内电极层。
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2005
- 2005-03-11 KR KR1020050020572A patent/KR100688743B1/ko active IP Right Grant
- 2005-12-22 TW TW094145790A patent/TWI305480B/zh not_active IP Right Cessation
- 2005-12-31 CN CNB2005101378263A patent/CN100548089C/zh not_active Expired - Fee Related
-
2006
- 2006-01-03 US US11/325,557 patent/US7293356B2/en not_active Expired - Fee Related
- 2006-01-26 JP JP2006017832A patent/JP4288266B2/ja not_active Expired - Fee Related
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CN101534613B (zh) * | 2008-03-14 | 2012-06-13 | 富葵精密组件(深圳)有限公司 | 一种具有断差结构的电路板的制作方法 |
CN108550531A (zh) * | 2018-05-15 | 2018-09-18 | 日月光半导体(上海)有限公司 | 封装基板的制造方法 |
CN108682630A (zh) * | 2018-05-15 | 2018-10-19 | 日月光半导体(上海)有限公司 | 封装基板的制造方法 |
CN108682630B (zh) * | 2018-05-15 | 2020-04-24 | 日月光半导体(上海)有限公司 | 封装基板的制造方法 |
CN108550531B (zh) * | 2018-05-15 | 2020-05-08 | 日月光半导体(上海)有限公司 | 封装基板的制造方法 |
CN111986925A (zh) * | 2019-05-22 | 2020-11-24 | 江西兴海容电路板有限公司 | 电容器及其制造方法 |
CN111986925B (zh) * | 2019-05-22 | 2022-05-17 | 江西兴海容电路板有限公司 | 电容器及其制造方法 |
Also Published As
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CN100548089C (zh) | 2009-10-07 |
US7293356B2 (en) | 2007-11-13 |
TWI305480B (en) | 2009-01-11 |
JP4288266B2 (ja) | 2009-07-01 |
KR100688743B1 (ko) | 2007-03-02 |
KR20060099245A (ko) | 2006-09-19 |
US20060203456A1 (en) | 2006-09-14 |
TW200633614A (en) | 2006-09-16 |
JP2006253656A (ja) | 2006-09-21 |
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