CN1256006C - 线路板 - Google Patents
线路板 Download PDFInfo
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- CN1256006C CN1256006C CNB021053065A CN02105306A CN1256006C CN 1256006 C CN1256006 C CN 1256006C CN B021053065 A CNB021053065 A CN B021053065A CN 02105306 A CN02105306 A CN 02105306A CN 1256006 C CN1256006 C CN 1256006C
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Abstract
本发明提供一种线路板,仅在芯板的前表面(单面)上层叠构筑层,缩短安装在前表面侧的半导体元件和安装或内置在背表面侧的电子部件的距离,提高两者间的导通路径的电气特性,同时,提高整体的强度,难于产生挠曲和翘曲。本发明的线路板(1)包含:具有前表面(3)和背表面(4)的比较薄的第一芯板(2),层叠在第一芯板(2)的背表面(4)侧并且具有通孔(9)的比较厚的第二芯板(6),该通孔与第一芯板(2)一起形成凹部(9),形成在第一芯板(2)的前表面(3)的上方并且包含布线层(16、25)和绝缘层(23、26)的构筑层BU。其中,第一和第二芯板(2,6)由玻璃环氧树脂制成,并且第二芯板(6)比第一芯板(2)厚。
Description
技术领域
本发明涉及在芯板的单面上层叠构筑层的线路板。
背景技术
图7表示在芯板41的前表面和背表面42、43的上/下层叠构筑层BU1、BU2的线路板40中的主要部分的断面。芯板41由0.2~0.4mm厚度的玻璃环氧树脂构成,在贯通其前表面42和背表面43之间的多个通孔44中分别形成通孔导体45和填充树脂46。
如图7所示的那样,在芯板41的前表面42上形成预定图形的布线层48,并且,分别与各个通孔导体45的上端相连接。在相应的前表面42和布线层48上形成环氧树脂类的绝缘层50,并且,在布线层48上的预定位置上形成场通路导体52。
如图7所示的那样,在绝缘层50上形成与上述相同的绝缘层56和与上述通路导体52的上端相连接的布线层54。在相应的布线层54上的预定位置上形成场通路导体58,同时,在绝缘层56上形成焊料保护层(绝缘层)60和与通路导体58的上端相连接的布线层62。以上的布线层48、54、62和绝缘层50、56、60形成构筑层BU1。
如图7所示的那样,在布线层62上的预定位置上分别形成比作为焊料保护层60的表面的第一主面64高的突出的多个焊料凸起66。各个焊料凸起66分别与安装在第一主面64上的IC芯片(半导体元件)68的底面上的连接端子70相连接。
而且,在IC芯片68的周围,从平面上看大致为矩形框形以便于围绕该芯片的铜制的加强件(加强板)72通过未图示的粘接剂粘接到第一主面64上。
如图7所示的那样,在芯板41的背表面43下形成与通孔导体45的下端相连接的布线层47。在相应的布线层47的下方形成由与上述相同的绝缘层49、55,焊料保护层(绝缘层)63,布线层53、59和场通路导体51,57组成的构筑层BU2。在布线层59的预定位置上分别形成突出到第二主面65的下方的多个焊料凸起67,各个焊料凸起67分别与安装在第二主面65的下侧的片状电容器(电子部件)69的连接端子71相连接。
发明所要解决的问题
但是,在以上这样的芯板41的两面上具有构筑层BU1,BU2的线路板40上,IC芯片68通过布线层62、54、48,通孔导体45和布线层47、53、59等与片状电容器69导通。因此,存在这样的问题,导通路径变长,环路电感增加等,电气特性变得不稳定。
因此,应当缩短IC芯片68与片状电容器69的距离,使芯板41成为0.4mm以下的厚度,同时,仅在其表面42侧形成构筑层BU1。但是,在这样的情况下,线路板40整体的强度降低,产生挠曲和翘曲。为了防止相应的挠曲和翘曲,必须在第一主面64上配置金属制的加强件72。由此,引起成本高的问题。
为了解决上述现有技术的问题,本发明的课题是提供一种线路板,仅在芯板的单面(前表面)层叠包含多个布线层和多个绝缘层的构筑层,缩短安装在线路板的前表面侧的半导体元件(IC芯片)与安装在背表面侧或者内置的电子部件(片状电容器等)的距离,提高两者间的导通路径的电气特性。而且,提供提高了线路板整体的强度并且难于产生挠曲和翘曲的线路板。
发明内容
为了解决上述课题,本发明着眼于并用两个芯板来构成。
即,本发明的线路板,其特征在于,包含:具有前表面和背表面的第一芯板;层叠在该第一芯板的背表面侧并且具有通孔的第二芯板,该通孔与第一芯板一起形成凹部;以及形成在上述第一芯板的前表面上方并且包含多个布线层和多个绝缘层的构筑层。其中,所述第一和第二芯板由玻璃环氧树脂制成,并且所述第二芯板比第一芯板厚。
由此,通过层叠第一和第二芯板来使用,不需要现有技术这样的昂贵的加强件和粘接它的工序,因此,能够廉价地制造线路板。而且,由于电子部件可以安装或者内置在两个芯板所形成的凹部内,因此,能够缩短相应的电子部件与安装在构筑层的前表面上的IC芯片等半导体元件的导通路径。由此,能够降低环路电感,使内部的电气特性稳定。而且,与IC芯片相连接的IC连接端子除了贯通第一芯板的通孔导体之外还能利用来自贯通第一和第二芯板的通孔导体的布线路径。
而且,在本说明书中,所谓芯板是指绝缘性的板材本身,不包含在其前表面和背表面上所形成的布线层。
附带地说,上述线路板包含:具有前表面和背表面的第一芯板;层叠在该第一芯板的背表面侧并且具有通孔的第二芯板,该通孔与第一芯板一起形成凹部;形成在上述第一芯板的前表面上方并且包含多个布线层和多个绝缘层的构筑层,同时,在上述第二芯板上的与第一芯板的背表面相对的表面(即,第二芯板的背表面)上形成一个布线层或者一个布线层和绝缘层(焊料保护层)。
在此情况下,在上述效果的基础上,由于在上述第二芯板的背表面侧不形成构筑层,能够节省形成多个通路导体、布线层和绝缘层的成本。而且,把上述一个布线层上的布线作为连接端子,能够作为与搭载该线路板的主板等连接来使用。
而且,在本发明中包含了具有上述通孔的第二芯板的厚度厚于上述第一芯板的线路板。由此,能够确实地缩短安装或内置在凹部内的电子部件与安装在构筑层的前表面上的半导体元件的导通路径。由此,能够降低环路电感而使内部的电气特性进一步稳定。而且,由于厚度较厚的第二芯板加强了厚度较薄的第一芯板,则不需要昂贵的加强件和粘接它的工序,线路板的廉价的制造进一步变得确实。
而且,在本发明中包含了在上述第一芯板与具有上述通孔的第二芯板之间插入粘接层和布线层的线路板。
由此,能够在第一和第二芯板之间形成多个布线层,因此,能够容易地适应内部的布线密度的提高,同时,能够降低随着接地层的形成而从电源到电子部件(片状电容器等)的供电噪声,即,能够降低电感。而且,可以在第一和第二芯板之间仅插入粘接层。
而且,在本发明中包含了上述第一芯板的厚度在100μm以上,400μm以下,上述第二芯板的厚度在500μm以上,1000μm以下的线路板。
由此,由于第一和第二芯板的厚度是适当的,则不需要加强件,并且,成为能够廉价地制造的线路板。
而且,第一芯板的厚度不足100μm时,操作性降低,容易损伤,当超过400μm时,安装在构筑层的前表面上的IC芯片等半导体元件与安装在背表面侧的电子部件的距离变长,不能使电气特性稳定,因此,取上述范围。而且,当第二芯板的厚度不足500μm时,不能获得提高线路板整体强度的效果,当超过1000μm时,通孔的开孔加工的精度降低,因此取上述范围。
附带地说,本发明包含这样的线路板:在上述构筑层的前表面上配置多个IC连接端子,并且,在上述凹部内配置电子部件连接端子。在此情况下,与多个IC连接端子相连接的半导体元件和与电子部件连接端子相连接的电子部件通过第一芯板以比较短的距离进行连接,因此,能够谋求两者间路径的环路电感的降低以及电气特性的提高。
而且,本发明包含这样的线路板:在上述凹部中进一步配置具有能够与上述构筑层的布线层导通的电子部件连接端子的电子部件。在此情况下,使电子部件通过短的导通路径与安装在构筑层的前表面上的半导体元件(IC芯片)导通。
而且,本发明包含这样的线路板:电子部件通过埋入树脂而内置在上述凹部中。在此情况下,在凹部中坚固地内置了片状电容器等电子部件,并且,使线路板的强度提高,同时,使相应的电子部件通过短的导通路径与安装在构筑层的前表面上的半导体元件(IC芯片)导通。
而且,上述电子部件包含电容器、电感器、电阻器、滤波器等无源部件和低噪声放大器(LNA)、晶体管、半导体元件、FET等有源部件;SAW滤波器、LC滤波器、天线开关模块、耦合器、双工器等;把它们形成为片状的装置,但并不仅限于此。而且,在其中可以把不同种类的电子部件彼此内置在同一个凹部内。而且,在电子部件中包含仅在第二芯板上的前表面或背表面的一方具有电极的形态。
附图说明
图1表示本发明的一个形态的线路板的主要部分的剖视图;
图2表示图1所示线路板的变形形态的线路板的主要部分的剖视图;
图3(A)~(D)是表示用于得到图1和图2的线路板的主要制造工序的简图;
图4(A)~(C)是接着图3(D)表示主要制造工序的简图;
图5(A)~(C)是接着图4(C)表示主要制造工序的简图;
图6表示不同形态的线路板中的主要部分的剖视图;
图7表示现有的线路板的主要部分的剖视图。
具体实施方式
下面与附图一起来说明本发明的最佳实施例。
图1表示本发明的一个实施例的线路板1上的主要部分的断面。
线路板1,如图1所示的那样,包含:厚度较薄的例如200μm的第一芯板2、厚度较厚的例如800μm的第二芯板6、由在第一芯板2的前表面3上方所形成的布线层16、25和绝缘层23、26组成的构筑层BU。
第一芯板2由具有前表面3和背表面4的厚度在100μm以上,400μm以下的玻璃环氧树脂构成,在其中央部附近,开通直径约100μm的多个通孔10,同时,在各个通孔10的内侧形成铜制的厚度约25μm的通孔导体11和填充树脂12。
如图1所示的那样,第二芯板6由具有前表面7和背表面8的厚度在600μm以上,100μm以下的玻璃环氧树脂所构成,在其中央附近形成凹部9。相应的凹部9从平面上看呈纵和横各为约14mm的大致正方形。
第一芯板2和第二芯板6通过厚度约60μm的具有粘接性的绝缘层(半固化片:粘接层)5而在两者的厚度方向上层叠。
如图1中的左右所示的那样,在第一芯板2和第二芯板6以及绝缘层5,贯通直径约100μm的多个通孔13,在各个通孔13的内侧形成铜制的并且厚度约25μm的长的通孔导体14和填充树脂15。
而且,如图1所示的那样,在第一芯板2的背表面4上形成具有预定图形的铜制的厚度为约15μm的铜制布线层17,与各个通孔导体11的下端或者某个通孔导体14的中间相连接。在第二芯板6的前表面7上形成具有与上述相同的预定图形和厚度的铜制布线层18,并且,与某个通孔导体14的中间相连接。
而且,如图1所示的那样,在第一芯板2的前表面3上形成具有预定图形的铜制布线层16,与通孔导体11、14的上端的某个相连接。在前表面3和布线层16上形成环氧类树脂的绝缘层23,并且,在布线层16上的预定位置上形成场通路导体24。在上述绝缘层23上形成与绝缘层26和通路导体24的上端相连接的布线层25,并且,在布线层25上的预定位置上形成场通路导体28。同样,在绝缘层26上形成焊料保护层(绝缘层)32和与通路导体28的上端相连接的布线层30。
以上的布线层16、25、30和绝缘层23、26、32形成构筑层BU。而且,绝缘层23的厚度约为30μm,焊料保护层26的厚度约为25μm。
如图1所示的那样,在布线层30上的预定位置上分别形成高于第一主面(前表面)36的突出的多个焊料凸起(IC连接端子)34,相应的焊料凸起34分别与安装在第一主面36上的IC芯片(半导体元件)38的底面上的多个连接端子39相连接。
上述焊料凸起34由Sn-Ag系、Sn-Ag-Cu系、Sn-Su系、Pb-Sn系或者Sn-Zn系等低熔点合金(在本实施例中为Sn-Cu系)所构成,相邻的焊料凸起34,34轴心间距离(间距)被配置为约150μm。而且,多个焊料凸起28和连接端子34被未图示的未充满材料所埋设。
而且,如图1所示的那样,在由第一芯板2、第二芯板6所形成的凹部9内,多个片状电容器(电子部件)20通过支持件(Sn-Sb类)19进行安装。相应的电容器20沿着图中的前后方向具有多个突出到两侧面的上端的电极21,例如,是把以钛酸钡为主要成分的介电体层和成为内部电极的Ni层交替层叠而成的陶瓷电容器,其尺寸为3.2mm×1.6mm×0.7mm。
片状电容器20的各个电极21通过支持件19与位于通孔导体11的下端的布线层(电子部件连接端子)17相连接。
而且,支持件19由熔点比上述焊料凸起28高的低熔点合金所构成。
而且,如图1所示的那样,在第二芯板6的背表面8和布线层27的下侧形成具有与上述相同厚度的焊料保护层(绝缘层)29,在向着作为其前表面(下表面)的第二主面3 1侧开口的开口部33内露出布线层27内的布线35。在相应的布线35的前表面上被覆Ni和Au镀膜,被用作与搭载该线路板1本身的未图示的主板等的印刷电路板的连接端子。
而且,片状电容器20所安装的凹部9的下侧在第二主面31侧开口,不形成布线层27和焊料保护层29。
根据以上这样的线路板1,在薄的第一芯板2上通过绝缘层(粘接层)5层叠厚的第二芯板6,并且,在第一芯板2的前表面3上形成构筑层BU,因此,不需要设置现有技术的昂贵的金属制的加强件,因此,能够以低成本进行制造。而且,安装在第一主面36上的IC芯片38的连接端子39和插入凹部9的片状电容器20的电极21通过焊料凸起34、布线层30,25,16、通路导体28,24、短的通孔导体11、布线层17和支持件19的短的路径进行连接。因此,能够降低相应路径上的环路电感和电阻,能够获得稳定的导通。
而且,从第一主面36突出的多个焊料凸起34可以形成在与经过贯通第一芯板2而与电子部件20导通的通孔导体11和贯通第一和第二芯板2、6的通孔导体14的布线相对应的位置上。因此,能够高密度配置多个焊料凸起34,能够确实地安装具有多个连接端子39的IC芯片38。
这样,本发明的线路板1,能够进行廉价的制造,并且,内部的电气特性稳定,同时,难于产生挠曲和翘曲。
图2表示作为线路板1的变形例的线路板1a的主要部分的断面。所涉及的线路板1a,如图2所示的那样,在具有由第一芯板2,第二芯板6和布线层16、25以及绝缘层23、26等组成的构筑层BU这点上,具有与线路板1共同的基本构造。下面对不同点进行说明。
如图2所示的那样,在由第一芯板2,第二芯板6所形成的凹部9中,多个片状电容器(电子部件)20a通过埋入树脂9a被内置。片状电容器20a具有与上述相同的尺寸和构造,沿着图2的前后方向具有多个突出到两侧面的上和下端的电极21、22。
电容器20a的上端的电极21与上述相同通过支持件19与布线层17相连接,但是,下端的电极22与形成在第二芯板6的背表面8和埋入树脂9a下并且具有预定图形的铜制布线层27相连接。而且,埋入树脂9a的下侧焊料保护层29所覆盖。
上述那样的线路板1a在上述线路板1的优点的基础上,还能够使片状电容器20a坚固地内置在凹部9中。
下面通过图3至图5来说明上述线路板1,1a的主要制造工序。
图3(A)表示在前表面3和背表面4上分别粘贴了厚约为18μm的铜箔3a和4a的厚度约为400μm的第一芯板2。如图3(A)所示的那样,在第一芯板2的前表面3侧的中央部的位置上照射CO2等激光L。
其结果,如图3(B)所示的那样,形成多个贯通第一芯板2的前表面3,背表面4之间并且内径约为100μm的通孔10。而且,可以使用细直径的钻机取代激光L钻出通孔10。
接着,对于具有多个通孔10的第一芯板2的整个表面进行非电解镀铜和电解镀铜。而且,在各个通孔10的内壁上预先涂敷包含Pd的电镀触媒。而且,上述通孔10的穿孔和镀铜可以在包含多个芯板2(产品单位)的面板状态下进行。
其结果,如图3(C)所示的那样,沿着各个通孔10的内壁形成厚度约为25μm的通孔导体11。在各个通孔导体11的内侧填充由加入了硅酸盐填料等的无机填料的环氧类树脂所构成的填充树脂12。而且,可以使用包含大量的金属粉末的导电性树脂或者包含金属粉末的非导电性树脂来代替所涉及的填充树脂12。
接着,在前表面3和背表面4的铜箔(包含上述铜镀层)3a和4a上,通过公知的光刻法技术,来形成具有预定图形的未图示的抗蚀层,然后,腐蚀掉从抗蚀层的图形间露出的铜箔3a和4a(即公知的除去法)。
其结果,如图3(D)的上方所示的那样,在第一芯板2的前表面3、背表面4上分别形成仿照上述图形的布线层16、17。
而且,如图3(D)的下方所示的那样,另外准备厚度约为800μm的第二芯板6。在所涉及的第二芯板6的前表面7和背表面8上通过与上述相同的方法预先形成预定图形的布线层18和27,同时,在其中央部通过穿孔等来开出从平面看大致正方形的通孔9。
如图3(D)所示的那样,在第一芯板2的背表面4与在第二芯板6的前表面7上并且除去了通孔9的位置之间,配置由具有粘接性的树脂(半固化片)所构成的绝缘层(粘接层)5,在此状态下,沿着图3(D)中所述的箭头的方向加热并且压接第一和第二芯板2、6。而且,除了半固化片5之外,可以使用薄膜状的粘接层。
其结果,如图4(A)所示的那样,第一和第二芯板2,6通过绝缘层5被层叠起来,同时,上述通孔9成为向第二芯板6的背表面8侧开口的凹部9。在所涉及的状态下,在除了凹部9的上方的图4(A)中左右的预定位置上,进行由与上述相同的激光L的照射或钻机所进行的穿孔。
其结果,如图4(B)所示的那样,在左右的各个预定位置上,分别开出贯通包含绝缘层5和第一和第二芯板2、6的前表面3,背表面8之间的长通孔13。所涉及的通孔13贯通了在其中间位于绝缘层5的两侧的布线层17、18。
接着,在各个通孔13的内壁上涂敷与上述相同的电镀触媒,然后,进行非电解镀铜和电解镀铜。其结果,如图4(C)所示的那样,形成沿着各个通孔13的内壁的通孔导体14。而且,用未图示的带子堵住该开口部或者预先填充树脂,在上述电镀之后,去除以使电镀液不能侵入凹部9内。
接着,如图4(C)所示的那样,在各个通孔导体14的内侧分别填充与上述相同的填充树脂15,然后,把它们的上下端进行盖镀。而且,凹部9的上方的各个通孔导体11的上下端同样进行盖镀。
如图5(A)所示的那样,把上述第一和第二芯板2、6旋转180度,成为上下颠倒的状态,通过未图示的芯片固定件,在向上开口的凹部9中插入片状电容器20或片状电容器20a。此时,预先在位于凹部9内的底面的布线层(电子部件连接端子)17上形成支持件19,通过该支持件19,分别连接片状电容器20、20a的电极21和布线层17。
在此之前的工序中,既然线路板1的制造工序已结束,以后接着对线路板1a的制造工序进行说明。
如图5(B)所示的那样,在注入熔在凹部9内的埋入树脂9a之后,进行脱泡处理和加热到约100℃并保持约60分钟的固化处理。接着,例如通过研磨等把埋入树脂9a突出的背表面9b整形为平坦的。
其结果,如图5(C)所示的那样,形成使各个片状电容器20a的电极22露出的平坦的前表面9c。在电极22上形成布线层27。
在此以后或者在上述图5(A)的状态下,通过公知的构筑工序(半添加法、全添加法、除去法、通过薄膜状树脂材料的层叠形成绝缘层、光刻技术等)来形成将成为上述构筑层BU的布线层25、30和绝缘层23、26、32,通孔导体24、28等。由此,能够得到上述图1或图2所示的线路板1、1a。
图6表示线路板1、1a的应用形态的线路板1b的主要部分的断面。而且,下面对与上述例子相同的部分和要素使用共同的标号。
Claims (3)
1.一种线路板,其特征在于,包含:
具有前表面和背表面的第一芯板;
层叠在该第一芯板的背表面侧的第二芯板,所述第二芯板具有形成于其中的通孔,第一芯板与该通孔一起形成凹部;
形成在上述第一芯板的前表面上方并且包含多个布线层和多个绝缘层的构筑层;
其中,所述第一和第二芯板由玻璃环氧树脂制成,并且
所述第二芯板比第一芯板厚。
2.根据权利要求1所述的线路板,其特征在于,在上述第一芯板与具有上述通孔的第二芯板之间插入粘接层和布线层。
3.根据权利要求1或2所述的线路板,其特征在于,上述第一芯板的厚度在100μm以上,400μm以下,上述第二芯板的厚度在500μm以上,1000μm以下。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001086015A JP2002290030A (ja) | 2001-03-23 | 2001-03-23 | 配線基板 |
JP86015/2001 | 2001-03-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1377216A CN1377216A (zh) | 2002-10-30 |
CN1256006C true CN1256006C (zh) | 2006-05-10 |
Family
ID=18941449
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB021053065A Expired - Fee Related CN1256006C (zh) | 2001-03-23 | 2002-02-22 | 线路板 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7102085B2 (zh) |
JP (1) | JP2002290030A (zh) |
CN (1) | CN1256006C (zh) |
TW (1) | TW595296B (zh) |
Families Citing this family (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020053734A1 (en) | 1993-11-16 | 2002-05-09 | Formfactor, Inc. | Probe card assembly and kit, and methods of making same |
US20100065963A1 (en) | 1995-05-26 | 2010-03-18 | Formfactor, Inc. | Method of wirebonding that utilizes a gas flow within a capillary from which a wire is played out |
US7262611B2 (en) | 2000-03-17 | 2007-08-28 | Formfactor, Inc. | Apparatuses and methods for planarizing a semiconductor contactor |
US6729019B2 (en) | 2001-07-11 | 2004-05-04 | Formfactor, Inc. | Method of manufacturing a probe card |
JP3446124B2 (ja) * | 2001-12-04 | 2003-09-16 | 科学技術振興事業団 | 高速入出力装置を備えた半導体集積回路装置の試験方法及び試験装置 |
US6774324B2 (en) | 2002-12-12 | 2004-08-10 | Agilent Technologies, Inc. | Switch and production thereof |
JP4181510B2 (ja) | 2003-02-28 | 2008-11-19 | 日本特殊陶業株式会社 | 樹脂製配線基板 |
JP2004282033A (ja) * | 2003-02-28 | 2004-10-07 | Ngk Spark Plug Co Ltd | 樹脂製配線基板 |
DE102004031878B3 (de) * | 2004-07-01 | 2005-10-06 | Epcos Ag | Elektrisches Mehrschichtbauelement mit zuverlässigem Lötkontakt |
US20060051912A1 (en) * | 2004-09-09 | 2006-03-09 | Ati Technologies Inc. | Method and apparatus for a stacked die configuration |
US7515434B2 (en) * | 2004-12-20 | 2009-04-07 | Nortel Networks Limited | Technique for enhancing circuit density and performance |
JP2006216711A (ja) * | 2005-02-02 | 2006-08-17 | Ibiden Co Ltd | 多層プリント配線板 |
JP2006216713A (ja) * | 2005-02-02 | 2006-08-17 | Ibiden Co Ltd | 多層プリント配線板 |
JP2007005246A (ja) * | 2005-06-27 | 2007-01-11 | Sumitomo Electric Ind Ltd | 多孔質樹脂基材及び多層基板 |
EP1887846A4 (en) * | 2005-06-30 | 2010-08-11 | Ibiden Co Ltd | CIRCUIT BOARD |
CN101868120A (zh) * | 2005-06-30 | 2010-10-20 | 揖斐电株式会社 | 印刷线路板及其制造方法 |
CN101317187B (zh) * | 2005-11-28 | 2015-05-27 | Nxp股份有限公司 | 包括具有电触点的基板的器件和发射机应答器 |
TWI296910B (en) * | 2005-12-27 | 2008-05-11 | Phoenix Prec Technology Corp | Substrate structure with capacitance component embedded therein and method for fabricating the same |
US7462784B2 (en) * | 2006-05-02 | 2008-12-09 | Ibiden Co., Ltd. | Heat resistant substrate incorporated circuit wiring board |
JP5108253B2 (ja) * | 2006-05-09 | 2012-12-26 | 大日本印刷株式会社 | 部品実装モジュール |
US20080054490A1 (en) | 2006-08-31 | 2008-03-06 | Ati Technologies Inc. | Flip-Chip Ball Grid Array Strip and Package |
JP5064768B2 (ja) * | 2006-11-22 | 2012-10-31 | 新光電気工業株式会社 | 電子部品および電子部品の製造方法 |
US20080157335A1 (en) * | 2006-12-28 | 2008-07-03 | Jia Miao Tang | Strip patterned transmission line |
US20080205023A1 (en) | 2007-02-27 | 2008-08-28 | International Business Machines Corporation | Electronic components on trenched substrates and method of forming same |
US7893527B2 (en) * | 2007-07-24 | 2011-02-22 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor plastic package and fabricating method thereof |
TW200917446A (en) * | 2007-10-01 | 2009-04-16 | Phoenix Prec Technology Corp | Packaging substrate structure having electronic component embedded therein and fabricating method thereof |
KR20090042556A (ko) * | 2007-10-26 | 2009-04-30 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
JPWO2009107747A1 (ja) * | 2008-02-29 | 2011-07-07 | 日本発條株式会社 | 配線基板およびプローブカード |
US8058723B2 (en) * | 2008-03-19 | 2011-11-15 | Phoenix Precision Technology Corporation | Package structure in which coreless substrate has direct electrical connections to semiconductor chip and manufacturing method thereof |
JP2008306227A (ja) * | 2008-09-25 | 2008-12-18 | Panasonic Electric Works Co Ltd | 凹凸多層回路板モジュール及びその製造方法 |
US9420707B2 (en) * | 2009-12-17 | 2016-08-16 | Intel Corporation | Substrate for integrated circuit devices including multi-layer glass core and methods of making the same |
US8207453B2 (en) * | 2009-12-17 | 2012-06-26 | Intel Corporation | Glass core substrate for integrated circuit devices and methods of making the same |
US10297550B2 (en) * | 2010-02-05 | 2019-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D IC architecture with interposer and interconnect structure for bonding dies |
US8624127B2 (en) * | 2010-02-26 | 2014-01-07 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
JP5623308B2 (ja) * | 2010-02-26 | 2014-11-12 | 日本特殊陶業株式会社 | 多層配線基板及びその製造方法 |
JP5550526B2 (ja) | 2010-10-29 | 2014-07-16 | Tdk株式会社 | 積層型電子部品およびその製造方法 |
TWI402007B (zh) * | 2010-11-29 | 2013-07-11 | Hon Hai Prec Ind Co Ltd | 印刷電路板 |
US9058455B2 (en) * | 2012-01-20 | 2015-06-16 | International Business Machines Corporation | Backside integration of RF filters for RF front end modules and design structure |
US9445496B2 (en) | 2012-03-07 | 2016-09-13 | Intel Corporation | Glass clad microelectronic substrate |
JP5904856B2 (ja) * | 2012-04-23 | 2016-04-20 | キヤノン株式会社 | プリント配線板、半導体パッケージ及びプリント回路板 |
US9001520B2 (en) | 2012-09-24 | 2015-04-07 | Intel Corporation | Microelectronic structures having laminated or embedded glass routing structures for high density packaging |
US9615453B2 (en) | 2012-09-26 | 2017-04-04 | Ping-Jung Yang | Method for fabricating glass substrate package |
US10622310B2 (en) | 2012-09-26 | 2020-04-14 | Ping-Jung Yang | Method for fabricating glass substrate package |
US9293426B2 (en) * | 2012-09-28 | 2016-03-22 | Intel Corporation | Land side and die side cavities to reduce package Z-height |
CN103857211B (zh) * | 2012-11-28 | 2017-03-01 | 富葵精密组件(深圳)有限公司 | 透明电路板及其制作方法 |
KR101420526B1 (ko) * | 2012-11-29 | 2014-07-17 | 삼성전기주식회사 | 전자부품 내장기판 및 그 제조방법 |
US10251269B2 (en) * | 2012-12-27 | 2019-04-02 | Kyocera Corporation | Wiring board, electronic device, and light emitting apparatus |
US8803310B1 (en) * | 2013-02-08 | 2014-08-12 | Unimicron Technology Corp. | Embedded electronic device package structure |
US9185794B1 (en) * | 2013-07-31 | 2015-11-10 | Juniper Networks, Inc. | Apparatus and methods for placement of discrete components on internal printed circuit board layers |
JP2015095587A (ja) * | 2013-11-13 | 2015-05-18 | 日本特殊陶業株式会社 | 多層配線基板 |
US9502490B2 (en) * | 2014-05-21 | 2016-11-22 | Qualcomm Incorporated | Embedded package substrate capacitor |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9198296B1 (en) * | 2015-01-06 | 2015-11-24 | Kinsus Interconnect Technology Corp. | Double sided board with buried element and method for manufacturing the same |
KR20180090527A (ko) * | 2017-02-03 | 2018-08-13 | 삼성전기주식회사 | 반도체 패키지와 그 제조 방법 |
JP6845316B2 (ja) * | 2017-05-23 | 2021-03-17 | 京セラ株式会社 | 多数個取り配線基板、電子部品収納用パッケージ、および電子装置 |
US20190164891A1 (en) * | 2017-11-27 | 2019-05-30 | Finisar Corporation | Tunable differential via circuit |
JP2019121763A (ja) * | 2018-01-11 | 2019-07-22 | イビデン株式会社 | プリント配線板およびその製造方法 |
US11222850B2 (en) | 2019-05-15 | 2022-01-11 | Mediatek Inc. | Electronic package with rotated semiconductor die |
JP2022146063A (ja) * | 2021-03-22 | 2022-10-05 | キヤノン株式会社 | 電子モジュール及び電子機器 |
JP2023045290A (ja) * | 2021-09-21 | 2023-04-03 | キオクシア株式会社 | 記憶装置 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3112059B2 (ja) * | 1995-07-05 | 2000-11-27 | 株式会社日立製作所 | 薄膜多層配線基板及びその製法 |
JP3961092B2 (ja) * | 1997-06-03 | 2007-08-15 | 株式会社東芝 | 複合配線基板、フレキシブル基板、半導体装置、および複合配線基板の製造方法 |
US6272020B1 (en) * | 1997-10-16 | 2001-08-07 | Hitachi, Ltd. | Structure for mounting a semiconductor device and a capacitor device on a substrate |
JP2000357873A (ja) * | 1999-06-17 | 2000-12-26 | Hitachi Ltd | 多層配線基板及びその製造方法 |
US6392301B1 (en) * | 1999-10-22 | 2002-05-21 | Intel Corporation | Chip package and method |
US6370013B1 (en) * | 1999-11-30 | 2002-04-09 | Kyocera Corporation | Electric element incorporating wiring board |
JP2001237512A (ja) * | 1999-12-14 | 2001-08-31 | Nitto Denko Corp | 両面回路基板およびこれを用いた多層配線基板ならびに両面回路基板の製造方法 |
US6480395B1 (en) * | 2000-05-25 | 2002-11-12 | Hewlett-Packard Company | Device and method for interstitial components in a printed circuit board |
US6495770B2 (en) * | 2000-12-04 | 2002-12-17 | Intel Corporation | Electronic assembly providing shunting of electrical current |
US6426470B1 (en) * | 2001-01-17 | 2002-07-30 | International Business Machines Corporation | Formation of multisegmented plated through holes |
-
2001
- 2001-03-23 JP JP2001086015A patent/JP2002290030A/ja not_active Withdrawn
-
2002
- 2002-02-22 CN CNB021053065A patent/CN1256006C/zh not_active Expired - Fee Related
- 2002-03-12 TW TW091104552A patent/TW595296B/zh not_active IP Right Cessation
- 2002-03-22 US US10/103,039 patent/US7102085B2/en not_active Expired - Fee Related
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US20020145197A1 (en) | 2002-10-10 |
TW595296B (en) | 2004-06-21 |
US7102085B2 (en) | 2006-09-05 |
JP2002290030A (ja) | 2002-10-04 |
CN1377216A (zh) | 2002-10-30 |
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