CN1783473B - 绝缘衬底和半导体器件 - Google Patents

绝缘衬底和半导体器件 Download PDF

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CN1783473B
CN1783473B CN2005101287160A CN200510128716A CN1783473B CN 1783473 B CN1783473 B CN 1783473B CN 2005101287160 A CN2005101287160 A CN 2005101287160A CN 200510128716 A CN200510128716 A CN 200510128716A CN 1783473 B CN1783473 B CN 1783473B
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dielectric substrate
insulating barrier
metallic substrates
circuit pattern
ceramic
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CN1783473A (zh
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冈本健次
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Fuji Electric Co Ltd
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Fuji Electric Systems Co Ltd
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/053—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
    • C—CHEMISTRY; METALLURGY
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Abstract

一种绝缘衬底设有：作为基底构件的金属基底；用气溶胶淀积法形成在金属基底上的室温冲击固化膜；和用冷喷涂法形成在绝缘层上的热喷涂涂层的电路图案。一种半导体器件包含这种绝缘衬底，从而提高了热辐射特性。

Description

绝缘衬底和半导体器件 
技术领域
本发明涉及具有增加的热辐射能力的绝缘衬底和包括这种绝缘衬底的半导体器件。 
背景技术
具有能量转换功能的半导体器件被广泛应用于包括诸如家用空调器和冰箱在内的消费装置和包括诸如逆变器和伺服控制器在内的工业装置。 
在这样的半导体器件中，因为绝缘衬底的热阻的减小能显著地改善热辐射特性，绝缘衬底正在努力地予以开发。 
有关这种绝缘衬底的传统技术将参照附图在下面描述。图5是示出传统的绝缘衬底500的结构的剖视图。传统的绝缘衬底500设有金属基底501，绝缘层502和电路图案503。 
金属基底是铝板、铝合金板、铜板、铜合金板等等。 
绝缘层502是通过固化包含诸如氧化硅(SiO2)、氧化铝(Al2O3)或氮化铝(AlN)的无机填充料的环氧树脂形成的绝缘层，且通常具有大约为7.0-10.0W/m·k的热传导率。 
例如，电路图案503是铜薄膜图案。 
因为它出众的散热性能，具有上述三层结构的绝缘衬底500被用作其上安装诸如功率半导体器件的高热产生元件的布线衬底。特别是，绝缘衬底500被用作用在电源装置中的电源电路组件的布线板的衬底。因为如上述的它的热传导率大约是7.0-10.0W/m·k，通常可以将绝缘衬底500应用到电流容量为约50A或更低的电源电路组件。但是，很难将绝缘衬底500应用到电流容量超过约50A的电源电路组件。 
另一个与绝缘衬底有关的传统技术将参照附图在下面描述。图6(a)是示出普通形式传统的绝缘衬底600的结构的剖视图。图6(b)是示出包括金属基底基体的传统绝缘衬底的结构的剖视图。如图6a中所示，绝缘衬底600设有陶 瓷基底基体601、第一电路图案602、第二电路图案603。 
陶瓷基底基体是主要由氧化铝(Al2O3)、氮化铝(AlN)、氮化硅(Si3N4)等制成的板，并具有大约0.2-0.8mm的厚度。在氧化铝(Al2O3)的情况热传导率为大约20W/m·k，在氮化铝(AlN)的情况热传导率为大约160-180W/m·k，及在氮化硅(Si3N4)的情况热传导率为大约80W/m·k，因此比类似图5中示出的绝缘层502的由包含无机填充料的环氧树脂制成的绝缘层要高出一个或两个数量级。 
第一电路图案602是在陶瓷基底基体601下面形成的图案。由于是铜或铝的金属箔，第一电路图案602被直接或用钎焊材料连接到陶瓷基底基体601。通常，第一电路图案602只是不具有电路图案的固体板体。第一电路图案602接地。 
第二电路图案603是在陶瓷基底基体601上面形成的图案。由于是铜或铝的金属箔，第一电路图案602被直接或用钎焊材料连接到陶瓷基底基体601。第二电路图案是普通的电路图案。 
在电路图案形成在具有高热传导率的陶瓷基底基体601的两侧的绝缘衬底600中，由装配在第二电路图案603上的功率半导体器件(未示出)产生的热量经由陶瓷基底基体601→第一电路图案602的路径散发。这使得更高容量的电源器件和电流容量超过50A的功率半导体器件能够使用，这用上述的绝缘衬底500不能够实现。 
图6(b)示出了诸如2-3mm厚的铜板的金属基底基体604经由钎料部分605连接到绝缘衬底600的另一种结构(模块结构)。 
在这个电路图案形成在陶瓷基底基体601的两侧的绝缘衬底中，由装配在第二电路图案603的电源半导体器件(未示出)产生的热量经由陶瓷基底基体601→第一电路图案602→钎料部分605→金属基底基体604的路径散发。这使得更高容量的功率器件和电流容量超过50A的功率半导体器件能够使用，这用上述的绝缘衬底500不能够实现。 
例如，第JP-A-2004-47863号发明(第26-32段和图1-3)是另一个有关旨在改善热辐射特性的传统技术。该引用揭示了通过气溶胶淀积法在导电衬底一个表面上形成陶瓷层的技术。 
如上所述，包括陶瓷基底基体的绝缘衬底600的使用在电流容量超过50A的应用中较佳。 
但是，结合陶瓷基底基体的绝缘衬底600因为以下原因存在昂贵的问题。为制造绝缘衬底600，首先，在高温通过焙烧形成陶瓷基底基体601，通过揉搓材料粉末和粘合剂在一起形成薄板(称为“生薄板”(green sheet))。然后，各自为铜箔或铝箔的第一和第二图案602和603在高温时被连接到陶瓷基底基体601以制成绝缘衬底600。照此，包括陶瓷作为材料的绝缘衬底600在形成陶瓷基底基体601方面需要许多制造步骤，导致高价格。 
在JP-A-2004-47863的半导体器件中，通过普通的电镀技术等形成布线图案。存在着通过对布线图案的改进来改善总的热辐射特性的需要。 
发明内容
考虑到现有技术的上述问题做出本发明，因此本发明的目的是提供因为减少了制造步骤的数量而价格便宜的以及具有出众的热辐射和绝缘性能的绝缘衬底。 
本发明的另一目的是提供使用这种绝缘衬底的半导体器件。 
为达到上面的目的，依据本发明第一方面的绝缘衬底包括作为基底构件的金属基底；形成在金属基底上的室温冲击固化膜；和作为形成在绝缘层上的热喷涂涂层的电路图案。 
依据本发明第二方面的绝缘衬底是这样的，在依据本发明第一方面的绝缘衬底中，绝缘层是通过使陶瓷微粒与金属基底碰撞而连接到金属基底的室温冲击固化膜的陶瓷层，陶瓷微粒由氧化硅、氧化铝、氮化硅、氮化硼和氮化铝中的至少一种制成。 
依据本发明第三方面的绝缘衬底是这样的，在依据本发明第二方面的绝缘衬底中，由氧化硅和氧化铝组成的第一组中的至少一种和由氮化硅、氮化硼、氮化铝组成的第二材料组中的至少一种制成。 
依据本发明第四方面的绝缘衬底是这样的，在依据本发明第一个方面的绝缘衬底中，绝缘层是通过使陶瓷微粒与金属基底碰撞而连接到金属基底的室温冲击固化膜的陶瓷层，陶瓷微粒由表面形成有氧化铝涂层的氮化硅、氮化硼和 氮化铝中的至少一种制成。 
依据本发明第五方面的绝缘衬底是这样的，在依据本发明第一方面的绝缘衬底中，绝缘层是通过使陶瓷微粒与金属基底碰撞连接到金属基底的室温冲击固化膜的陶瓷层，陶瓷微粒由表面形成有氧化硅涂层的氮化硅、氮化硼和氮化铝中的至少一种制成。 
依据本发明第六方面的绝缘衬底是这样的，在依据本发明第一到第四方面的任一绝缘衬底中，电路图案是通过铜、铝、镍、铁、钛、钼中的一种金属或它们的合金热喷涂形成的热喷涂涂层。 
依据本发明第七方面的绝缘衬底是这样的，在依据本发明第一到第六方面中的任一绝缘衬底中，绝缘层是用气溶胶淀积法形成的室温冲击固化膜。 
依据本发明第八方面的绝缘衬底是这样的，在依据本发明第一到第七方面中的任一绝缘衬底中，电路图案是用冷喷涂方法形成的热喷涂涂层。 
依据本发明第九方面的半导体器件包括依据本发明第一到第八方面的任何一个的绝缘衬底；粘结到绝缘衬底的金属基底的树脂外壳；装配在绝缘衬底的电路图案上和放置在树脂外壳中的功率器件；充满在树脂外壳中的绝缘树脂，从而使绝缘衬底的绝缘层电路图案以及功率器件被封入且与外界隔开。 
依据本发明第十方面的半导体器件包括依据本发明第一到第八方面的任何一个的绝缘衬底；装配在绝缘衬底的电路图案上的功率器件；以及形成的热固性树脂以使得绝缘衬底的金属基底的一部分暴露于外界及使绝缘衬底的绝缘层和电路图案以及功率器件被封入且与外界隔开。 
上述方面能够提供由于减少了制造步骤而价格便宜的以及具有出众的热辐射和绝缘性能的绝缘衬底。 
本发明也能够提供使用这种绝缘衬底的半导体器件。 
附图说明
图1是示出依据本发明实施例的绝缘衬底的结构的剖视图； 
图2(a)-2(d)示出了绝缘衬底的制造方法； 
图3是示出依据本发明实施例的半导体器件的结构的剖视图； 
图4是示出依据本发明另一个实施例的半导体器件的结构的剖视图； 
图5示出传统的绝缘衬底的结构的剖视图； 
图6(a)是示出普通形式的另一个传统的绝缘衬底的结构的剖视图； 
图6(b)是示出包括金属基底基体的另一个传统绝缘衬底的结构的剖视图。 
具体实施方式
依据本发明实施例的绝缘衬底和半导体器件在下文中将参照附图做出描述。图1是示出依据本发明实施例的绝缘衬底的结构的剖视图。绝缘衬底1设有金属基底2，绝缘层3和电路图案4。 
金属基底是诸如铝板、铝合金板、铜板、或铜合金板的金属板。 
绝缘层3是通过气溶胶淀积法形成的室温冲击固化膜(room temperatureshock solidification film)。绝缘层3的厚度考虑到热阻、绝缘特性等而设置，并通常设置为约300-400微米。通过气溶胶淀积法在结晶状态形成，绝缘层3的热传导率变得等于或接近于即使是由任何材料制成的绝缘体本体的热传导率。通过气溶胶淀积法形成绝缘层3的方式将在以后描述。 
绝缘层3可以由任何不同种类的材料制成。例如，绝缘层3可以是以这种方式形成的室温冲击固化膜：氧化硅(SiO2)、氧化铝(Al2O3)、氮化硅(Si3N4)、氮化硼(BN)、氮化铝(AlN)中的至少一种的陶瓷微粒是由气溶胶淀积法室温冲击固化的，即，陶瓷微粒通过以微粒表面被激活并且然后彼此结合的这种方式产生的晶界相被结合在一起。 
在这种情况下，获得了约1.3-2.0W/m·k(在氧化硅(SiO2)的情况下)、约20W/m·k(在氧化铝(Al2O3)的情况下)、约80W/m·k(在氮化硅(Si3N4)的情况下)、36-75W/m·k(在氮化硼(BN)的情况下)，或约160-180W/m·k(在氧化硅(SiO2)的情况下)的热传导率，从而改善了热辐射特性。 
在这些材料中，氧化硅(SiO2)和氧化铝(Al2O3)适合增加在形成室温冲击固化膜的过程中的粘着性。 
另一种形成绝缘层的方法是这样的：由氧化硅(SiO2)和氧化铝(Al2O3)组成的第一材料组中的至少一种制成的微粒与由氮化硅(Si3N4)、氮化硼(BN)、氮化铝(AlN)组成的第二材料组中的至少一种制成的微粒混和，并且，得到的微粒通过气溶胶淀积法是室温冲击固化的。在这种情况下，由于：氧化硅 (SiO2)和氧化铝(Al2O3)的微粒牢固地结合在一起，形成了作为致密陶瓷层的牢固涂层。 
还有一种形成了绝缘层3的方法是这样的：把其表面预先用氧化铝(Al2O3)涂层形成的氮化硅(Si3N4)、氮化硼(BN)、氮化铝(AlN)中的至少一种的陶瓷微粒，借助气溶胶淀积法将那些微粒喷涂在金属基底2上碰撞进行室温冲击固化。在这种情况下，作为表面涂层的氧化铝(Al2O3)和作为籽晶的氮化硅(Si3N4)、氮化硼(BN)，或氮化铝(AlN)彼此牢固地结合，由此形成致密的室温冲击固化膜。 
还有一种形成了绝缘层3的方法是这样的：把其表面预先用氧化硅(SiO2)涂层形成的氮化硅(Si3N4)、氮化硼(BN)、氮化铝(AlN)中的至少一种的陶瓷微粒，借助气溶胶淀积法将那些微粒喷涂在金属基底2上碰撞进行室温冲击固化。在这种情况下，作为表面涂层的氧化硅(SiO2)和作为籽晶的氮化硅(Si3N4)、氮化硼(BN)，或氮化铝(AlN)彼此牢固地结合，由此形成致密的室温冲击固化膜。 
电路图案4是期望的电路图案，该电路图案是通过将铜、铝、镍、铁、钛和钼中的一种金属用冷喷涂方法热喷涂形成在绝缘层3上的热喷涂涂层。形成电路图案4的材料可以是上述金属中的一种的合金。电路图案4是热喷涂涂层具有此优点：因为热喷涂涂层的表面与绝缘层紧密接触，即使涂层较薄也能提供较高的电流密度。 
能够使电路图案4变薄的特征有助于改善热辐射特性。 
接下来，将参照附图描述绝缘衬底1的制造方法。图2(a)-2(d)示出了绝缘衬底1的制造方法。 
图2(a)示出了通过气溶胶淀积法在预先形成的金属基底上形成绝缘层的绝缘层成形过程。更具体地说，图2(a)示出了通过把陶瓷微粒喷涂在金属基底2上的气溶胶淀积法正在形成绝缘层的状态。金属基底2四周的区域覆盖掩膜5。掩膜5的厚度与所需绝缘层3的厚度接近。 
气溶胶淀积法是一种以这样的方式形成涂层的技术：作为材料的微粒和超细微粒与诸如氦或空气的的气体相混和以形成气溶胶，并且从喷嘴发射气溶胶使之与衬底相撞，藉此微粒和超细微粒通过室温冲击固化淀积在衬底上。 
使用在这个实施例中的微粒和超细微粒是如通过机械研磨(粒子直径：0.1-2微米)产生的粉末的陶瓷微粒。对气溶胶淀积法的说明将在假设陶瓷微粒由氧化铝(Al2O3)、氮化硅(Si3N4)、氮化硼(BN)、氮化铝(AlN)中的一种组成的情况下继续。 
装置由气溶胶形成室和膜形成室组成。通过真空泵膜形成室内部的压力被降低到50Pa到1Kpa。通过搅拌作为材料的干陶瓷粒子和气体相混和在气溶胶形成室中形成气溶胶。由于是干的，陶瓷粒子不会粘进大粒子中。 
装置在上述状态被启动，在该装置中由两个室之间的压力差引起的气流运送的陶瓷微粒被传送到膜成形室。在气溶胶成形室和膜成形室之间设置有粉碎机和分选机。当陶瓷微粒通过粉碎机时，粘着的粒子被粉碎成陶瓷微粒，且具有小直径的陶瓷微粒被允许通过分选机。依靠这些措施，仅具有小直径的个别陶瓷微粒被传送到膜成形室。这些陶瓷微粒通过槽状喷嘴并从而被加速到100m/s。被加速的陶瓷微粒被喷涂在金属基底2上。 
直径在5纳米到1微米范围之间的陶瓷微粒以高速与金属基底2相碰撞。其中直径小于大约几十纳米的陶瓷微粒被使用，它们互相结合(如下所述它们中的一部分被压碎或变形)，藉此形成致密的陶瓷层。其中直径在大约几十纳米到1微米范围之间的陶瓷微粒被使用，它们被压碎或变形成厚度(尺寸)在0.5-20纳米范围之间的数片，并且被压碎的片互相结合，从而形成致密的陶瓷层。在这个陶瓷层中，陶瓷片相互结合得如此致密以致没有晶界可辨别。陶瓷层能够在室温形成，就是说，不需要温度的增加。 
陶瓷微粒可以由氧化硅、氧化铝、氮化硅、氮化硼和氮化铝中的一种制成。使用以这种方式至少一种材料制成的陶瓷微粒使形成如此致密以致没有晶界可辨别的绝缘层成为可能。 
或者，陶瓷微粒可以由氧化硅和氧化铝组成的第一材料组中的至少一种与由氮化硅、氮化硼、氮化铝组成的第二材料组中的至少一种制成。其中陶瓷微粒由通过从两组材料的每一组选择至少一种材料确定的材料制成，第一组的陶瓷微粒和第二组的陶瓷微粒互相牢固地结合，藉此能够形成如此致密以致没有晶界可辨别的绝缘层。 
作为另一种选择，可以使用由氮化硅、氮化硼和氮化铝中的至少一种制成的和其表面由氧化铝涂层形成的陶瓷微粒或由氮化硅、氮化硼和氮化铝中的至少一种制成的和其表面由氧化硅涂层形成的陶瓷微粒。在表面由氧化铝涂层或氧化硅涂层形成的陶瓷微粒中，氧化铝或氧化硅与由氮化硅、氮化硼或氮化铝制成的陶瓷微粒牢固地结合，藉此能够形成如此致密以致没有晶界可辨别的绝缘层。
例如，陶瓷微粒可以是这样的以使得具有1-100纳米厚度的氧化铝或氧化硅涂层形成在由氮化硅、氮化硼或氮化铝制成的并具有5纳米到1微米的粒子直径的籽晶填料的表面上。期望使用氧化铝(Al2O3)、氮化铝(AlN)和氮化硅(Si3N4)。特别期望使用作为主要材料的具有高热传导率的氮化铝(AlN)。 
这样形成的绝缘层是陶瓷粒子致密地相互结合的陶瓷层。因此，即使厚度降低到几个微米到100微米绝缘层3也具有想得到的击穿电压。 
根据绝缘层3的膜形成率，使用直径在几十个纳米到1微米的范围中的陶瓷微粒是有利的。在陶瓷微粒的喷涂被执行规定的时间后最后形成如图2(b)所示的绝缘层3。 
上面的绝缘层3的形成具有以下优点： 
(1)增加的绝缘击穿电压 
在气溶胶淀积方法中，在室温能形成膜并且使亚微细粒级的陶瓷微粒以可与声速相比的速度与衬底碰撞。因此，新活化的表面(active fresh surface)被暴露的陶瓷微粒互相结合，藉此能够形成是非常致密的绝缘膜的陶瓷微粒层。在膜的内部没有孔隙，这样形成的绝缘层3展示了比传统焙烧方法形成的陶瓷衬底中的绝缘层大约高十倍的每单位长度击穿电压。 
(2)降低的热阻 
因为每单位长度击穿电压是增加的，绝缘层3能够做的更薄并且因此整个绝缘层3的热阻能够被降低。 
如上述项(1)和(2)所描述的，改善的绝缘性能和降低的热阻都能够得到保证。此外，绝缘层3能够在力学含义上牢固地粘结到金属基底2。 
在形成绝缘层3后，作为热喷涂涂层的电路图案4形成在绝缘层3上。 
图2(c)示出了电路图案形成过程，即，在用前述过程已经形成的绝缘层上通过冷喷涂方法形成电路图案4的过程。图(2)示出了用冷喷涂方法在形成在金属基底2的绝缘层3上喷涂金属粉末的状态。绝缘层3被掩膜6覆盖。掩膜6形成与所需电路图案相应的许多孔，并与电路图案4的厚度接近。 
冷喷涂方法，是一种热喷涂技术，是温度比热喷涂材料的熔点或软化温度更低的气体的超声流，并且热喷涂材料的粒子被放入流中，且从而被加速。造成仍然在固相的粒子以高速与基底构件相撞，藉此在基底构件上形成涂层。可以通过等离子喷涂法、火焰喷涂法、高速火焰喷涂法等替代冷喷涂法形成电路图案4。 
在冷喷涂法中，用于加热和加速热喷涂材料的粒子的工作气体的温度可以非常低。更具体地说，对比等离子喷涂中工作气体的温度要高达2000-8000℃的情况，工作气体的温度可以是大约为室温到600℃。热喷涂粒子不是非常热并因此在它们仍处于固相的状态使之与基底构件相撞。合成的能量在基底构件和粒子中产生塑性变形，结果是形成涂层。因此，可以使制造设备比传统的情况更简单，这也对降低制造成本有用。同样就所形成的电路图案的传导率和热传导率而言，这个实施例的制造方法比其它制造方法是有利的。 
至于所使用的装置，高压工作气体从诸如集气筒的气源供应到每一粉末供应装置和气体加热器。该气体是空气、氦气、氮气等等。 
部分操作的气体分流供应到粉末供应装置，并作为运载气体与热喷涂粉末一起流到热喷枪。 
作为主流的大多数工作气体通过由电炉等直接或间接加热的线圈形管道流动，在此期间它的温度被增加。工作气体然后被供应到热喷枪，并通过超声波喷嘴加速且从喷嘴喷出。 
工作气体并不总是热的。但是，加热工作气体是有利的因为它增加了粒子速度并促进粒子的塑性变形。 
热喷涂以上述状态开始，因此热喷涂粉末从超声喷嘴与工作气体一起喷出。 
在图2(c)中示出的冷喷涂中，使用其直径在1.0-50.0微米范围中的金属粒子。粒子材料的例子为铜、铝、铁、钛和钼。通常，铜或铝用于这个实施例的情况下的布线板的形成。这种金属粒子从距离绝缘层3处10-50mm的位置以500-900mm/s的速度经由掩膜6喷涂到绝缘层3上。金属粒子淀积在绝 缘层3上，藉此在绝缘层上形成作为图2(d)中示出的电路图案的热喷涂层。为了得到所需的膜厚度，喷涂在给定的时间完成。考虑电流密度设置电路图案4的厚度并且通常设置在约30-500微米。 
通过上述制造过程制造出具有三层结构的绝缘衬底。 
根据上面的制造方法，陶瓷绝缘层3能够直接在金属基底2上形成并且电路图案4能够在陶瓷绝缘层3上形成。因此，制造步骤的数量大为减少，因而制造成本比制造陶瓷布线板的传统方法大幅降低。此外，气溶胶淀积法和冷喷涂法都不需要加热到高温，这对降低制造成本也有用。 
此外，绝缘层3和电路图案4在热辐射特性方面都得到改善，藉此绝缘衬底1能够在热辐射性能上胜过传统的金属基底印刷布线板并被给予能与陶瓷相比的高的热传导率。此外，依靠高的绝缘阻抗，绝缘衬底1使高输出功率粉末设备能够使用。 
在上面的制造方法中，通过气溶胶淀积法以这种方式可以形成绝缘层3，使得通过调节掩膜5的开口3将陶瓷连续地粘结到金属基底1的一个主要表面和侧面的一部分。这种结构在获得高的绝缘体击穿电压方面是有利的，因为在绝缘层3和的电路图案4和金属基底2之间的漏电距离增加了。 
接下来，将参照附图描述使用上述绝缘衬底的半导体器件。图3是示出依照本发明实施例的半导体器件的结构的剖视图。 
半导体器件10是半导体组件并且设有绝缘衬底1、树脂外壳11、引线端子12、绝缘树脂13、功率器件14和铝线15。如图1所示，绝缘衬底1由金属基底2，通过气溶胶淀积法在金属基底2上形成的陶瓷绝缘层3，和通过冷喷涂法在绝缘层3上形成的金属电路图案4组成。 
半导体器件10具有供应电能的功能。由树脂(环氧树脂、PPS、PBT等等)制成的且与引线端子构成整体的树脂外壳11被粘结到绝缘衬底1，藉此形成了容纳空间。功率器件14的背电极和引线端子12安装(连接并固定)在绝缘衬底1的电路图案4上，功率器件14的其它电极经铝线15连接到电路图案4。由树脂外壳11形成的容纳空间充满着由具有高热传导率的硅树脂胶体、环氧树脂等制成的绝缘树脂13，藉此电源电路被封入。树脂外壳11的开口部分用由与树脂外壳11相同的树脂(环氧树脂、PPS、PBT等等)制成的盖子16覆 盖。 
通过在另一印刷电路板等等上面形成控制功率器件14的控制电路和将该印刷电路板放入上述容纳空间可以构成智能功率模块。 
如图3的圆形放大部分中所示，绝缘层3可以是将陶瓷连续地粘结到一个主要表面和粘结到金属基底2的侧面部分。这种结构在获得高的绝缘体击穿电压方面是有利的，因为在绝缘层3上的电路图案4和金属基底2之间的漏电距离增加了。 
功率器件14是作为用诸如IGBT(绝缘栅型双极晶体管)或FWD(续流二极管)的开关器件举例说明的功率半导体器件，并被安装在电路图案4上以形成电源电路。如需要，也可将电阻、电容、线圈等安装到电路图案4。通常，由于功率半导体器件产生热量，特别是，开关器件的开关操作产生热量，这种电源电路的温度会变高。但是，在半导体器件10中，所产生的热量经具有出色冷却性能的绝缘衬底1和固定到绝缘衬底1的金属基底2的散热片被散发。 
至于半导体器件10的制造方法，首先，将功率器件14装配在由气溶胶淀积法和冷喷涂法形成的绝缘衬底1的电路图案4上。然后，用硅树脂粘结剂等将树脂外壳11安装在绝缘衬底1的周围上。引线端子被插入并因此与树脂外壳11构成整体。然后，所需的功率器件14经铝线15被电气连接到电路图案4以形成电源电路。类似地，引线端子12经铝线15连接到电路图案4的引线部分。然后，诸如硅树脂胶体或环氧树脂的绝缘树脂13被喷射到电源电路上以绝缘和保护功率器件14等和它们的临近部分。最后，将树脂盖16粘结到树脂外壳11的开口部分。 
如上所述半导体器件被作为智能功率模块构成，在上面的过程中在粘结树脂盖16之前在另一块印刷电路板等等上面形成控制功率器件14的控制电路并且将该印刷电路板放入容纳空间。在半导体器件的内部当中，印刷电路板能够以不同方式连接到电源电路和引线端子，这些方式举例如下：电线粘结法和设有供内部连接的引线端子，通过印刷电路板的连接通孔插入并焊接到印刷电路板的方法。但是这些方法的详细说明予以省略。 
接下来，以下将参照附图描述依据本发明另一个实施例的半导体器件。图4是示出依据另一个实施例的半导体器件的剖视图。该半导体器件20不同于上 述半导体器件之处在于，未使用壳结构和用绝缘树脂22实现整体结构。该半导体器件以下面的方式形成。功率器件23和引线端子21安装(连接和固定)在绝缘衬底1的绝缘层3上的电路图案4上，并然后通过使用铝线作连接。密封树脂被施加到装配了功率器件23的金属基底侧，以使得没有形成绝缘层3的金属基底2的其它表面暴露，藉此形成绝缘树脂模22。如图1所示，绝缘衬底1由通过气溶胶淀积法在金属基底2上形成的陶瓷绝缘层3和通过冷喷涂法在绝缘层3上形成的金属电路图案4组成。 
由于其开关转换产生的热量，功率器件的温度变高。因此，在半导体器件20中，绝缘衬底1的金属基底2的一个表面(即没有形成绝缘层3的表面)暴露在热辐射的环境下。在绝缘衬底1的电路图案4上形成包括为功率半导体器件等的功率器件23的电源电路，并且在引线端子21向外引出的状态下将具有高热传导率的环氧树脂等施加到绝缘层3、绝缘衬底1的电路图案4以及功率器件23以形成绝缘树脂模22。绝缘衬底1的金属基底2暴露在外界中，这改善了冷却性能。 
如图4的圆形放大部分中所示，绝缘层3可以是将陶瓷连续地粘结到金属基底2的一个主要表面或侧面2a。这种结构在获得高的绝缘体击穿电压方面是有利的，因为在绝缘层3上的电路图案4和金属基底2之间的漏电距离增加了。 
半导体器件20的制造方法如下。首先，将功率器件23和引线端子21焊接到预先形成的绝缘基底1的电路图案4上。然后，用超声波键合通过铝线24把功率器件23、电路图案4和引线端子31电气地相互连接，藉此完成电源电路。 
然后，所得到的结构设置在与转移成型机器(transfer molding machine)的相连的模具中。模具的温度保持在170-180℃。通过预热，片状的环氧树脂用柱塞被注入模具中。该环氧树脂包括从氧化硅(SiO2)、氧化铝(Al2O3)、氮化硅(Si3N4)、氮化铝(AlN)和氮化硼(BN)组成的组中选择的一种或多种填充物，并具有0.5-5.0W/m·k的热传导率。 
环氧树脂从注射起几十秒内固化。在环氧树脂固化后立即将该结构从模具中取出，并且，环氧树脂然后在恒温室中接受后固化。从而形成绝缘树脂模。 
如此半导体器件20被完成以使得金属衬底2从绝缘衬底1暴露于外界， 并且绝缘衬底1的绝缘层3和电路图案4以及功率器件23被绝缘树脂模22封入和与外界隔开。 
根据该实施例的每一半导体器件10和20作为电源电路模块已经在上面作了描述，本发明可应用于不仅设有电源电路模块而且设有控制电路模块的半导体器件。 
由于通过具有出众的绝缘性能、抗湿性和阻止腐蚀气体功能的环氧树脂等等，内部的电路被封入且与外界隔开，根据本发明的半导体器件10和20防止了因灰尘引入或吸湿导致的绝缘性能的变差，同时也防止了因暴露于诸如氢化硫的腐蚀气体导致的电子元件的电极腐蚀。 
能够降低因功率器件14或23错误的电气操作或短路产生电弧或火化的可能性，这避免了整个设备被烧引起火灾。 
除上述优点外，本发明同时提供了高可靠性的半导体器件。 

Claims (7)

1.一种绝缘衬底，包括：
作为基底构件的金属基底；
绝缘层，其为形成在所述金属基底上的室温冲击固化膜；以及
电路图案，其为形成在所述绝缘层上的热喷涂涂层，其中，所述电路图案是用冷喷涂方法形成的热喷涂涂层，所述绝缘层是用气溶胶淀积法形成的室温冲击固化膜。
2.如权利要求1所述的绝缘衬底，其特征在于：所述绝缘层是通过使陶瓷微粒与金属基底碰撞而连接到金属基底的室温冲击固化膜的陶瓷层，所述陶瓷微粒由氧化硅、氧化铝、氮化硅、氮化硼和氮化铝中的至少一种制成。
3.如权利要求2所述的绝缘衬底，其特征在于：所述绝缘层由氧化硅和氧化铝组成的第一组中的至少一种及由氮化硅、氮化硼、氮化铝组成的第二材料组中的至少一种制成。
4.如权利要求1所述的绝缘衬底，其特征在于：所述绝缘层是通过使陶瓷微粒与金属基底碰撞而连接到金属基底的室温冲击固化膜的陶瓷层，所述陶瓷微粒由表面形成有氧化铝涂层的氮化硅、表面形成有氧化铝涂层的氮化硼和表面形成有氧化铝涂层的氮化铝中的至少一种制成。
5.如权利要求1所述的绝缘衬底，其特征在于：所述绝缘层是通过使陶瓷微粒与金属基底碰撞连接到金属基底的室温冲击固化膜的陶瓷层，所述陶瓷微粒由表面形成有氧化硅涂层的氮化硅、表面形成有氧化硅涂层的氮化硼和表面形成有氧化硅涂层的氮化铝中的至少一种制成。
6.一种半导体器件，包括：
如权利要求1-5中任一权项所述的绝缘衬底；
粘结到所述绝缘衬底的金属基底的树脂外壳；
安装在所述绝缘衬底的电路图案上并放置在所述树脂外壳中的功率器件；以及
绝缘树脂，充满在所述树脂外壳中，从而使所述绝缘衬底的所述绝缘层和所述电路图案以及所述功率器件被封入并与外界隔开。
7.一种半导体器件，包括：
如权利要求1-5中任一权项所述的绝缘衬底；
安装在所述绝缘衬底的电路图案上的功率器件；以及
热固性绝缘树脂，其形成使得所述绝缘衬底的金属基底的一部分向外界暴露，并使所述绝缘衬底的所述绝缘层和所述电路图案以及所述功率器件被封入且与外界隔开。
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Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196853A (ja) * 2004-12-13 2006-07-27 Daikin Ind Ltd ヒートポンプ装置
CN100449740C (zh) * 2006-06-19 2009-01-07 上海集成电路研发中心有限公司 降低半导体器件发热的散热方法、相应器件及其制造方法
JP4760585B2 (ja) * 2006-07-18 2011-08-31 三菱電機株式会社 電力用半導体装置
JP2008091764A (ja) * 2006-10-04 2008-04-17 Toyota Motor Corp 電子部品及びフィルムコンデンサー
JP5077529B2 (ja) * 2006-11-10 2012-11-21 富士電機株式会社 絶縁基板の製造方法、ならびに半導体装置の製造方法
JP2008130767A (ja) * 2006-11-20 2008-06-05 Canon Inc 振動体の製造方法、振動体および振動型駆動装置
JP4910903B2 (ja) * 2007-06-22 2012-04-04 トヨタ自動車株式会社 伝熱部材の製造方法、パワーモジュール、車両用インバータ、及び車両
JP4241859B2 (ja) 2007-07-19 2009-03-18 トヨタ自動車株式会社 パワーモジュールの製造方法、パワーモジュール、車両用インバータ、及び車両
WO2009020804A1 (en) * 2007-08-06 2009-02-12 Olzak James M Method of depositing electrically conductive material onto a substrate
JP2010229426A (ja) * 2007-08-07 2010-10-14 Showa Denko Kk 熱交換器用部材の製造方法および熱交換器用部材
JP2009108369A (ja) * 2007-10-30 2009-05-21 Fujifilm Corp セラミック製造方法およびセラミック製造装置
JP5110441B2 (ja) * 2008-01-15 2012-12-26 大日本印刷株式会社 半導体装置用配線部材、半導体装置用複合配線部材、および樹脂封止型半導体装置
KR20090103600A (ko) * 2008-03-28 2009-10-01 페어차일드코리아반도체 주식회사 전력 소자용 기판 및 이를 포함하는 전력 소자 패키지
DE102008019682A1 (de) * 2008-04-11 2009-10-15 Siemens Aktiengesellschaft Kaltgasspritzanlage
KR100981112B1 (ko) 2008-10-16 2010-09-08 주식회사 포스코 비정질 전기강판의 제조장치 및 제조방법
DE102008056652A1 (de) 2008-11-10 2010-05-12 Mtu Aero Engines Gmbh Maske für das kinetische Kaltgaskompaktieren
TWI501371B (zh) * 2009-01-13 2015-09-21 Dainippon Printing Co Ltd A wiring member for a semiconductor device, a composite wiring member for a semiconductor device, and a resin-sealed type semiconductor device
JP5526632B2 (ja) * 2009-07-14 2014-06-18 三菱マテリアル株式会社 絶縁基板、絶縁回路基板、半導体装置、絶縁基板の製造方法及び絶縁回路基板の製造方法
JP5359644B2 (ja) * 2009-07-23 2013-12-04 三菱マテリアル株式会社 パワーモジュール用基板、パワーモジュール及びパワーモジュール用基板の製造方法
US8461462B2 (en) * 2009-09-28 2013-06-11 Kyocera Corporation Circuit substrate, laminated board and laminated sheet
US20110086178A1 (en) * 2009-10-14 2011-04-14 General Electric Company Ceramic coatings and methods of making the same
EP2315242A1 (en) * 2009-10-23 2011-04-27 ABB Technology AG Circuit arrangement and manufacturing method thereof
US8076696B2 (en) * 2009-10-30 2011-12-13 General Electric Company Power module assembly with reduced inductance
JP5486608B2 (ja) * 2009-11-13 2014-05-07 株式会社日立製作所 絶縁性構造及びその製造方法
TW201119742A (en) * 2009-12-14 2011-06-16 Yi-Chun Liu Composition having catalyst particles
JP5565147B2 (ja) 2010-06-30 2014-08-06 株式会社デンソー 半導体モジュールの製造方法
KR101380836B1 (ko) * 2011-01-18 2014-04-09 한국기계연구원 상온진공과립분사 공정을 위한 취성재료 과립 및 이를 이용한 코팅층의 형성방법
JP5633496B2 (ja) * 2011-09-29 2014-12-03 三菱電機株式会社 半導体装置及びその製造方法
DE112012004593B4 (de) * 2011-11-02 2020-10-01 Fuji Electric Co., Ltd. Leistungswandler
DE102012101889A1 (de) 2012-03-06 2013-09-12 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip
DE102012107797A1 (de) * 2012-08-23 2014-02-27 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Licht emittierenden Halbleiterbauelements und Licht emittierendes Halbleiterbauelement
JP5926654B2 (ja) * 2012-08-29 2016-05-25 日立オートモティブシステムズ株式会社 パワー半導体モジュールおよびパワー半導体モジュールの製造方法
CN104620372B (zh) * 2012-12-28 2017-10-24 富士电机株式会社 半导体装置
JP2015002306A (ja) * 2013-06-18 2015-01-05 富士電機株式会社 絶縁基板およびその製造方法
US20150001700A1 (en) * 2013-06-28 2015-01-01 Infineon Technologies Ag Power Modules with Parylene Coating
WO2015025347A1 (ja) * 2013-08-19 2015-02-26 株式会社日立製作所 電子回路基板、それを用いた半導体装置及びその製造方法
US9806244B2 (en) * 2014-01-10 2017-10-31 Sharp Kabushiki Kaisha Substrate for light emitting device, light emitting device, and manufacturing method of substrate for light emitting device
DE112015000141B4 (de) * 2014-03-31 2021-11-11 Fuji Electric Co., Ltd. Stromrichtvorrichtung
JP6203942B2 (ja) * 2014-04-04 2017-09-27 シャープ株式会社 発光装置用基板の製造方法、発光装置の製造方法、及び照明装置の製造方法
DE102014105000B4 (de) * 2014-04-08 2021-02-25 Infineon Technologies Ag Verfahren zur Herstellung und zum Bestücken eines Schaltungsträgers
WO2015162035A1 (en) * 2014-04-24 2015-10-29 Basf Se Gas phase process for producing conductive metal oxide films
CN105280567B (zh) 2014-06-19 2018-12-28 株式会社吉帝伟士 半导体封装件及其制造方法
JP6466252B2 (ja) * 2014-06-19 2019-02-06 株式会社ジェイデバイス 半導体パッケージ及びその製造方法
DE102014214784A1 (de) * 2014-07-28 2016-02-11 Continental Automotive Gmbh Schaltungsträger, elektronische Baugruppe, Verfahren zum Herstellen eines Schaltungsträgers
JP6451257B2 (ja) * 2014-11-21 2019-01-16 富士電機株式会社 半導体装置
US10014237B2 (en) * 2014-12-16 2018-07-03 Kyocera Corporation Circuit board having a heat dissipating sheet with varying metal grain size
DE102015201927A1 (de) * 2015-02-04 2016-08-04 Siemens Aktiengesellschaft Verfahren zum Kaltgasspritzen mit Maske
CN105469130B (zh) * 2015-04-14 2018-12-04 赵宏峰 油田井下金属制品增加永久性可自动识别标识的方法
JP6699111B2 (ja) 2015-08-18 2020-05-27 富士電機株式会社 半導体装置及び半導体装置の製造方法
EP3425087A4 (en) * 2016-03-01 2019-11-06 Nippon Steel Corporation CERAMIC LAMINATE
US9532448B1 (en) * 2016-03-03 2016-12-27 Ford Global Technologies, Llc Power electronics modules
US10336579B2 (en) 2016-03-29 2019-07-02 Otis Elevator Company Metal coating of load bearing member for elevator system
DE102016209003B4 (de) * 2016-05-24 2021-04-22 Vitesco Technologies GmbH Vorrichtung zum Kühlen mindestens eines (Halbleiter)-Schalters und mindestens eines Widerstands, sowie Herstellungsverfahren
JP2018012852A (ja) * 2016-07-19 2018-01-25 株式会社東芝 凝集体およびその製造方法、ならびにこの凝集体を用いた被膜の形成方法
JP6642719B2 (ja) * 2016-08-10 2020-02-12 三菱電機株式会社 半導体装置
DE102016219309B4 (de) * 2016-10-05 2024-05-02 Vitesco Technologies GmbH Vibrationsfeste Schaltungsanordnung zum elektrischen Verbinden zweier Anschlussbereiche sowie Kraftfahrzeug und Verfahren zum Herstellen der Schaltungsanordnung
US10177057B2 (en) 2016-12-15 2019-01-08 Infineon Technologies Ag Power semiconductor modules with protective coating
US11570901B2 (en) * 2017-02-24 2023-01-31 National Institute For Materials Science Method for manufacturing aluminum circuit board
JP2018170362A (ja) * 2017-03-29 2018-11-01 株式会社東芝 半導体モジュール
JP2018182119A (ja) * 2017-04-17 2018-11-15 三菱電機株式会社 半導体装置
DE102018101750A1 (de) * 2018-01-26 2019-08-01 Rogers Germany Gmbh Verbundkeramik für eine Leiterplatte und Verfahren zu deren Herstellung
CN111742404A (zh) * 2018-02-20 2020-10-02 株式会社村田制作所 半导体装置以及半导体装置的制造方法
US11081422B2 (en) * 2019-03-14 2021-08-03 Toyota Motor Engineering & Manufacturing North America, Inc. Self-healing PDMS encapsulation and repair of power modules
JP7265137B2 (ja) * 2019-04-25 2023-04-26 日本製鉄株式会社 セラミックス積層体の製造方法およびそれによって製造されたセラミックス積層体
JP7341756B2 (ja) * 2019-07-05 2023-09-11 日本特殊陶業株式会社 デバイス搭載用基板
CN111739845B (zh) * 2020-08-24 2021-06-08 江苏宏微科技股份有限公司 内绝缘封装结构及其工艺方法
CN112746242A (zh) * 2020-12-29 2021-05-04 佛山桃园先进制造研究院 一种提升电能利用效率和温度控制的电加热涂层及其制备方法
JP2023121432A (ja) * 2022-02-21 2023-08-31 サンデン株式会社 電動圧縮機

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276423A (en) * 1991-11-12 1994-01-04 Texas Instruments Incorporated Circuit units, substrates therefor and method of making
US5354415A (en) * 1990-04-16 1994-10-11 Denki Kagaku Kogyo Kabushiki Kaisha Method for forming a ceramic circuit board
CN1106164A (zh) * 1993-11-18 1995-08-02 三星电子株式会社 半导体器件及其制造方法
CN1122052A (zh) * 1994-07-05 1996-05-08 国际商业机器公司 半导体封装及制造方法
US6222166B1 (en) * 1999-08-09 2001-04-24 Watlow Electric Manufacturing Co. Aluminum substrate thick film heater
US6428858B1 (en) * 2001-01-25 2002-08-06 Jimmie Brooks Bolton Wire for thermal spraying system

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2848068B2 (ja) * 1991-12-10 1999-01-20 富士電機株式会社 半導体装置
US6331680B1 (en) 1996-08-07 2001-12-18 Visteon Global Technologies, Inc. Multilayer electrical interconnection device and method of making same
JP3554735B2 (ja) 2000-10-23 2004-08-18 独立行政法人産業技術総合研究所 複合構造物およびその作製方法並びに作製装置
TW511405B (en) * 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
JP2002203942A (ja) * 2000-12-28 2002-07-19 Fuji Electric Co Ltd パワー半導体モジュール
JP3784341B2 (ja) * 2001-04-03 2006-06-07 独立行政法人産業技術総合研究所 回路基板とその作製方法
JP3937952B2 (ja) 2002-07-15 2007-06-27 東陶機器株式会社 放熱回路基板とその作製方法
AU2003301935A1 (en) 2002-08-05 2004-06-03 Research Foundation Of The State University Of New York System and method for manufacturing wireless devices
JP4239526B2 (ja) 2002-08-30 2009-03-18 Ｔｏｔｏ株式会社 コンデンサ、複合回路基板及びコンデンサの製造方法
JP3929978B2 (ja) * 2003-01-15 2007-06-13 ユナイテッド テクノロジーズ コーポレイション アルミニウム基合金
JP3960230B2 (ja) * 2003-01-24 2007-08-15 富士電機ホールディングス株式会社 半導体モジュールおよびその製造方法並びにスイッチング電源装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5354415A (en) * 1990-04-16 1994-10-11 Denki Kagaku Kogyo Kabushiki Kaisha Method for forming a ceramic circuit board
US5276423A (en) * 1991-11-12 1994-01-04 Texas Instruments Incorporated Circuit units, substrates therefor and method of making
CN1106164A (zh) * 1993-11-18 1995-08-02 三星电子株式会社 半导体器件及其制造方法
CN1122052A (zh) * 1994-07-05 1996-05-08 国际商业机器公司 半导体封装及制造方法
US6222166B1 (en) * 1999-08-09 2001-04-24 Watlow Electric Manufacturing Co. Aluminum substrate thick film heater
US6428858B1 (en) * 2001-01-25 2002-08-06 Jimmie Brooks Bolton Wire for thermal spraying system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
US 5276423 A,全文.

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