JP6699111B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- JP6699111B2 JP6699111B2 JP2015161392A JP2015161392A JP6699111B2 JP 6699111 B2 JP6699111 B2 JP 6699111B2 JP 2015161392 A JP2015161392 A JP 2015161392A JP 2015161392 A JP2015161392 A JP 2015161392A JP 6699111 B2 JP6699111 B2 JP 6699111B2
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Description
前記金属板上に配置され、上面および下面に金属電極を備え、前記下面の金属電極が他方の前記第1貫通孔を塞ぐ位置に配置された第2半導体素子をさらに備え、第5金属層は、前記金属板、前記第1半導体素子下面の前記金属電極および前記第2半導体素子下面の前記金属電極とそれぞれ直接接続されていてもよい。
本発明に係る実施の形態1について説明する。図1、図2、図3、図5および図6は、本発明の実施の形態1に係る半導体装置の製造方法を説明する断面図である。図4は、本発明の実施の形態1に係る半導体装置の金属板の下面図である。本発明の実施の形態1に係る半導体装置20は、一方の主面に第1金属層2および第10金属層23を有する絶縁回路基板40と、第1金属層2と導電接続した金属板5と、表面に複数の金属電極7cを備えた第1半導体素子7と、第1半導体素子7の側面に配置された第1絶縁部材8と、第1絶縁部材8上および第1半導体素子7上に配置された第2絶縁部材9と、少なくとも一部が第2絶縁部材9上に配置され、かつ第1半導体素子7の金属電極7cと絶縁回路基板40上の第10金属層23とを導電接続する第6金属層11aと、を備えている(図6の(y1)参照)。さらに、半導体装置20は、金属板5が第1貫通孔5aを有し、第1半導体素子7の金属電極7cの少なくとも1つが第1貫通孔5aを塞ぐ位置に配置され、第1半導体素子7と第1金属層2とを導電接続する第5金属層6が第1貫通孔5a内に配置されている。
図1の(a)に示すように、一方の面にプロトンが注入された単結晶炭化珪素ウェハ31と、表面にボイドを形成された多結晶炭化珪素ウェハ32とを準備する。ボイドを形成方法は、特許5725430号公報の0053段落から0054段落に記載されている。例えば、多結晶炭化珪素ウェハ32の表面にプラズマを全面的または部分的に照射することでボイドを形成できる。プロトン注入領域31aでは、プロトン濃度は、1×1016ions/cm2以上5×1017ions/cm2以下であることが望ましい。
次に、図2の(g)に示すように、エピタキシャル成長された単結晶炭化珪素膜33表面に半導体素子の上部構造7aを形成する。
次に、図2の(h)に示すように、単結晶炭化珪素膜33の半導体素子の上部構造7aを形成された面に粘着剤34aを介してサポート材34を固定する。
次に、図2の(i)に示すように、単結晶炭化珪素膜33と多結晶炭化珪素ウェハ32との界面外周にレーザー光を照射し、ウェハの外周の一部を起点にして、単結晶炭化珪素膜33と多結晶炭化珪素ウェハ32とをこの界面で剥離させる。レーザー光は、ウェハの側面方向または垂直方向からウェハへ照射される。詳細な方法は、特許5725430号公報の0046段落から0051段落に記載されている。
次に、図2の(k)に示すように、単結晶炭化珪素膜33の裏面に半導体素子の下部構造7bを形成する。半導体素子の上部構造7aと、半導体素子の下部構造7bは、製造する半導体素子の種類に応じて適宜変更する。例えば、半導体素子7を絶縁ゲートバイポーラトランジスタ(IGBT:Insulated Gate Bipolar Transistor)にし、半導体素子16をショットキーバリアダイオード(SBD:Schottky Barrier Diode)にできる。そして、半導体素子の下部構造7bの表面にダイシングテープ35を貼る。
次に、図5の(t1)に示すように、第1金属層2の上面と、第10金属層23の上面と、第11金属層25の上面とを砥石38cで研磨する。
図5の(u1)は、研磨工程後の絶縁回路基板40の構造を示している。第1金属層2の上面と、第10金属層23の上面と、第11金属層25の上面とが、面一になっている。
本発明に係る実施の形態2について説明する。図7および図8は、本発明の実施の形態2に係る半導体装置の製造方法を説明する断面図である。
本発明に係る実施の形態3について説明する。図9は、半導体装置22の一部の回路図である。図10は、半導体装置22の製造方法を説明する断面図である。
実施の形態2である図8の(x2)に続いて、第3絶縁部材17が、第6金属層11a上および第2絶縁部材9上に配置される。
2 第1金属層
2a 第1金属層
3 第2金属層
3a 第3金属層
5 金属板
5a 第1貫通孔
5b 第2貫通孔
6 第5金属層
7 第1半導体素子
7a 半導体素子の上部構造
7b 半導体素子の下部構造
7c 金属電極
8 第1絶縁部材
9 第2絶縁部材
11a 第6金属層
11b 第7金属層
12a 金属端子
12b 金属端子
13 端子接続用金属板
14 絶縁樹脂
15 半導体素子複合体
16 第2半導体素子
16c 金属電極
17 第3絶縁部材
18a 第8金属層
18b 第9金属層
19 第4絶縁部材
20 半導体装置
21 半導体装置
22 半導体装置
23 第10金属層
23a 第10金属層
24 第3半導体素子
24c 金属電極
25 第11金属層
25a 第11金属層
26 端子接続用金属板
31 単結晶炭化珪素ウェハ
31a プロトン注入領域
32 多結晶炭化珪素ウェハ
33 単結晶炭化珪素膜
34 サポート材
34a 粘着剤
35 ダイシングテープ
36 ダイシングトレイ
37 加熱炉
38a 砥石
38b 砥石
38c 砥石
39 保護テープ
40 絶縁回路基板
41 絶縁回路基板
Claims (4)
- 上面および下面に金属電極が形成された第1半導体素子を準備する半導体素子準備工程と、
前記第1半導体素子下面の前記金属電極を金属板の第1貫通孔を塞ぐように配置する工程と、
前記金属板の前記第1半導体素子側の面とは反対側の面の前記第1貫通孔から前記第1半導体素子下面の前記金属電極へ金属を溶射して前記第1貫通孔内に第5金属層を形成し、該第5金属層が前記第1半導体素子下面の金属電極および前記金属板と接続する溶射工程と、
溶射された前記金属の面を研磨する研磨工程と、
絶縁回路基板上に形成された第10金属層の上側の一部と、前記第1半導体素子上面の前記金属電極が形成されている表面のうち該金属電極が形成されている部分を除いた面とを該金属電極の外縁上を覆うように第2絶縁部材で覆う工程と、
前記第2絶縁部材上を延伸して、前記第1半導体素子上面の前記金属電極と、前記第10金属層とを導電接続する第6金属層を形成する工程と、
を順に備えることを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第6金属層は、金属を溶射して形成されることを特徴とする半導体装置の製造方法。 - 請求項1または2に記載の半導体装置の製造方法において、
前記研磨工程より前に、
前記金属板上の前記第1半導体素子が配置されない位置に前記金属板および前記第1半導体素子を固定する第1絶縁部材を配置する工程と、
前記第1半導体素子および前記第1絶縁部材の前記金属板に面する側の反対面を保護テープで覆う工程と、
を順に備えることを特徴とする半導体装置の製造方法。 - 請求項1から3のいずれか一項に記載の半導体装置の製造方法において、
前記研磨された前記金属の面と、前記絶縁回路基板上の第1金属層とを直接接合する工程を備えることを特徴とする半導体装置の製造方法。
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JP6809294B2 (ja) * | 2017-03-02 | 2021-01-06 | 三菱電機株式会社 | パワーモジュール |
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