JP7309396B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7309396B2 JP7309396B2 JP2019050530A JP2019050530A JP7309396B2 JP 7309396 B2 JP7309396 B2 JP 7309396B2 JP 2019050530 A JP2019050530 A JP 2019050530A JP 2019050530 A JP2019050530 A JP 2019050530A JP 7309396 B2 JP7309396 B2 JP 7309396B2
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Description
実施形態の半導体装置は、主基板と、主基板上に設けられた第1基板と、第1基板上に設けられた第1半導体素子及び第2半導体素子と、第1基板上に設けられた第1正端子、第1負端子、第1出力端子と、主基板上に設けられた第2基板と、第2基板上に設けられた第3半導体素子及び第4半導体素子と、第2基板上に設けられた第2正端子、第2負端子、第2出力端子と、第1正端子及び第2正端子を接続する第1端子板と、第1負端子及び第2負端子を接続する第2端子板と、第1出力端子及び第2出力端子を接続する第3端子板と、のうち、少なくとも1つの端子板と、を備える。
4a 第1基板
4b 第2基板
4c 第3基板
4d 第4基板
6a 第1電極部材
6b 第4電極部材
6c 第7電極部材
6d 第10電極部材
8a 第1平面部
8b 第4平面部
8c 第7平面部
8d 第10平面部
10a 第2電極部材
10b 第5電極部材
10c 第8電極部材
10d 第11電極部材
12a 第2平面部
12b 第5平面部
12c 第8平面部
12d 第11平面部
14a 第3電極部材
14b 第6電極部材
14c 第9電極部材
14d 第12電極部材
16a 第3平面部
16b 第6平面部
16c 第9平面部
16d 第12平面部
18a 第1配線
18b 第2配線
20a~c 第1半導体素子
21a 第1電極
21b 第2電極
22a~c 第2半導体素子
23a 第3電極
23b 第4電極
24a~c 第3半導体素子
25a 第5電極
25b 第6電極
26a~c 第4半導体素子
27a 第7電極
27b 第8電極
28a~c 第5半導体素子
29a 第9電極
29b 第10電極
30a~c 第6半導体素子
31a 第11電極
31b 第12電極
32a~c 第7半導体素子
33a 第13電極
33b 第14電極
34a~c 第8半導体素子
35a 第15電極
35b 第16電極
40 第1端子板
42 板部
44a 板部
44b 板部
44c 板部
44d 板部
46 穴
50 第2端子板
52 第1板部
54a 第1配線部
54b 第2配線部
54c 第3配線部
54d 第4配線部
60 第3端子板
62 第2板部
64a 第5配線部
64b 第6配線部
64c 第7配線部
64d 第8配線部
80a~l 配線(第5配線、第6配線)
100 半導体装置
200 電力変換装置
210 直流電源
212 正極
214 負極
220 平滑キャパシタ
222a~c ハイサイドトランジスタ
224a~c ローサイドトランジスタ
Claims (4)
- 電気伝導性を有する主基板と、
前記主基板上に設けられ、絶縁性のセラミックスで形成された第1基板と、
前記第1基板上に設けられた第1半導体素子及び第2半導体素子と、
前記第1基板上に設けられた第1正端子、第1負端子、第1出力端子と、
前記主基板上に設けられ、絶縁性のセラミックスで形成された第2基板と、
前記第2基板上に設けられた第3半導体素子及び第4半導体素子と、
前記第2基板上に設けられた第2正端子、第2負端子、第2出力端子と、
前記主基板上に設けられ、絶縁性のセラミックスで形成された第3基板と、
前記第3基板上に設けられた第5半導体素子及び第6半導体素子と、
前記第3基板上に設けられた第3正端子、第3負端子、第3出力端子と、
前記主基板上に設けられ、絶縁性のセラミックスで形成された第4基板と、
前記第4基板上に設けられた第7半導体素子及び第8半導体素子と、
前記第4基板上に設けられた第4正端子、第4負端子、第4出力端子と、
前記第1正端子、前記第2正端子、前記第3正端子及び前記第4正端子を接続する第1端子板と、
前記第1負端子、前記第2負端子、前記第3負端子及び前記第4負端子を接続する第2端子板と、
前記第1出力端子、前記第2出力端子、前記第3出力端子及び前記第4出力端子を接続する第3端子板と、
を備え、
前記第1基板上の前記第1正端子、前記第1負端子、及び前記第1出力端子と前記第2基板上の前記第2正端子、前記第2負端子、及び前記第2出力端子は、それぞれ前記第1基板と前記第2基板の間における、前記主基板に垂直な第1平面に対して面対称であり、
前記第3基板上の前記第3正端子、前記第3負端子、及び前記第3出力端子と前記第4基板上の前記第4正端子、前記第4負端子、及び前記第4出力端子は、それぞれ前記第3基板と前記第4基板の間における、前記主基板に垂直な第2平面に対して面対称であり、
前記第1基板上の前記第1正端子、前記第1負端子、及び前記第1出力端子と前記第3基板上の前記第3正端子、前記第3負端子、及び前記第3出力端子は、それぞれ前記第1基板と前記第3基板の間における、前記主基板に垂直な第3平面に対して面対称であり、
前記第2基板上の前記第2正端子、前記第2負端子、及び前記第2出力端子と前記第4基板上の前記第4正端子、前記第4負端子、及び前記第4出力端子は、それぞれ前記第2基板と前記第4基板の間における、前記主基板に垂直な第4平面に対して面対称である、
半導体装置。 - 前記第2端子板は、
第1板部と、
一端が前記第1板部に接続され、他端が前記第1負端子に接続された第1配線部と、
一端が前記第1板部に接続され、他端が前記第2負端子に接続された第2配線部と、
一端が前記第1板部に接続され、他端が前記第3負端子に接続された第3配線部と、
一端が前記第1板部に接続され、他端が前記第4負端子に接続された第4配線部と、
を有する請求項1に記載の半導体装置。 - 前記第3端子板は、
第2板部と、
一端が前記第2板部に接続され、他端が前記第1出力端子に接続された第5配線部と、
一端が前記第2板部に接続され、他端が前記第2出力端子に接続された第6配線部と、
一端が前記第2板部に接続され、他端が前記第3出力端子に接続された第7配線部と、
一端が前記第2板部に接続され、他端が前記第4出力端子に接続された第8配線部と、
を有する請求項1又は請求項2に記載の半導体装置。 - 前記第1半導体素子と前記第2半導体素子は電気的に直列に接続され、
前記第3半導体素子と前記第4半導体素子は電気的に直列に接続され、
前記第5半導体素子と前記第6半導体素子は電気的に直列に接続され、
前記第7半導体素子と前記第8半導体素子は電気的に直列に接続されている、
請求項1乃至請求項3いずれか一項に記載の半導体装置。
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