CN105280567B - 半导体封装件及其制造方法 - Google Patents
半导体封装件及其制造方法 Download PDFInfo
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- CN105280567B CN105280567B CN201510320188.2A CN201510320188A CN105280567B CN 105280567 B CN105280567 B CN 105280567B CN 201510320188 A CN201510320188 A CN 201510320188A CN 105280567 B CN105280567 B CN 105280567B
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Abstract
本发明提供一种减少在支撑基板与粘接材料之间产生的内部应力且可靠性高的半导体封装件。本发明的半导体封装件的特征在于,包括:支撑基板;应力缓和层,设置于上述支撑基板的主面;半导体器件,配置在上述应力缓和层之上;密封体,由与上述应力缓和层不同的绝缘材料形成,用于覆盖上述半导体器件;布线,贯通上述密封体而与上述半导体器件电连接;以及外部端子,与上述布线电连接。此时,当在相同温度条件下,设上述支撑基板的弹性模量为A,设上述应力缓和层的弹性模量为B,并设上述密封体的弹性模量为C时,A>C>B或C>A>B的关系成立。
Description
技术领域
本发明涉及半导体封装件的安装技术。尤其涉及用于缓和半导体封装件的制造工序中产生的应力的技术。
背景技术
以往,已知有在支撑基板上搭载集成电路(IC)芯片等半导体器件的半导体封装件结构。通常,这种半导体封装件采用在支撑基板上经由被称为管芯连接(die attach)材料的粘接材料粘接IC芯片等半导体器件,并由密封体(密封用树脂)覆盖上述半导体器件而进行保护的结构。
作为用于半导体封装件的支撑基板,使用了印刷电路板、陶瓷基板等多种基板。尤其,近年来,正在开发利用金属基板的半导体封装件。利用金属基板的半导体封装件具有电磁屏蔽性、热特性优异的优点,作为可靠性高的半导体封装件而备受瞩目。
但是,被指出了如下问题:由于金属和树脂在热膨胀系数(CTE,coefficient ofthermal expansion)上存在较大的差异,因而在利用金属基板的半导体封装件的制造工序中,金属基板和密封体(用于保护半导体器件的树脂)之间因热膨胀系数的差异而产生内部应力,密封体会发生翘曲(专利文献1)。
(现有技术文献)
(专利文献)
专利文献1:日本特开2010-40911号公报
发明内容
本发明鉴于上述问题而提出,其课题在于提供一种减少支撑基板与密封体之间产生的内部应力且可靠性高的半导体封装件。
本发明一个实施方式的半导体封装件的特征在于,包括:支撑基板;应力缓和层,其设置于上述支撑基板的主面;半导体器件,其配置在上述应力缓和层之上;密封体,其由与上述应力缓和层不同的绝缘材料形成,用于覆盖上述半导体器件;布线,其贯通上述密封体而与上述半导体器件电连接;以及外部端子,其与上述布线电连接。
本发明一个实施方式的半导体封装件的特征在于,包括:支撑基板;应力缓和层,其设置于上述支撑基板的主面;导电层,其设置在上述应力缓和层之上;半导体器件,其配置在上述导电层之上;密封体,其由与上述应力缓和层不同的绝缘材料形成,用于覆盖上述半导体器件;布线,其贯通上述密封体而与上述半导体器件电连接;以及外部端子,其与上述布线电连接。
本发明一个实施方式的半导体封装件的特征在于,包括:支撑基板;应力缓和层,其设置于上述支撑基板的主面;导电层,其设置在上述应力缓和层之上;半导体器件,其被上述导电层包围,并且配置在上述应力缓和层之上;密封体,其由与上述应力缓和层不同的绝缘材料形成,用于覆盖上述半导体器件;布线,其贯通上述密封体而与上述半导体器件电连接;以及外部端子,其与上述布线电连接。
另外,本发明一个实施方式的半导体封装件的制造方法的特征在于,包括:在支撑基板的主面形成应力缓和层的工序;在上述应力缓和层之上配置至少一个半导体器件的工序;利用由与上述应力缓和层不同的材料形成的密封体来覆盖上述半导体器件的工序;形成贯通上述密封体而与上述半导体器件电连接的布线的工序;以及形成与上述布线电连接的外部端子的工序。
本发明一个实施方式的半导体封装件的制造方法的特征在于,包括:在支撑基板的主面形成应力缓和层的工序;在上述应力缓和层之上形成导电层的工序;在上述导电层上配置至少一个半导体器件的工序;利用由与上述应力缓和层不同的材料形成的密封体来覆盖上述半导体器件的工序;形成贯通上述密封体而与上述半导体器件电连接的布线的工序;以及形成与上述布线电连接的外部端子的工序。
本发明一个实施方式的半导体封装件的制造方法的特征在于,包括:在支撑基板的主面形成应力缓和层的工序;在上述应力缓和层之上形成导电层的工序;对上述导电层进行刻蚀而使上述应力缓和层露出的工序;在使上述应力缓和层露出的区域配置至少一个半导体器件的工序;利用由与上述应力缓和层不同的材料形成的密封体来覆盖上述半导体器件的工序;形成贯通上述密封体而与上述半导体器件电连接的布线的工序;以及形成与上述布线电连接的外部端子的工序。
根据本发明,可实现减少支撑基板与密封体之间产生的内部应力且可靠性高的半导体封装件。
附图说明
图1为本发明第一实施方式的半导体封装件的外观图。
图2为本发明第一实施方式的半导体封装件的剖面图。
图3为示出本发明第一实施方式的半导体封装件的制造工序的图。
图4为示出本发明第一实施方式的半导体封装件的制造工序的图。
图5为示出本发明第一实施方式的半导体封装件的制造工序的图。
图6为示出本发明第一实施方式的半导体封装件的制造工序的图。
图7为本发明第二实施方式的半导体封装件的剖面图。
图8为本发明第二实施方式的半导体封装件的俯视图。
图9为本发明第三实施方式的半导体封装件的剖面图。
图10为本发明第三实施方式的半导体封装件的俯视图。
图11为本发明第四实施方式的半导体封装件的剖面图。
图12为本发明第四实施方式的半导体封装件的俯视图。
图13为本发明第五实施方式的半导体封装件的剖面图。
图14为本发明第六实施方式的半导体封装件的俯视图。
图15为本发明第六实施方式中形成一边的尺寸为400μm的开口部的情况下的可靠性评价结果。
图16为本发明的第六实施方式中形成一边的尺寸为500μm的开口部的情况下的可靠性评价结果。
图17为本发明的第六实施方式中形成一边的尺寸为600μm的开口部的情况下的可靠性评价结果。
图18为本发明的第六实施方式中形成一边的尺寸为400μm的开口部的情况的可靠性评价结果。
(附图标记的说明)
100:半导体封装件;101:支撑基板;102:应力缓和层;103:粘接材料;
104:半导体器件;105:第一密封体;106:第一布线层;107:第二密封体;
108:第二布线层;109:第三密封体;110:外部端子;111:平坦化层
具体实施方式
以下,参照附图详细说明本发明一个实施方式的半导体封装件。以下所示的实施方式为本发明实施方式的一例,本发明并不局限于这些实施方式。
此外,在本实施方式中所参照的图中,对于同一部分或具有相同的功能的部分标注同一附图标记或类似的附图标记(仅在数字后面标注A、B等的附图标记),并省略其重复说明。另外,为了便于说明,图的尺寸比例与实际比例或有所不同,或者从图中省略结构的一部分。
另外,在本说明书中的剖面图中,“上”是指以支撑基板的主面(配置半导体器件的面)为基准的相对位置,远离支撑基板的主面的方向为“上”。图2之后,朝向纸面时,上方为“上”。另外,“上”包括与物体的上表面接触的情况(即,在……上面(on)的情况)和位于物体的上方的情况(即,在……上方(over)的情况)。
(第一实施方式)
<封装件的外观>
图1为本发明第一实施方式的半导体封装件100的外观图。此外,图1的近前部分为了示出内部结构的外观而图示了切割面。
在图1中,11为支撑基板,12为设置于支撑基板的主面的应力缓和层。13为IC芯片或大规模集成电路(LSI)芯片等半导体器件,14及15为保护半导体器件的密封体(密封用树脂)。在这里虽未图示,但密封体14、15内形成有布线,用于将半导体器件的输出端子与作为外部端子的焊料球16电连接。
这样,本实施方式的半导体封装件100的构造为:将支撑基板11直接用作基体,并利用层叠的树脂层(密封体14、15)将半导体器件13与外部空气隔离而加以保护。
<封装件结构>
图2为用于详细说明利用图1来说明的半导体封装件100的结构的剖面图。101为支撑基板,在这里,利用金属基板。作为金属基板,可使用不锈钢等铁合金基板或铜合金基板等金属基板。当然,无需限定为金属基板,也可以根据用途或成本,而使用硅基板、玻璃基板、陶瓷基板、有机基板等。
在支撑基板101上设有应力缓和层102。应力缓和层102为用于缓和在支撑基板101与下述的第一密封体105之间产生的应力而设置的绝缘层。在下面将对应力缓和层102进行详细说明。在本实施方式的半导体封装件100中,使用膜厚为10~200μm的热固性树脂或热塑性树脂(例如,环氧类树脂)。另外,也可以为提高了热传导率的无机材料或包含金属填充剂的材料。
在应力缓和层102上经由粘接材料(管芯连接材料)103而设置有半导体器件104。粘接材料103为用于粘接支撑基板与半导体器件的公知的粘接材料(在这里,为粘接应力缓和层102与半导体器件104的粘接材料),在本实施方式中,使用管芯附着膜。
此外,在本实施方式中,使用粘接材料103来粘接半导体器件104,但也可以省略粘接材料103,而在应力缓和层102上直接设置半导体器件104。
半导体器件104为IC芯片或LSI芯片等半导体元件。半导体器件104经过公知的管芯切割(dicing)工序、管芯接合工序而配置于应力缓和层102上。此外,在图1中,示出了在支撑基板101上配置两个半导体器件的例子,但实际上,可以在支撑基板101上配置更多的半导体器件。由此,可以提高量产性。例如,可以在500mm×400mm的大型基板上配置500个以上的半导体器件104。
半导体器件104的上表面及侧面被第一密封体105覆盖而与外部环境隔离来加以保护。作为第一密封体105可以使用环氧类树脂,也可使用其他公知的密封用树脂。
在第一密封体105上形成有第一布线层106。在这里,第一布线层106由铜种子层(copper seed layer)106a与铜布线106b构成。当然,不局限于铜,只要是铝或银等可确保与半导体器件的良好的电连接的材料,就可以使用公知的任意材料。
在第一布线层106上还设置有第二密封体107、第二布线层108。第二密封体107可使用与第一密封体105相同的材料,在此省略说明。第二布线层108与第一布线层106一样,由铜种子层108a与铜布线108b构成。在本实施方式中,布线层为第一布线层106和第二布线层108的双层结构,但布线层的数量可以增减,可以根据需要适当地确定。
在第二布线层108上设置有第三密封体(公知的阻焊剂)109,在第三密封体109上,经由开口部设置焊料球作为外部端子110。在这里,利用阻焊剂作为第三密封体109,但也可以使用与第一密封体105或第二密封体107相同的材料,由于与外部空气直接相接触,因而也可使用作为保护膜的功能性更优良的材料。另外,由焊料球构成的外部端子110利用260℃左右的回流焊处理来形成即可。
以上说明的本发明第一实施方式的半导体封装件100通过在支撑基板101的主面设置应力缓和层102,来减少因支撑基板101与第一密封体105之间的物性(物理特性)值(尤其,弹性模量、线膨胀系数)之差而产生的应力。以下,详细说明应力缓和层102的物性。
在本发明第一实施方式的半导体封装件100中,应力缓和层102的作用是减少因支撑基板101的物性值与第一密封体105的物性值之差而产生的内部应力(支撑基板101与第一密封体105的边界面产生的应力)。为此,优选地,作为应力缓和层102,使用弹性模量比支撑基板101及第一密封体105的弹性模量小的绝缘层。
具体地,确定支撑基板101、应力缓和层102及第一密封体105的组合,以便在相同温度条件下,设支撑基板101的弹性模量为A,设应力缓和层102的弹性模量为B,并设第一密封体105的弹性模量为C的情况下,使得A>C>B或C>A>B成立。
像这样,应力缓和层102优选为低弹性。例如,优选地,在约25℃(室温)的温度区域中,具有2GPa以下的弹性模量,并且在大于100℃的温度区域中,具有100MPa以下的弹性模量。对各个温度区域中的弹性模量设置上限的原因在于,若超过这些上限值,则应力缓和层102太硬,导致作为应力缓和层的功能下降。
即,在室温条件下,为了即使具有某种程度的硬度(即使弹性模量高),也充分发挥作为应力缓和层的功能,因此应力缓和层102的弹性模量为至少2GPa以下即可。另一方面,在热固化性树脂的固化温度(170℃左右)附近等、大于100℃的温度区域(例如大于150℃的温度区域)中,使应力缓和层102的弹性模量为100MPa以下。这是因为在这种高温区域,若大于100MPa,则存在无法实现作为应力缓和层的功能的担忧。
此外,弹性模量越低,作为应力缓和层的功能就越强,但若弹性模量太低,则由于流动性极高,存在已无法维持作为层的形状的担忧。因此,在本实施方式中,虽未特别地对弹性模量设置下限,但前提条件是具有可在室温到260℃(下述的回流焊温度)的范围内维持形状的范围的弹性模量。
另外,在使用满足上述弹性模量的关系的绝缘层作为应力缓和层102的情况下,其结果,若在相同温度条件下,设支撑基板101的线膨胀系数定为a,设应力缓和层102的线膨胀系数为b,并设第一密封体105的线膨胀系数为c,则a≤c<b(或者,a≒c<b)成立。
通常,金属基板的线膨胀系数为20ppm/℃左右,密封体的线膨胀系数为数十ppm/℃左右。为此,在本实施方式的半导体封装件100中,使用在200℃以下的温度区域中线膨胀系数为100~200ppm/℃、优选为100~150ppm/℃的绝缘层。此外,200℃以下的温度区域这一条件是根据半导体封装件的制造工序中上限温度为200℃左右而设定的。优选至少在半导体封装件的制造工序中,线膨胀系数处于上述的范围内。
进而,在本发明第一个实施方式的半导体封装件100中,优选地,使用5%重量减少温度为300℃以上的粘接材料作为应力缓和层102。设定上述条件的原因如下:由于通常的回流焊温度为260℃左右,因而使用经过回流焊处理重量减少也少的绝缘层(即,具有回流焊耐受性的绝缘层),据此来防止半导体封装件的可靠性下降。
此外,“重量减少温度”是用于表示物质的耐热性的指标之一,用一边使氮气或空气流动、一边从室温开始慢慢地加热微量的物质,而发生规定的重量减少的温度来表示。在这里,表示发生5%的重量减少的温度。
进而,优选地,使用对支撑基板(由铁合金或铜合金等代表性的金属材料形成的基板)101和第一密封体(环氧类、酚(phenol)类或聚酰亚胺类等树脂)105双方均具有在日本工业标准(JIS)的棋盘格胶带试验(旧JIS K5400)中分类为“分类0”的附着力的树脂作为应力缓和层102。由此,可提高支撑基板101与第一密封体105之间的紧贴性,进而可以抑制第一密封体105的膜剥离。
像以上那样,本发明第一实施方式的半导体封装件100的特征在于,使用满足以下条件中的至少任一个条件(优选为所有条件)的绝缘层作为应力缓和层102,具体条件如下:(1)在相同温度条件下,设支撑基板101的弹性模量为A,设应力缓和层102的弹性模量为B,并且设第一密封体105的弹性模量为C的情况下,A>C>B或C>A>B成立;(2)在相同温度条件下,设支撑基板101的线膨胀系数为a,设应力缓和层102的线膨胀系数为b,并设第一密封体105的线膨胀系数为c的情况下,a≤c<b(或a≒c<b)成立。
由此,可以减少由支撑基板101与第一密封体105之间的物性值之差所引起的内部应力,尽可能防止支撑基板101、第一密封体105发生翘曲,并可以提高作为半导体封装件的可靠性。
<制造工序>
图3~图6为示出本发明第一实施方式的半导体封装件100的制造工序的图。在图3(A)中,在支撑基板101上形成应力缓和层102。在这里,使用铁合金的不锈钢基板(SUS基板)作为支撑基板101,但只要是具有一定程度的刚性的基板即可,也可以用由其他材料形成的基板。例如,也可以为玻璃基板、硅基板、陶瓷基板、有机基板。
使用膜厚为10~200μm的热固性树脂作为应力缓和层102。如上所述,应力缓和层102的物性值满足以下条件中的至少任一个条件(优选为所有条件),具体条件如下:(1)在相同温度条件下,设支撑基板101的弹性模量为A,设应力缓和层102的弹性模量为B,并设第一密封体105的弹性模量为C的情况下,A>C>B或C>A>B成立;(2)在相同温度条件下,设支撑基板101的线膨胀系数为a,设应力缓和层102的线膨胀系数为b,并设第一密封体105的线膨胀系数为c的情况下,a≤c<b(或a≒c<b)成立。
另外,优选地,使用针对支撑基板101和第一密封体105双方均具有JIS的棋盘格胶带试验(旧JIS K5400)中分类为“分类0”的附着力的树脂,作为应力缓和层102。
在形成应力缓和层102后,接着如图3(B)所示,使用粘接材料103将半导体器件104粘接于应力缓和层102上。在这里,作为粘接材料103,使用公知的管芯附着膜。
具体地,首先,在晶片上利用公知的半导体工艺来制造多个半导体器件(半导体元件),在将管芯附着膜贴附于半导体器件的状态下执行背面研磨工序(晶片的厚度减薄化)。之后,通过管芯切割工序来将多个半导体器件单片化,并将连带粘接材料103而分离的多个半导体器件104粘接于应力缓和层102上。这样,在支撑基板101上配置多个半导体器件104,并在封装化后将其各自地分离,据此大幅度地提高量产性。
接着,如图3(C)所示,以覆盖半导体器件104的方式形成第一密封体105。作为第一密封体105,可以使用环氧类树脂、酚(phenol)类树脂以及聚酰亚胺类树脂中的任意一种。可以为热固性树脂,也可以为光固性树脂。另外,第一密封体105也可以使用丝网印刷法、旋涂法等公知的任意一种涂敷方法。
在形成第一密封体105后,接着,利用公知的光刻技术或公知的激光加工技术对第一密封体105进行图案化,而形成多个开口部105a(图4(A))。这些开口部105a用于确保之后要形成的第一布线层106和半导体器件104的电连接。
接着,如图4(B)所示,以覆盖第一密封体105及开口部105a的方式形成铜种子层106a。铜种子层106a为以作为镀铜(copper plating)的基底的铜、镍铬(NiCr)、钛、或者钛钨(TiW)等为主要成分的薄膜,例如,利用溅射法来形成。
接着,如图4(C)所示,在形成铜种子层106a之后,形成覆盖铜种子层106a的抗蚀剂掩模21。关于抗蚀剂掩模21的形成,可在利用公知的方法(例如旋涂法)来涂敷抗蚀剂材料之后,通过光刻技术或者公知的激光加工技术来形成开口部21a。上述开口部21a作为下述的铜布线106b的形成区域发挥功能。
在对抗蚀剂掩模21形成开口部21a之后,通过镀铜在铜种子层106a上形成铜布线106b(图5(A))。镀铜可利用电镀,也可利用无电解镀。另外,在本实施方式中,通过镀铜来形成铜布线106b,但并不局限于此,也可以通过其他方法来形成铜布线106b。例如,也可使用溅射法、蒸镀法等。
接着,如图5(B)所示,除去抗蚀剂掩模21,接着,如图5(C)所示,将铜布线106b作为掩模对铜种子层106a进行刻蚀来除去。利用刻蚀除去铜种子层106a,据此将铜布线106b进行电隔离,而作为第一布线层106发挥作用。
在形成铜布线106b之后,接着,形成第二密封体107,并通过光刻技术或者公知的激光加工技术来形成开口部107a(图6(A))。第二密封体107的形成与第一密封体105相同,因而省略其说明。开口部107a用于将下述的外部端子110与第一布线层106电连接。
接着,如图6(B)所示,以掩埋设置于第二密封体107的开口部107a的方式形成外部端子(在这里,焊料球)110。关于外部端子110的形成,也可以使用公知的任何方法。在这里,利用260℃的回流焊处理来进行。另外,也可以形成销形状的金属导体来代替焊料球。
最后,如图6(C)所示,通过公知的切割工序来切割每个支撑基板101,而将各个半导体器件104分离。如此,形成多个半导体封装件100a、100b。
此外,在图3~图6所示的制造工序中,采用了在第一布线层106设置外部端子110的结构,但也可以如图2所示,在形成外部端子110之前,还形成第二布线层108。
通过以上的制造工序,完成图1所示的本发明的半导体封装件100。根据本发明,采用将满足上述的规定的条件的应力缓和层102设置于支撑基板101上的结构,因而可降低在之后的加热工序(热固性树脂的固化处理、焊料球的回流焊处理)中,因支撑基板101与第一密封体105之间的物性值之差所引起的内部应力,实现整体上尽可能地抑制翘曲的半导体封装件的制造工序。
(第二实施方式)
图7的(A)示出了本发明第二实施方式的半导体封装件200的剖面图。第二实施方式的半导体封装件200中,在应力缓和层102上设置有导电层31,这一点与第一实施方式的半导体封装件100不同。其他方面与第一实施方式的半导体封装件100相同。
在图7的(A)中,导电层31不局限于铜,也可以使用铝或银等任何材料,但为了有效地执行半导体器件104的散热,优选地,使用热传导率良好的金属材料。
此外,在图7的(A)所示的半导体封装件200中,为了提高从半导体器件104的下方整体的散热效果,如图8的(A)所示,在半导体器件104的下方设置矩形(在本实施方式中是正方形)的导电层31。当然,导电层31的形状不局限于矩形,可以呈任何形状。在图8的(A)中,虚线表示半导体器件104的轮廓,在比导电层31更靠内侧的位置配置半导体器件104。
另外,如图7的(A)所示,导电层31可以与上层的铜布线32、33电连接。在这里,示出了与形成于第二密封体107上的第二布线层108电连接的例子,但也可以与形成于第一密封体105上的第一布线层106电连接。为此,可以使导电层31发挥布线的功能,或者发挥电容(电容器)、电阻、电感器等负载元件的功能。
另外,图7的(B)为本发明第二实施方式的半导体封装件200a的剖面图。如图7的(B)所示,也可以将导电层31a设置在半导体器件104的轮廓的内侧。另外,在本实施方式中,将基于导电层31a的台阶差形成为被粘接材料103a填埋的结构,将粘接材料103a作为平坦化层使用。这种情况下,作为粘接材料103a,优选使用在半导体器件104粘接时具有充分的流动性的材料。另外,关于半导体封装件200a,如图8的(B)所示,导电层31a的轮廓位于半导体器件104的轮廓的内侧。
如上所述,在第二实施方式的半导体封装件200以及200a中,除了第一实施方式的半导体封装件100所发挥的效果之外,可以使用导电层31来形成连接各半导体器件之间的布线或构成各种功能电路的负载元件,因而可以获得提高电路设计的自由度的效果。
进而,可以通过在半导体器件104的下方设置由热传导率良好的金属形成的导电层,来提高半导体器件104的散热效果,可以实现散热性优异、可靠性高的半导体封装件。
(第三实施方式)
图9的(A)示出了本发明第三实施方式的半导体封装件300的剖面图。第三实施方式的半导体封装件300中,对设置于应力缓和层102上的导电层进行图案化来积极地用作布线,这一点与第二实施方式的半导体封装件200不同。其他方面与第二实施方式的半导体封装件200相同。
在图9的(A)中,导电层41不局限于铜,也可以使用铝或银等任何材料。在图中,可观察到分离成多个导电层41,但实际上如图10所示,是相互电连接的,发挥将形成于半导体器件的元件之间连接的布线的功能,或者发挥各种负载元件的功能。
作为可由导电层41形成的负载元件,可以例举电容(电容器)、电阻、电感器等。当然,除此之外,只要是可将导电层图案化而形成的元件,就可以形成任何元件。
另外,如图9的(A)所示,导电层41可与上层的铜布线42、43电连接。在这里,示出了与形成于第二密封体107上的第二布线层108电连接的例子,但也可以与形成于第一密封体105上的第一布线层106电连接。
另外,图9的(B)为本发明第三实施方式的半导体封装件300b的剖面图。如图9的(B)所示,在本实施方式中,将基于导电层41的图案的台阶差形成为被粘接材料103b填埋的结构,将粘接材料103b作为平坦化层使用。这种情况下,作为粘接材料103b,优选使用在半导体器件104粘接时具有充分的流动性的材料。另外,图9的(C)为本发明第三实施方式的半导体封装件300c的剖面图。如图9的(C)所示,在本实施方式中,也可以形成为将基于导电层41的图案的台阶差形成为被平坦化层111填埋的结构,在平坦化层111之上经由粘接材料103设置半导体器件104的结构。此时,作为平坦化层111,可以使用公知的树脂材料。例如,可以使用与应力缓和层102相同的材料,也可以使用与第一密封体105相同的材料。
如上所述,在第三实施方式的半导体封装件300、300b以及300c中,除了第二实施方式的半导体封装件200所取得的效果之外,可以使用导电层41来形成连接各半导体器件之间的布线或构成各种功能电路的负载元件,因而具有提高电路设计的自由度的效果。
(第四实施方式)
图11示出了本发明第四实施方式的半导体封装件400的剖面图。第四实施方式的半导体封装件400中,不在半导体器件104的下侧设置导电层51,这一点与第二实施方式的半导体封装件200不同。其他方面与第二实施方式的半导体封装件200相同。
在图11所示的半导体封装件400中,未在半导体器件104的下侧设置导电层51,因而半导体器件104与支撑基板101之间的距离会缩短与导电层51的厚度相对应的量。在本实施方式的结构的情况下,如图12所示,导电层51呈面积稍大于半导体器件104的面积且一部分中空的形态。关于这种结构,例如,在形成导电层51之后,对导电层51进行刻蚀而使应力缓和层102露出,在使应力缓和层102露出的部分配置半导体器件104即可。
这种情况下,如图11所示,导电层51也可以与上层的铜布线52、53电连接。另外,示出了与形成于第二密封体107上的第二布线层108电连接的例子,但也可以与形成于第一密封体105上的第一布线层106电连接。
如上所述,在第四实施方式的半导体封装件400中,除了第一实施方式及第二实施方式的半导体封装件所取得的效果之外,还具有将半导体封装件整体厚度变薄的效果。
(第五实施方式)
图13示出了本发明第五实施方式的半导体封装件500的剖面图。第五实施方式的半导体封装件500中,不在半导体器件104的下侧设置粘接材料103,这一点与第一实施方式的半导体封装件100不同。其他方面与第一实施方式的半导体封装件100相同。
在本发明第五实施方式的半导体封装件500中,在应力缓和层102上配置半导体器件104时,可以直接在应力缓和层102上粘接半导体器件104而不使用粘接材料103。具体地,在设置了形成应力缓和层102的树脂之后,在进行固化(烘焙)工序之前,搭载半导体器件104,并在该状态下进行固化工序即可。
由此,不需要使用管芯附着膜等粘接材料,因而与第一个实施方式的半导体封装件相比,可以减少发生应力的可能性,进而由于减小了与粘接材料相对应的量的厚度,因而可实现半导体封装件的小型化。
(第六实施方式)
在上述的第一实施方式至第五实施方式的半导体封装件中,采用在应力缓和层102上设置半导体器件104的结构,但此时,需要将半导体器件104配置于准确的位置。但是,可以预想的是,在支撑基板101上设置应力缓和层102的情况下,即使在支撑基板101上设置了对准标记,也会由于应力缓和层102存在而难以确认位置。
由此,第六实施方式的半导体封装件600的特征为,设置了将半导体器件104配置在应力缓和层102上时,可以准确地进行对准的对准标记。
图14(A)为示出本发明第六实施方式的半导体封装件600的一部分的俯视图,图14(B)为被图14(A)所示的虚线62包围的区域的放大图。
在图14(A)中,在支撑基板101上的大致整个面设置有应力缓和层102,在上述应力缓和层102上配置有多个半导体器件104。第六实施方式的半导体封装件600的特征在于,在应力缓和层102的一部分设置有开口部63,并用作对准标记,上述对准标记作为在配置半导体器件104时的基准。
开口部63可以通过对应力缓和层102进行刻蚀来形成,可以使用激光刻蚀等公知的刻蚀技术。可将开口部63本身用作对准标记,也可以在通过开口部63露出的支撑基板101的表面利用半刻蚀等设置槽、孔等。这种情况下,可以在形成应力缓和层102之前,预先对支撑基板101进行刻蚀来形成槽、孔,也可在形成开口部63之后,通过激光刻蚀等在支撑基板101上形成槽、孔。
但是,若开口部63的尺寸大到所需程度以上,则存在应力缓和层102从上述开口部63剥落的担忧,因而,优选地,对开口部63的尺寸设置一定的限制。
根据本发明人的实验结果,确认了若开口部63的一边大于480μm(或直径大于480μm),则有可能影响应力缓和层102的可靠性。为此,优选地,开口部63呈一边为至少480μm以下的多边形或直径为480μm以下的圆形。此外,开口部63的尺寸的下限值可根据支撑基板的材质、开口加工精度或管芯连接装置的对准性能而少量变动,因而可适当地确定。
在这里,对本发明人进行的实验的结果进行说明。本发明人通过利用图3~图6说明的工序来制作半导体封装件,并对制作而成的半导体封装件进行基于固态技术协会(JEDEC)标准的等级2的湿度可靠性试验(MRT,Moisture Reliability Test)。此外,在制作半导体封装件时,如利用图14所说明的那样,将形成于应力缓和层的开口部用作对准标记。
关于湿度可靠性试验,是通过在温度为85℃、湿度为60%的气氛条件下,将半导体封装件放置168小时,使其充分地吸收水分之后,在最高温度为260℃的标准回流焊条件下通过4次来进行的。试验后的评价使用超声波成像装置(SAT,Scanning AcousticTomograph)来进行。
图15为形成一边为400μm的尺寸的开口部的情况下的可靠性评价结果。图16为形成一边为500μm的尺寸的开口部的情况下的可靠性评价结果。图17为形成一边为600μm的尺寸的开口部的情况下的可靠性评价结果。
如图15~图17所示,在开口部的一边为500μm及600μm的情况下,在半导体封装件的面内发生了缺陷,但在开口部的一边为400μm的情况下,不会发生缺陷。进而,本发明人对开口部的一边为400μm的半导体封装件施加更苛刻的条件(基于JEDEC标准的等级1的湿度可靠性试验),并进行了进一步的实验结果的验证。
图18为一边为400μm的尺寸的开口部的可靠性评价结果。在上述可靠性评价中,将半导体封装件在温度为85℃、湿度为85%的气氛条件下放置168小时,以使其充分地吸收水分之后,在最高温度为260℃的标准回流焊条件下通过3次来进行评价。试验后的评价使用上述的超声波成像装置来进行。结果确认了,如图18所示,在基于JEDEC标准的等级1的湿度可靠性试验前后,半导体封装件的外观没有任何变化,可确保高的可靠性。
若考虑上述的结果和形成对准标记时的加工精度(σ=6μm),则500μm±3σ的范围被认为具有可能发生缺陷的担忧。即,可以说确认了若开口部的一边大于480μm(或直径大于480μm),则有可能对应力缓和层的可靠性产生影响。
如上所述,第六实施方式的半导体封装件600中,在半导体器件104的附近(例如,半导体器件104的角部)具有通过应力缓和层102的刻蚀而形成的开口部63,将上述开口部63用作将半导体器件104配置于应力缓和层102上时的对准标记,据此能够进行准确的对准操作,并可以提高半导体封装件的制造工序的成品率或可靠性。
另外,使开口部63呈一边为至少480μm以下的多边形或直径为480μm以下的圆形(更优选地,一边为至少400μm以下的多边形或直径为400μm以下的圆形),据此可以防止应力缓和层102的膜剥落。由此,可以在不影响第一实施方式至第五实施方式中的半导体封装件所具有的优点的情况下,提高半导体封装件的制造工序的成品率或可靠性。
本发明人在以下条件下制作样品来进行可靠性试验,并确认了未发生密封体的剥落等。
(实施例1)
支撑基板:金属基板(弹性模量:193GPa@25℃、100℃)
应力缓和层:改性环氧类树脂(弹性模量:580MPa@25℃、4MPa@100℃)
密封体:环氧类树脂(弹性模量:16GPa@25℃、14.7GPa@100℃)
(实施例2)
支撑基板:金属基板(弹性模量:193GPa@25℃、100℃)
应力缓和层:改性环氧类树脂(弹性模量:10MPa@25℃、0.6MPa@100℃)
密封体:环氧类树脂(弹性模量:1.8GPa@25℃、1GPa@100℃)
如上所述,调节各弹性模量的关系,使得在相同温度条件下,设支撑基板的弹性模量为A,设应力缓和层的弹性模量为B,并设密封体的弹性模量为C的情况下,A>C>B或C>A>B成立,由此可实现减少在支撑基板与密封体之间产生的内部应力并且可靠性高的半导体封装件。
Claims (34)
1.一种半导体封装件,其特征在于,包括:
支撑基板;
应力缓和层,其设置于上述支撑基板的主面;
半导体器件,其配置在上述应力缓和层之上;
密封体,其由与上述应力缓和层不同的绝缘材料形成,用于覆盖上述半导体器件;
布线,其贯通上述密封体而与上述半导体器件电连接;以及
外部端子,其与上述布线电连接,
当在相同温度条件下,设上述支撑基板的弹性模量为A,设上述应力缓和层的弹性模量为B,并设上述密封体的弹性模量为C时,A>C>B或C>A>B的关系成立。
2.根据权利要求1所述的半导体封装件,其特征在于,在室温下,上述应力缓和层的弹性模量为2GPa以下,并且在大于100℃的温度下,上述应力缓和层的弹性模量为100MPa以下。
3.根据权利要求1所述的半导体封装件,其特征在于,当在相同温度条件下,设上述支撑基板的线膨胀系数为a,设上述应力缓和层的线膨胀系数为b,并设上述密封体的线膨胀系数为c时,a≤c<b或a≒c<b的关系成立。
4.根据权利要求1所述的半导体封装件,其特征在于,在上述半导体器件的周围具有设置于上述应力缓和层的开口部。
5.根据权利要求4所述的半导体封装件,其特征在于,上述开口部为对准标记,呈至少一边为480μm以下的多边形或直径为480μm以下的圆形。
6.一种半导体封装件,其特征在于,包括:
支撑基板;
应力缓和层,其设置于上述支撑基板的主面;
导电层,其设置在上述应力缓和层之上;
半导体器件,其配置在上述导电层之上;
密封体,其由与上述应力缓和层不同的绝缘材料形成,用于覆盖上述半导体器件;
布线,其贯通上述密封体而与上述半导体器件电连接;以及
外部端子,其与上述布线电连接,
当在相同温度条件下,设上述支撑基板的弹性模量为A,设上述应力缓和层的弹性模量为B,并设上述密封体的弹性模量为C时,A>C>B或C>A>B的关系成立。
7.根据权利要求6所述的半导体封装件,其特征在于,上述导电层至少构成电容器、电阻及电感器中的任一种。
8.根据权利要求6或7所述的半导体封装件,其特征在于,在室温下,上述应力缓和层的弹性模量为2GPa以下,并且在大于100℃的温度下,上述应力缓和层的弹性模量为100MPa以下。
9.根据权利要求6或7所述的半导体封装件,其特征在于,当在相同温度条件下,设上述支撑基板的线膨胀系数为a,设上述应力缓和层的线膨胀系数为b,并设上述密封体的线膨胀系数为c时,a≤c<b或a≒c<b的关系成立。
10.根据权利要求6或7所述的半导体封装件,其特征在于,在上述半导体器件的周围具有设置于上述应力缓和层的开口部。
11.根据权利要求10所述的半导体封装件,其特征在于,上述开口部为对准标记,呈至少一边为480μm以下的多边形或直径为480μm以下的圆形。
12.一种半导体封装件,其特征在于,包括:
支撑基板;
应力缓和层,其设置于上述支撑基板的主面;
导电层,其设置在上述应力缓和层之上;
半导体器件,其被上述导电层包围,并且配置在上述应力缓和层之上;
密封体,其由与上述应力缓和层不同的绝缘材料形成,用于覆盖上述半导体器件;
布线,其贯通上述密封体而与上述半导体器件电连接;以及
外部端子,其与上述布线电连接,
当在相同温度条件下,设上述支撑基板的弹性模量为A,设上述应力缓和层的弹性模量为B,并设上述密封体的弹性模量为C时,A>C>B或C>A>B的关系成立。
13.根据权利要求12所述的半导体封装件,其特征在于,上述导电层至少构成电容器、电阻及电感器中的任一种。
14.根据权利要求12或13所述的半导体封装件,其特征在于,在室温下,上述应力缓和层的弹性模量为2GPa以下,并且在大于100℃的温度下,上述应力缓和层的弹性模量为100MPa以下。
15.根据权利要求12或13所述的半导体封装件,其特征在于,当在相同温度条件下,设上述支撑基板的线膨胀系数为a,设上述应力缓和层的线膨胀系数为b,并设上述密封体的线膨胀系数为c时,a≤c<b或a≒c<b的关系成立。
16.根据权利要求12或13所述的半导体封装件,其特征在于,在上述半导体器件的周围具有设置于上述应力缓和层的开口部。
17.根据权利要求16所述的半导体封装件,其特征在于,上述开口部为对准标记,呈至少一边为480μm以下的多边形或直径为480μm以下的圆形。
18.一种半导体封装件的制造方法,其特征在于,包括:
在支撑基板的主面形成应力缓和层的工序;
在上述应力缓和层之上配置至少一个半导体器件的工序;
利用由与上述应力缓和层不同的材料形成的密封体来覆盖上述半导体器件的工序;
形成贯通上述密封体而与上述半导体器件电连接的布线的工序;以及
形成与上述布线电连接的外部端子的工序,
当在相同温度条件下,设上述支撑基板的弹性模量为A,设上述应力缓和层的弹性模量为B,并设上述密封体的弹性模量为C时,A>C>B或C>A>B的关系成立。
19.根据权利要求18所述的半导体封装件的制造方法,其特征在于,在室温下,上述应力缓和层的弹性模量为2GPa以下,并且在大于100℃的温度下,上述应力缓和层的弹性模量为100MPa以下。
20.根据权利要求18所述的半导体封装件的制造方法,其特征在于,当在相同温度条件下,设上述支撑基板的线膨胀系数为a,设上述应力缓和层的线膨胀系数为b,并设上述密封体的线膨胀系数为c时,a≤c<b或a≒c<b的关系成立。
21.根据权利要求18所述的半导体封装件的制造方法,其特征在于,在上述半导体器件的周围具有设置于上述应力缓和层的开口部。
22.根据权利要求21所述的半导体封装件的制造方法,其特征在于,上述开口部为对准标记,呈至少一边为480μm以下的多边形或直径为480μm以下的圆形。
23.一种半导体封装件的制造方法,其特征在于,包括:
在支撑基板的主面形成应力缓和层的工序;
在上述应力缓和层之上形成导电层的工序;
在上述导电层之上配置至少一个半导体器件的工序;
利用由与上述应力缓和层不同的材料形成的密封体来覆盖上述半导体器件的工序;
形成贯通上述密封体而与上述半导体器件电连接的布线的工序;以及
形成与上述布线电连接的外部端子的工序,
当在相同温度条件下,设上述支撑基板的弹性模量为A,设上述应力缓和层的弹性模量为B,并设上述密封体的弹性模量为C时,A>C>B或C>A>B的关系成立。
24.根据权利要求23所述的半导体封装件的制造方法,其特征在于,上述导电层至少构成电容器、电阻及电感器中的任一种。
25.根据权利要求23或24所述的半导体封装件的制造方法,其特征在于,在室温下,上述应力缓和层的弹性模量为2GPa以下,并且在大于100℃的温度下,上述应力缓和层的弹性模量为100MPa以下。
26.根据权利要求23或24所述的半导体封装件的制造方法,其特征在于,当在相同温度条件下,设上述支撑基板的线膨胀系数为a,设上述应力缓和层的线膨胀系数为b,并设上述密封体的线膨胀系数为c时,a≤c<b或a≒c<b的关系成立。
27.根据权利要求23或24所述的半导体封装件的制造方法,其特征在于,在上述半导体器件的周围具有设置于上述应力缓和层的开口部。
28.根据权利要求27所述的半导体封装件的制造方法,其特征在于,上述开口部为对准标记,呈至少一边为480μm以下的多边形或直径为480μm以下的圆形。
29.一种半导体封装件的制造方法,其特征在于,包括:
在支撑基板的主面形成应力缓和层的工序;
在上述应力缓和层之上形成导电层的工序;
对上述导电层进行刻蚀而使上述应力缓和层露出的工序;
在使上述应力缓和层露出的区域配置至少一个半导体器件的工序;
利用由与上述应力缓和层不同的材料形成的密封体来覆盖上述半导体器件的工序;
形成贯通上述密封体而与上述半导体器件电连接的布线的工序;以及
形成与上述布线电连接的外部端子的工序,
当在相同温度条件下,设上述支撑基板的弹性模量为A,设上述应力缓和层的弹性模量为B,并设上述密封体的弹性模量为C时,A>C>B或C>A>B的关系成立。
30.根据权利要求29所述的半导体封装件的制造方法,其特征在于,对上述导电层进行图案化而至少形成电容器、电阻以及电感器中的任一种。
31.根据权利要求29或30所述的半导体封装件的制造方法,其特征在于,在室温下,上述应力缓和层的弹性模量为2GPa以下,并且在大于100℃的温度下,上述应力缓和层的弹性模量为100MPa以下。
32.根据权利要求29或30所述的半导体封装件的制造方法,其特征在于,当在相同温度条件下,设上述支撑基板的线膨胀系数为a,设上述应力缓和层的线膨胀系数为b,并设上述密封体的线膨胀系数为c时,a≤c<b或a≒c<b的关系成立。
33.根据权利要求29或30所述的半导体封装件的制造方法,其特征在于,在上述半导体器件的周围,对上述应力缓和层进行刻蚀而形成开口部。
34.根据权利要求33所述的半导体封装件的制造方法,其特征在于,上述开口部为对准标记,呈至少一边为480μm以下的多边形或直径为480μm以下的圆形。
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US9786611B2 (en) | 2017-10-10 |
US20160351511A1 (en) | 2016-12-01 |
CN105280567A (zh) | 2016-01-27 |
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