CN1675759A - 使用金属氧化物形成双重栅极氧化物器件的方法及其合成器件 - Google Patents

使用金属氧化物形成双重栅极氧化物器件的方法及其合成器件 Download PDF

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Publication number
CN1675759A
CN1675759A CNA038194023A CN03819402A CN1675759A CN 1675759 A CN1675759 A CN 1675759A CN A038194023 A CNA038194023 A CN A038194023A CN 03819402 A CN03819402 A CN 03819402A CN 1675759 A CN1675759 A CN 1675759A
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China
Prior art keywords
gate
metal oxide
dielectric
gate dielectric
layer
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Pending
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CNA038194023A
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English (en)
Chinese (zh)
Inventor
大卫·C·吉尔默
克里斯托佛·C·霍布斯
曾兴黄
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of CN1675759A publication Critical patent/CN1675759A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers
    • H10P14/6328—
    • H10P14/69391—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
CNA038194023A 2002-08-15 2003-06-16 使用金属氧化物形成双重栅极氧化物器件的方法及其合成器件 Pending CN1675759A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/219,522 US6787421B2 (en) 2002-08-15 2002-08-15 Method for forming a dual gate oxide device using a metal oxide and resulting device
US10/219,522 2002-08-15

Publications (1)

Publication Number Publication Date
CN1675759A true CN1675759A (zh) 2005-09-28

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CNA038194023A Pending CN1675759A (zh) 2002-08-15 2003-06-16 使用金属氧化物形成双重栅极氧化物器件的方法及其合成器件

Country Status (7)

Country Link
US (1) US6787421B2 (enExample)
JP (1) JP2005536053A (enExample)
KR (1) KR20050054920A (enExample)
CN (1) CN1675759A (enExample)
AU (1) AU2003285819A1 (enExample)
TW (1) TW200414529A (enExample)
WO (1) WO2004017403A1 (enExample)

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CN103915437A (zh) * 2012-12-28 2014-07-09 台湾积体电路制造股份有限公司 半导体结构及其形成方法
CN104124242A (zh) * 2013-04-23 2014-10-29 美国博通公司 分离式多栅极场效应晶体管
CN104183470A (zh) * 2013-05-21 2014-12-03 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN108122750A (zh) * 2016-11-29 2018-06-05 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN108630605A (zh) * 2017-03-22 2018-10-09 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法

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US20060088962A1 (en) * 2004-10-22 2006-04-27 Herman Gregory S Method of forming a solution processed transistor having a multilayer dielectric
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CN102332398B (zh) * 2011-10-28 2012-12-12 上海华力微电子有限公司 一种双高k栅介质/金属栅结构的制作方法
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CN103824771A (zh) * 2012-11-16 2014-05-28 中芯国际集成电路制造(上海)有限公司 栅氧化层的形成方法
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CN103915437A (zh) * 2012-12-28 2014-07-09 台湾积体电路制造股份有限公司 半导体结构及其形成方法
CN103915437B (zh) * 2012-12-28 2016-12-28 台湾积体电路制造股份有限公司 半导体结构及其形成方法
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CN104183470A (zh) * 2013-05-21 2014-12-03 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN104183470B (zh) * 2013-05-21 2017-09-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN108122750A (zh) * 2016-11-29 2018-06-05 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN108122750B (zh) * 2016-11-29 2020-06-09 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN108630605A (zh) * 2017-03-22 2018-10-09 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
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Also Published As

Publication number Publication date
JP2005536053A (ja) 2005-11-24
KR20050054920A (ko) 2005-06-10
TW200414529A (en) 2004-08-01
WO2004017403A1 (en) 2004-02-26
US20040032001A1 (en) 2004-02-19
US6787421B2 (en) 2004-09-07
AU2003285819A1 (en) 2004-03-03

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