TW540117B - Method for improving the roughness of the sidewall of a polysilicon layer in an etching process - Google Patents

Abstract

A method for improving the roughness of the sidewall of a polysilicon layer in an etching process comprises: depositing a polysilicon layer on a semiconductor substrate; performing a multi-stage etching process on the polysilicon layer to define a polysilicon gate on the upper surface of the semiconductor substrate, in which, upon completion of each stage's etching process, an oxidation process is performed on the exposed sidewall of the polysilicon layer to form a smooth oxidized surface layer to improve the rough surface thereof.

Description

540117 V. Description of the invention (1) Field of the invention: The present invention relates to a method for improving the roughness of the side wall of a polycrystalline silicon layer in an etching process. Related methods for oxidizing the side walls of polycrystalline stones. Background of the Invention: With the continuous progress of the semiconductor industry, in the development and design of ultra large integrated circuits (ULSI), in order to meet the design trend of high density integrated circuits, the size of various components has been reduced to sub-micron. And due to the continuous shrinking of components, the related semiconductor process often encounters unprecedented difficulties, and the complexity of the process is also increasing. Generally speaking, an integrated circuit consists of forming millions of components in a specific area on a wafer and an electronic connection structure used to connect these components in order to perform a specific function required. Based on the above reasons, how to improve the accuracy of the critical dimension (CD) of semiconductor components is very important in semiconductor-related processes. Take the production of a traditional polysilicon gate as an example to illustrate the problems encountered when the component size is continuously reduced and the line width accuracy is continuously improved. Referring to the first figure, firstly, an oxide film 12 and a polycrystalline silicon layer 14 are sequentially formed on a semiconductor substrate 10 that has completed the active area fabrication, and the polycrystalline silicon layer 14 can be formed using low-pressure chemistry. The vapor deposition method (丨 0 w pressure chemical vapor deposition; LPCVD) is produced by dissociating silane '(SiH4) by heating, and its reaction formula is

Page 4 540117 V. Description of the invention (2):

SiH4 (g) — Si (s) + 2H2 (g) Δ Wherein, when the temperature for performing the above reaction is lower than 5 7 5 ° C, the obtained silicon deposit will exist as an amorphous silicon (amorPhous); and When the temperature is between 5 7 5 ° C and 65 0 ° C, polycrystalline silicon (po 1 ysi 1 i con) is formed. In application, the temperature of this reaction is mostly controlled between 600 and 650 t, and the pressure is between about 0.3 and 0.6 Torr to form a polycrystalline silicon layer. After the polycrystalline silicon layer 14 is formed on the oxidized thin film t 1 2 by using a low-pressure chemical weather deposition method, in order to reduce the resistivity of the polycrystalline silicon layer 14, a doping reaction will be performed on it to turn it into an electrical conductor. Among them, there are three methods for doping polycrystalline silicon: (1) doping (in-situ) while performing a deposition reaction; (2) after the deposition is completed, the dopant is doped by means of high-temperature diffusion (diffusion) Drive into the polycrystalline stone layer; and (3) after the deposition is completed, the dopant is implanted into the polycrystalline form by ion implantation (ionization). Then please continue to refer to the first figure, coating the photoresist layer on the polycrystalline silicon sound:. Subsequently, as shown in the second figure, #the conventional exposure is used to display the order; define the gate opening 18 in the photoresist layer 1 β. '~ As shown in the third figure' With the photoresist layer 16 as a mask, sequentially read the small silicon layer 14 and the service read 19, 隹 >, and enter the multi-film 12 engraving process, To define polycrystalline stone

Page 5 540117 V. Description of the invention (3) Gate 20 'and exposed part of the upper surface of the semiconductor substrate 10. Finally, a part of the photoresist layer on the semiconductor substrate is removed. Worth it; I thought, when the polycrystalline silicon layer 14 is engraved to form silicon gate 20 on the semiconductor substrate 10, the ion plasma used will be in this polycrystalline silicon gate The side wall of the pole 20 causes a rough surface layer 2 2 (as shown in the fourth figure). This result will have some disadvantages: (1) When the subsequent film layer is formed, its deposition effect will be reduced, such as when a new film is formed. Between the layer and the rough sidewall of the polysilicon gate, holes are easily generated, resulting in poor adhesion between the film layer and the film layer, and the film layer peeling off; U (2), yield decreases. The surface of the polycrystalline silicon interrogator has a rough surface. Consequences: This will cause the polysilicon gate to easily break, which will reduce the yield of the process, and the polycrystalline silicon gate with excessively rough sidewalls will reduce the line width of the device. Summary: Improving polycrystalline seeds in the post-etching process and increasing line width in the etching process. A first object of the present invention is to provide a method for roughening the sidewall of a stone layer. A second object of the present invention is to provide a method of accuracy. A third object of the present invention is to provide a 540117

In order to form a process of engraving, the method of oxidizing the side wall of the polycrystalline silicon layer to form a flat side wall. -A way to define polycrystalline interrogation. First, a sequential layer and a photoresist layer are formed on the semiconductor substrate ', and then the photoresist layer is further subjected to two steps: Shi Xi: Procedure' to form an interrogation opening therein. After that, the polycrystalline silicon is multi-m carved with a photoresist power, and the layer material is removed.纟 中 ’after each period of money engraving procedure, the polycrystalline stone layer :: is subjected to a lice formation procedure to form a smooth oxidized sidewall. This etching process stops after reaching the upper surface of the semiconductor substrate, and defines polycrystalline silicon on the conductor substrate. ^% Cattle Detailed description of the invention: The present invention discloses a method for defining a polycrystalline silicon gate. Among them, a smooth oxidation side wall is formed by performing a multi-stage etching process on the polycrystalline silicon layer and performing an oxidation process on the sidewall of the polycrystalline silicon layer after each etching process. The detailed processes and examples of the present invention are described below. Please refer to the fifth figure, and first provide a semiconductor substrate 50 with a crystal orientation of < 100 >. Generally speaking, other types of semiconductor materials, such as gallium arsenide, germanium, or silicon on insulator (SOI) on the insulating layer can be used as the semiconductor substrate here. 50 used. In addition, due to the characteristics of the surface of the semiconductor substrate, the present invention does not cause any special influence.

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5. Description of the invention (5) You can also choose < 110> or < 111>. Next, a gate oxide layer 52 can be formed on the semiconductor substrate 50 to produce a desired insulating effect. Generally speaking, the gate oxide layer 52 is formed by thermal oxidation in an environment full of oxygen at a temperature of about 700 to 11000 ° C and oxygen. As for other suitable oxides or chemical combinations, procedures, such as chemical vapor deposition, can also be used to form the gate oxide layer 52 here. In a preferred embodiment, the thickness of the gate oxide layer 52 is approximately 50 to 350 angstroms. 3 Then, a polycrystalline silicon layer 54 can be formed on the gate oxide layer 52. Wherein, the thickness of the polycrystalline silicon layer 54 can be 150-1500 angstroms, and the low-pressure chemical vapor deposition (LPCVD) method can be used to deposit the required by heating and dissociating silarane. Polycrystalline silicon layer 5 4. In addition, the temperature of the deposited polycrystalline silicon layer 54 is controlled to be approximately 600 to 650 t, and the pressure is adjusted to be approximately 0.3 to 0.6 Torr. In addition, in order to reduce the resistance value of the formed polycrystalline silicon material, an in-sitij doping process can also be performed in the polysilicon's “redundant” reaction, or after the deposition process is completed, the ion implantation method is used. Dopants are implanted in the crystalline silicon layer 5 4. Then, a photoresist layer 56 is coated on the upper surface of the polycrystalline silicon layer 54, and a spin coating method may be selected as a method of forming the photoresist layer 56. After the photoresist layer 56 is formed, it is then subjected to a baking process to perform photoresist curing. This baking procedure can be divided into heating plate baking (h〇t plate bakln§) and f = =. Among them, the heating plate is baked by coating the coated 枓 + conductor substrate directly on the heating plate and applying 2 0 0 to 2 50

Page 8 540117 V. Description of the invention (6) The temperature of C is used to cure the photoresist material, and the ultraviolet curing is cured by light at a temperature of 50 ~ 250 ° C. In another embodiment, the photoresist layer 56 may be replaced by a hard mask layer. The material of the hard mask power layer can be selected from inorganic materials such as Si02, Si3N4, and SiON, and is formed by chemical vapor deposition (CVD). Then, referring to the sixth figure, the photoresist layer 56 is subjected to an exposure and lithography process to define a gate opening pattern 58 in the photoresist layer 56. Subsequently, the photoresist layer 56 is used as a mask 'to perform a multi-stage epitaxial process on the polycrystalline stone layer 54. The two-stage etching process is listed below as an example, and the above-mentioned stage etching process is described in detail. However, it is not intended to limit the spirit and the invention of the present invention, but only to this embodiment. Referring to the seventh figure, the polysilicon layer 54 is subjected to the first stage of the etching process until it reaches about one and a half heights of the polysilicon layer 54, and then stops. Among them, the sidewall of the polysilicon layer after completing the first stage of the polysilicon process has the following The picture shows $ 0 seam surface. Subsequently, the rough surface layer 60 is subjected to the first oxidation process to form a smooth sidewall 62 as shown in FIG. 8. In a preferred embodiment, the oxidation process is an oxygen plasma treatment (Oxygen-base (1 plasma treatment) process, that is, the use of pure oxygen in the etching reaction chamber, and the rough polycrystalline stone evening An oxide surface layer is generated on the sidewall of the layer. Next, a second etching process is performed on the remaining one-half polycrystalline silicon layer 54, and a second oxidation process is subsequently performed to make the polycrystalline silicon having completed the two-stage money engraving process. The sidewall of the layer has a complete smooth oxide surface layer 64 (as shown in the ninth figure). Subsequently, the polysilicon layer 54 is partially removed.

540117 V. Description of the invention (7) Part of the photoresist layer 56. It is worth noting that the etching process will continue until the upper surface of the semiconductor substrate 50 is reached, and the polysilicon gate 66 is defined, as shown in the tenth figure. In the present invention, the rough surface of the polysilicon gate sidewall is smoothed by using an oxidation process, which has the following advantages: (1) The effects of deposition and hole filling are improved. When the adhesion between the film layer and the film layer is increased, not only the film peeling phenomenon in the subsequent process can be avoided, but also the process yield can be greatly improved due to the improvement of the film deposition effect;

(2) Improve the structure pressure resistance of polysilicon gates. The smooth side wall can make the polycrystalline silicon gate have a better structural foundation to withstand the pressure given in the subsequent film deposition process; and 1 (3) improve the line width accuracy of the component. Although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the inventive substance of the present invention, but only to this embodiment. Therefore, all modifications made without departing from the spirit and scope of the present invention should be included in the scope of patent application described below.

Page 540117 Schematic illustrations Schematic illustrations: With the following detailed description combined with the attached drawings, the above content and the many advantages of this invention can be easily understood, of which: According to the silicon root crystal, multiple layers are displayed, and the membrane is thinned and the oxygen cut-off is formed into a circular crystal sequence. The upper half is used as the base material. The first half of the round crystal is cut into the middle layer. The second step of the first step of the light step is to open the gate of the technical field according to the original display plan. The previous step of the step industry is based on the original display. The conductor half gate and the silicon conducting half of the crystal are 'multi-picture for the fourth system technique', which is a graphic cutting technique based on the pre-industrial project image of the third technical field α ^ Γ. It is obvious that the surface of the layered diagram is rough and the surface of the semi-circular crystal wall body has a semi-conductive gate half gate. Oxygen Conductor for Circular Crystals The gate is formed into six patterns according to the technique, and the basis of the development is shown; the step is shown, and the pattern of the surface is cut. The open circular thyristor is used as a guide. According to the original graphic display, the half of the guide sequence of the Ipla step is the first step of the eighth paragraph of the carved picture. The formation of the first step of the n-th 'step of the ninth oxygen is based on the shape of the first step, and the basis of the step is shown. The sequence diagram shows the second round body of the second round crystal and the leading half of the sequence.刻 图 # 十 段 第二 第 The first

Page 11 540117 The diagram briefly explains the steps of polysilicon gate. Drawing number comparison table: Semiconductor substrate 10 Polycrystalline silicon layer 1 4 Gate opening 1 8 Thick chain surface layer 2 2 Gate oxide layer 5 2 Photoresistive layer 5 6 Thick chain surface layer 6 0 i Smooth oxide surface layer 6 4 Oxide film 1 2 Light Barrier layer 1 6 polycrystalline silicon gate 2 0 semiconductor substrate 50 polycrystalline silicon layer 5 4 gate opening pattern 5 8 smooth sidewall 6 2 polycrystalline silicon gate 6 6

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Claims (1)

6. Scope of patent application 1. A method for improving the roughness of the side wall of a polycrystalline silicon layer in a #etching process, in which a polycrystalline silicon layer is first deposited on a semiconductor substrate, and then a polycrystalline silicon layer is subjected to a step-and-step procedure to define multiple "Crystalline" is extremely close to the semiconductor substrate. The method includes at least the following steps. _ The surface is modified by another process, and the mother is oxidized to form a flat surface. Its rough surface: 2 · The squareness of item 丨 in the scope of patent application is about 15 0 ~ 2 500 Angstroms, in which the above polycrystalline silicon layer is thick. 3 · The square oxygen group in the scope of patent application 1 Plasma treatment procedure. '' Among the above-mentioned oxidation procedures is 4 · As described in the first item of the patent application scope, directly pass pure oxygen into the etching reaction chamber, wherein the above-mentioned oxidation procedure is a crystalline silicon layer on the semiconductor substrate. Method, the method first forms a engraving procedure to define the polysilicon gate adheres to the lithography of the polycrystalline silicon layer. The polysilicon gate structure is characterized by a slippery oxide surface, and greatly improvesAn oxidation process is performed to form the conductor substrate with a line width accuracy of 6 · As described in item 5 of the scope of the patent application, the degree is about 15 0 ~ 2 500 Angstroms. 540117 VI. Application for Patent Scope 7 · If the method of applying for the scope of the patent No.5, the above-mentioned oxidation process is an oxygen plasma treatment process. 8 · If the method of applying for the scope of the patent No.5, the above-mentioned oxidation process may Directly pass pure oxygen into the etching reaction chamber. 9 · A method for defining a polycrystalline silicon gate, the method includes at least the following steps: Forming a polycrystalline silicon layer on a semiconductor substrate; performing an etching process on the polycrystalline silicon layer to remove a portion of the polycrystalline silicon layer material; and applying an oxidation process to a sidewall of the polycrystalline silicon layer to form a smooth oxide surface layer. 10. The method according to item 9 of the patent application scope, which further comprises repeating the etching process and the oxidation process until reaching the upper surface of the semiconductor substrate, and defining a polycrystalline silicon gate on the semiconductor substrate. 1 1. The method according to item 9 of the scope of patent application, wherein the thickness of the above polycrystalline silicon layer is about 15,000 to 2500 angstroms. 1 2 · The method according to item 9 of the scope of patent application, wherein the above-mentioned oxidation procedure is an oxygen plasma treatment procedure. Page 14 540117 VI. Scope of patent application 1 3 · If the method of the scope of patent application No. 9 is applied, the above-mentioned oxidation procedure may be direct introduction of pure oxygen into the etching reaction chamber. Page 15