TW413853B - Manufacturing method for semiconductor device having small-size gate structure - Google Patents

Abstract

A manufacturing method for small-size gate structure. The present invention comprises at least two TiN side spacers. The semiconductor substrate comprises a field oxide and sequentially forming a gate oxide, polysilicide layer, the first dielectric layer and photoresist layer on the top of semiconductor substrate; then, etch the photoresist layer and the first delelectric layer to form a groove structure. Forming the second dielectric on top of semiconductor devices and etch it to form two side spacers in the groove structure; next, forming metal silicide on the gate location upon the polysilicide layer; then, forming the third dielectric layer on top of the semiconductor device; further, using wet-etching to remove the third dielectric, two side spacers and the first dielectric; lastly, using anisotropic etching to etch the gate structure.

Description

413¾53 5. Description of the invention (1) 5 ~ 1 Field of invention: The present invention relates to a method for manufacturing a semiconductor device, and in particular to a metal silicide of a titanium nitride side wall and a gate electrode, which can be made into a size Less than 0. 25 vm deep sub-micron gate length, and provide semiconductor components with low production costs. -2 Invention of Nanotechnology Recently, the demand for semiconductor devices has increased rapidly due to the large number of electronic components. In particular, the rapid spread of computers has increased the demand for semiconductor components. Since hundreds or thousands of transistors are required to make a complex integrated circuit manufactured on a single semiconductor wafer, it is important to reduce the size of the components and reduce production costs. The first diagram D shows a cross-sectional view of a conventional semiconductor element. The first a takes a conventional semiconductor element as an example, in which the silicon substrate 100 is a p-well, and the conventional conductor element, when its size is less than 0.25 jm gate At the pole length, using the existing I-Line Stepper will not provide good resolution. Because lithographic resolution is proportional to the wavelength of the stepper exposure and inversely proportional to the projected numerical aperture M (nuraericai aperture). Therefore, at 0. 25 βπι gate size, the use of expensive short-wavelength light sources (KrF248nm or ArF193nm) deep ultraviolet stepper (heart UUra-Violet ray for short) is used to improve the resolution, but it will also improve the resolution.

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Page 4 41¾853 V. Description of the invention (2) The production cost has increased significantly. The first diagram B shows an N-type semiconductor element as an example, wherein the source 280A and the drain 280B are N +, and the gate 160A is polycrystalline silicon. The first figure B uses a conventional semiconductor device as an example, and the same layers as the first figure A are represented by the same reference numerals. In addition to the structure of the first A picture, this manufacturing method increases the formation of field oxide, gate, source / drain, barrier, and film. The first C diagram uses a conventional semiconductor device as an example, and the same layer as the first B circle is represented by the same labeling number. In addition to the structure of the first B figure, this manufacturing method increases the formation of a titanium nitride layer and metal silicide. Therefore, there is an urgent need for a semiconductor device having a small size and a low production cost. [3] Purpose and summary of the invention: In view of the above-mentioned background of the invention, the existing semiconductor devices have many shortcomings. The main purpose of the present invention is to use a metal silicide of a titanium nitride sidewall spacer and a gate electrode. A semiconductor device with a gate length of less than 0.25 μm is obtained and provides a low production cost. A semiconductor device whose gate is a preferred method for forming metal silicidation on polycrystalline stones.

Another object of the present invention is to provide a parasitic resistance that rises as the element shrinks. The object (s i 1 i c i de) is to reduce the gate resistance. Another object of the present invention is to provide a semiconductor element # which controls nitrogen

The thickness of the titanium side wall is used to determine the size and length of the pole. The present invention can produce a semiconductor element with a size less than 0 · 2 5 // m deep sub-micron gate length and providing high accumulated sound. "* Furthermore, another object of the present invention is to provide a semiconductor device which can use I line stepper to obtain gate lengths smaller than 0.25 #m deep sub-micron gate length. It does not require the use of a responsible deep ultraviolet stepper (DUV), which can provide semiconductor components with low production costs. According to the structure, a field oxygen layer and a photo-dielectric layer are manufactured in a semiconducting structure. Next. Then use wet The formation layer is removed to form a shallow #dielectric layer. Using the method described above within the gate-side region, the cladding layer is sequentially blocked on the semiconducting layer to form a body element. Gold, and then form the first etching method. Then, a heterodiffusion electrode is used to form a gap in the field anisotropic etching wall of the oxide layer. Furthermore, for the purpose, a dinitride-containing nitride is used to form a groove on the substrate of the gate oxide. Junction, and the etching is a silicide triple dielectric, a third dielectric non-specific oxide layer, and a shallow doping etching method. Then it is invented to provide a titanium side wall wall layer, a multi-sided structure, and then a structure. In the shape of a polycrystalline semiconductor The fourth dielectric above the drain electrode between the gate layer and the two-etching method is formed by re-doping a small ^ semiconducting dream layer, and the size of the gate junction substrate with the first dielectric photoresist layer and erbium is formed. The second dielectric is engraved on the side gap wall # on the element above the gate position layer of the groove. Then, the second dielectric is etched with the gate quality layer to be shallower than the semiconductor. Furthermore, it is closed to the first dielectric. The electrode structure, 'forms the fourth periphery. Immediately after, it is used to form a doped dielectric material over the body substrate of the drain region.

Page 6 413853 5. Description of the invention (4), and a metal silicide is etched between the gate spacer and the field oxide layer to form a metal silicide above the contact window. The last shape of the window is a simple illustration of 5-4: The first A circle is a step of a conventional semiconductor device, which includes the definition of the gate region. " Action cross-sectional view. The first B diagram is a conventional semiconductor device, which includes a gate, a source, a drain, a spacer, and a titanium cross-section. The first C diagram is a conventional semiconductor device. form. It includes the formation of a metal silicide and a titanium nitride layer. Figure 1D is a conventional semiconductor device, which includes the removal of titanium nitride. Cross-sectional view of the actions of each step The second diagram is a semiconducting schematic diagram in the embodiment of the present invention, and the action formation including a closed oxide layer and == is formed. I The second picture of the vaporized silicon layer and the photoresist is a schematic semiconducting circle in the embodiment of the present invention, which includes the action of the photoresist and local nitrogen. "/ Etching of the layer, the sound of the titanium nitride layer." In the embodiment, the semiconductor device & each step "," which includes the formation of a gate metal silicide and a titanium nitride layer.

Page 7 Interpretation: The operation of each step of the semiconductor device in the fourth embodiment includes the formation of a side wall of titanium nitride. 4ί Norwegian 3

V. Description of the invention (5) The sixth diagram is a schematic diagram of the operation of each step of the semiconductor device in the embodiment of the present invention, which includes the removal of a titanium nitride layer, a titanium nitride sidewall spacer, and a silicon nitride layer. The seventh diagram is a schematic diagram of the operation of each step of the semiconductor device in the embodiment of the present invention, which includes the formation of a gate electrode and a shallowly doped drain electrode. The eighth figure is a schematic diagram of the operation of each step of the semiconductor element in the embodiment of the present invention, which includes the formation of a source, a drain, and a dielectric material in contact with the inner layer of the bathroom. … The representative symbols of the main parts: _ 1 00 silicon substrate 120 field oxide layer 140 gate oxide layer 1 60 polycrystalline fracture layer 16 0A gate 200 photoresistor 210 titanium film 240 gate metal; pentoxide 250 Titanium nitride layer 2 6 0 lightly doped drain 280A source 2 8 0 Β; and 300 metal nitride silicon nitride spacer 360A source metal silicide

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V. Description of the invention 360B 10 12 14 16 18 20 22 22A 24 26 28 30A 30B 32 34 36 38 38A 38B Titanium Nitride Layer Titanium Nitride Side Gap Gate Metal Silicide Titanium Nitride Layer Shallow #Hetero Drain Source Source Drain Silicon Nitride Gap Inner Layer Dielectric Material Contacts Window Source Metal Lithium Ionide Drain Metal silicide 5-5 Detailed description of the invention: Figure 8 shows a cross-sectional view of a semiconductor device in an embodiment of the present invention. The second to seventh figures show exploded views of the semiconductor device. On these

Page 9 413853 V. Description of the invention (7) In the drawings, the same elements are denoted by the same reference numerals. The second figure shows that the semiconductor substrate 10 uses a p-type stone evening substrate; however, N Type silicon substrates can also be used. Inside the wafer oxidation furnace tube, a field oxidation layer (fie d oxide) growth is performed by a wet oxidation method ^ Every two field oxide layers 12 are used to isolate semiconductor elements. Next, the wafer is sent into an oxidizing furnace tube, and the silicon on the surface is oxidized into silicon dioxide having a degree of about 100 to 250 angstroms by a dry oxidation method. This silicon dioxide layer will serve as a gate for the semiconductor device. Oxide layer (gate 0Xide) 14. Immediately afterwards, polycrystalline silicon 16 having a thickness of about 2000 to 3000 angstroms is deposited by a low pressure chemical vapor deposition method on the surface of the free oxygen layer 14, and high-intensity phosphorus or Arsenic 'doped into the newly deposited polycrystalline silicon wafer to reduce the resistivity of the gate: Furthermore,' a layer of nitride was deposited by low pressure chemical vapor deposition (LPCVD); May 18 on polycrystalline silicon layer 16 'has a thickness of about 1 00 to 2000 Angstroms. Next, a layer of photoresist is deposited on the silicon nitride 18, and a partial exposure is performed by using an I-line ([Une]) stepper, so that the pattern on the photomask is completely transferred to Photoresist, and then development of photoresist. … The third figure shows that silicon nitride is etched by dry etching and then the photoresist is removed. Next, a chemical vapor deposition (CVI) method is used to deposit titanium nitride with a thickness of about 1,000 to 2000 angstroms to form a layer of titanium nitride 22 on the surface of the nitride, 18 and polycrystalline silicon 16. Titanium 22 thin can be more than 90% of its step coverage.

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413853 V. Description of the invention (8) '一 · ~ The fourth figure shows that titanium nitride 22 is carved into a two-sided gap wall 22A by anisotropic etching. The present invention can define the size of the gate electrode by controlling the thickness of the titanium nitride and the size of the two side walls. The fifth figure shows: depositing a layer of metal thin film by magnetron DC hidden plating, with a thickness of about 200 to 1,000 angstroms, and then using a high temperature of about 60 (rc to 800 ° C, in an environment containing nitrogen or ammonia In the reaction, a part of the deposited titanium film is reacted with polycrystalline silicon on the gate electrode to form titanium silicide, and the remaining silicon that has not participated in the reaction or after the reaction will be nitrided to a nitrided thickness 26, which has a thickness of about 500 to 1,500 angstroms. The sixth figure shows: RCA-1 cleaning method using chemical cleaning solutions to remove nitric acid 26, 22A 'The RCA-1 cleaning method is by Nh4〇h _ · jj2 〇2 · 4〇 = 1 ·· j: 5 composition and then 'wet silicon nitride 18 yuan by wet-etching method. The seventh figure shows: using titanium silicide 24 as an etching mask, using automatic Aligned reactive ion etching (self_al ign RIE) etches polycrystalline silicon 16 to form a gate structure. Then '6 A gate mask is used, and phosphorus (_ is used as an ion source to perform phosphorus ionization on the entire wafer) Implantation. Its concentration is about 丄 〇u, / cm2 'is mainly used as an anti-short channel effect (sh〇r t channel effect) occurs in lightly doped drain (11 buckle 1; 1 yrain) 28 'is called N implantation. Next, the lightly doped drain electrode 2 8 is implanted into the heat The inside of the diffusion furnace is scaled at a high temperature of about 900 to 1,000 ° C.

413853

5. Description of the invention (9) Atomic diffusion. At the same time, the silicon atomic structure on the surface of the chip that was destroyed by ion implantation was annealed. The eighth figure is not shown. Using low pressure chemical vapor deposition (L p c V D), a layer of silicon nitride is stacked on the wafer to a thickness of about 100 to 2000 angstroms. Then, the silicon nitride is etched by anisotropic etching to form a gate electrode! Spacer 32 on the side wall of 6A. Using phosphorous or arsenic as the ion source, the wafer is implanted with high-latency and deep-depth ions to 'heavy doping' the source 3 0 A and the drain 3 0 B at a concentration of about 1015 / cm2, Called N + implantation. Furthermore, a layer of inter-layer die material 34 is deposited by chemical vapor deposition (CVD), and a comprehensive planarization of the inner layer dielectric material is performed by chemical mechanical polishing. Then, using the lithography and etching processes, the position of the contact window 36 is defined, and the contact window 3 is engraved in an anisotropic narrative manner 3. Next, a titanium (Ti) metal layer is deposited by metal sputtering as a barrier Uyer for subsequent wires. Finally, using a high temperature, a part of the deposited titanium film is reacted with silicon on the contact window 36 to form silicon titanate. The silicon silicide formed on the contact window 36 is the metal silicide of the source 38 and the drain 38B. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; Other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the scope of the following patent applications.

Claims (1)

413853 6. Application Patent Scope 1. A semiconductor device fabrication method, which includes at least the following steps: forming a field oxide in a semiconductor substrate; sequentially forming a gate oxide layer and a polycrystalline silicon Forming a first dielectric layer over the polycrystalline silicon layer; forming a photoresist layer over the first dielectric layer, and the photoresist used to define a gate position; The resist layer and the local first dielectric form a second dielectric layer on the first dielectric layer and the polycrystalline silicon layer. The optical layer is engraved with an anisotropic engraving method; Fang Cheng'er: ϊ, etc. The second dielectric layer is oriented in an isotropic manner, and a metal silicide is formed on the polycrystalline silicon layer to form a metal layer on the first dielectric layer and the gate positions of the two; above the paste; the gap wall And the gate gold silver engraving method: the third dielectric layer, the two side gap walls and the first dielectric layer; and using an anisotropic engraving method to engrav the polycrystalline stone layer, and the polycrystalline sand layer system Gate structure used as a semiconductor element_ 2 · The above-mentioned first dielectric layer in the method for manufacturing a semiconductor device described in item 1 of the scope of patent application includes at least a nitrided hair. 413853 6. Scope of patent application 3. The manufacturing method of the π-shaped piece of Fengcong conductor attacked by Lombe as described in item 1 of the scope of patent application, wherein the second dielectric layer includes at least the titanium nitride method, and t The above-mentioned gate layer in the semiconductor described in item! _ Includes at least a polycrystalline silicon layer. 6. The field oxide layer described above in the manufacture of semiconductor elements described in item 1 of the scope of patent application contains at least silicon dioxide. 'It 7. — A semiconductor device method including at least the following steps to form a field oxide substrate; sequentially forming a gate oxide layer and a polycrystalline silicon layer on the surface of the silicon substrate; forming a first silicon nitride Over the polycrystalline silicon layer; forming a photoresist-layer over the first silicon nitride; and the photoresist layer is used to define the position of the **-metal gate; the photoresist layer is etched by anisotropic etching And a local first nitrided sand layer; forming a first titanium nitride layer on the first gasified stone and polycrystalline stone layer by using an anisotropic etching method to etch the first nitride layer; shape Page 14 413853 6. The scope of the patent application is two side gap walls; a metal hairpin is formed on the metal gate position above the polycrystalline silicon layer; a second titanium nitride layer is formed on the first titanium nitride layer; and two side gaps are formed. Above the wall and metal gate; The second titanium nitride layer, the two side walls and the first titanium nitride layer are etched by a wet etching method; the polycrystalline silicon layer is etched by an anisotropic etching method, and the polycrystalline silicon layer is used as a metal gate of a semiconductor device. Electrode structure; forming two shallowly doped drain electrodes between the field oxide layer and the metal gate; forming a second silicon nitride layer on the field oxide layer, above the shallowly doped drain electrode and around the metal gate; The second silicon nitride layer is etched by using an anisotropic etching method to form a spacer on the side wall of the metal gate; a heavy doping is formed in a shallowly doped drain region; As a source / drain of the semiconductor element; forming an inter-layer dielectrics on the Above the semiconductor substrate, and the metal gate gap wall and the field oxide are engraved with a contact window; and 9Ί M forms a metal silicide above the contact window for use as a metallization method.... In the method for manufacturing a semiconductor device according to the seventh item, the above-mentioned gate is prepared by a thermal diffusion method. ''its 413853 6. Scope of patent application 9. The method for manufacturing a semiconductor device as described in item 7 of the scope of patent application, wherein the above-mentioned gate includes at least one of the following: polycrystalline silicon, phosphorus, arsenic, and silicide I 0, as in the scope of patent application No. 7 In the semiconductor device manufacturing method, the etching of the polycrystalline silicon described in f is made by self-align reactive ion etch. II. The method of manufacturing a semiconductor device according to item 7 of the scope of the patent application, wherein the spacers include at least silicon nitride. &, 1 2. According to the semiconductor device manufacturer's request described in item 7 of the scope of patent application, the above-mentioned spacers include at least silicon dioxide. ≫ 13_ The contact window above the source / drain electrode as described in the semiconductor device manufacturing side electrode described in item 7 of the scope of patent application is used as a filter / wave metal silicide. Therefore, the above-mentioned metal silicide in the semiconductor device manufacturer w described in item 7 of the scope of patent application includes at least titanium metal. 15. The method for manufacturing a semiconductor device according to item 7 of the patent application park mentioned above, the above metal silicide contains at least a starting metal. 页 Page 16 413853 VI. Patent Application Fanyuan1 6. According to the method of manufacturing a semiconductor element described in item 7 of the scope of patent application, the above-mentioned metal silicide above the open electrode should be deposited by sputtering & film The titanium film reacts with the above-mentioned polycrystalline silicon of the gate electrode to form a titanium bite, and removes the remaining titanium that is not involved in the reaction or the reaction by wet etching. 17 · The method for manufacturing a semiconductor device according to item 7 of the scope of the patent application, wherein the above-mentioned metal silicide 'above the contact window should be a titanium film deposited by a sputtering method, and the titanium film reacts with the aforementioned closed-end polycrystalline silicon. , Forming the dream of Qinhua. Remuneration 笫 17