JPH09199717A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress time fine-line effect of a silicide and to optimize the concentrations of impurities implanted into a gate and a diffusion layer by implanting impurities of specific concentrations selectively into a one conductivity type semiconductor substrate and a second polysilicon layer silicide and forming diffusion layers as a source and a drain, along with a gate electrode. SOLUTION: In an ion implanting process for forming a first shallow diffusion layer, impurities are implanted into portions 180 and 185 to be a source and a drain, and impurities are also implanted into a nondoped polysilicon 108 simultaneously. On this occasion, the doped quality of the implanted impurotoes is about 3.0 E14cm<2> , so the impurity concentrations of the undoped polysilicon 108 and the parts 180 and 185 to be a source and a drain after the implantation do not exceed 1.0 E18cm<-3> , so a fine-line effect is not produced even if a silicide is formed. Besides, it becomes possible to suppress the fine-line effect which increases the sheet resistance of a silicide, since a silicde is formed on the nondoped polysilicon layer 108.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using a silicide formation technique.

[0002]

2. Description of the Related Art Polysilicon is generally used as an electrode material for gate, source and drain electrodes of semiconductor devices. However, as power consumption and speed of semiconductor devices have increased in recent years, a laminated structure of a refractory metal silicide having a lower resistivity than polysilicon (hereinafter simply referred to as silicide) and polysilicon has come to be used. . FIG. 2A to FIG. 2E show a manufacturing process of a semiconductor device having an LDD structure using a conventional silicide formation technique.

As shown in FIG. 2A, an element isolation insulating film 201 is formed on a P-type silicon substrate 200 by a normal LOCOS method, and a gate insulating film is formed on the P-type silicon substrate 200 by a thermal oxidation method. Then, 202 is formed, and a polysilicon layer 203 containing no impurities (hereinafter referred to as non-doped polysilicon) is formed.

Next, as shown in FIG. 2B, the non-doped polysilicon layer 20 in the state of FIG.
3 is coated with a resist, a mask is placed on the resist, exposed and patterned, and then the non-doped polysilicon layer 203 is selectively etched.

Next, as shown in FIG. 2C, in the state of FIG. 2B, the non-doped polysilicon layer 2 is formed.
03 and inter-element isolation insulating film 201 as a mask, arsenic is implanted to form a shallow first diffusion layer 204 used as a source and a drain in a self-aligned manner, and then silicon nitride is deposited on the entire surface of the element, The sidewall 205 is formed by anisotropically etching the silicon nitride.

Next, as shown in FIG. 2 (d), in the state of FIG. 2 (c), the portion 2 to be the source and drain regions is formed.
The gate insulating film of 80 and 285 is removed, and P of that part is removed.
The type semiconductor substrate is exposed, a refractory metal is deposited on the entire surface of the semiconductor element, and heat treatment is performed to form the surface 280 of the non-doped polysilicon layer 203 and the exposed portions 280 to be the source and drain regions of the P type silicon substrate. And 28
After the silicides 206 and 216 are selectively formed at 5, the unreacted refractory metal is removed by etching.

Next, as shown in FIG. 2E, phosphorus is implanted into the polysilicon layer 203 in which silicide is formed by using the element isolation insulating film 201 and the sidewall 205 as a mask, and at the same time, the exposed P is exposed. Phosphorus is also implanted into the portions 280 and 285 that will be the source and drain regions of the silicon substrate to form the second diffusion layer 207 that will be the source and drain in a self-aligned manner. As described above, the semiconductor element using the silicide technique is formed.

Usually, when a silicide is formed on a polysilicon surface containing a high concentration of impurities having an impurity concentration of 1.0E18 cm -3 or more, a thin line effect occurs in which the sheet resistance of the silicide increases. However, since the silicide is formed on the non-doped polysilicon layer 203 in this manufacturing method, the thin line effect can be suppressed.

However, when the polysilicon 203 is used as a gate electrode and a voltage is applied, silicide is formed on the surface of the polysilicon 203 in order to suppress a depletion phenomenon in which a depletion layer is formed on the gate insulating film side. It is necessary to implant impurities into the formed polysilicon 203.
In FIG. 2 (e), the concentration of the impurity required to suppress the depletion phenomenon is usually about 100 times higher than the concentration of the impurity required to form the second diffusion layer 207. Therefore, when the optimum impurity implantation is performed to form the second diffusion layer 207, the polysilicon layer 20
Impurities having a concentration necessary to suppress the depletion phenomenon of No. 3 are not implanted into the polysilicon 203. On the contrary, an impurity having a concentration necessary for suppressing the depletion phenomenon is added to the polysilicon 203.
In the case of being implanted into the second diffusion layer 207, the concentration is too high for forming the second diffusion layer 207, so that the second diffusion layer 207 becomes deep, resulting in a decrease in the threshold voltage of the semiconductor element.

In the semiconductor device manufactured as described above, the thin line effect of increasing the sheet resistance of silicide can be suppressed, but it is difficult to optimize the impurity concentrations of the polysilicon 203 and the second diffusion layer 207.

Further, in this manufacturing method, the polysilicon layer 20 is used.
3 contains no impurities, the polysilicon layer 20
The impurity concentration contained in 3 is 0.0 or more and 1.0E18 cm
If it is less than -3, the thin line effect can be suppressed in the same manner as described above, but the polysilicon layer 203 and the second diffusion layer 20 can be suppressed.
It is difficult to optimize the impurity concentration of No. 7.

Next, FIGS. 3A to 3E show steps of manufacturing a semiconductor device having an LDD structure using a silicide forming technique different from the above manufacturing method. As shown in FIG. 3A, an element isolation insulating film 301 is formed on a P-type silicon substrate 300 by a normal LOCOS method, and a gate insulating film 302 is formed on the P-type silicon substrate 300 by a thermal oxidation method. However, the impurity concentration on the semiconductor element surface is 1.0E18 cm.
A polysilicon (hereinafter referred to as doped polysilicon) layer 303 containing impurities at a high concentration of −3 is formed.

Steps (b) to (e) of FIG. 3 are exactly the same as the steps (b) to (e) of FIG. In FIG. 3E, impurities are implanted so that the impurity concentration of the diffusion layer 307 used as the source and the drain is optimum. At this time, since the doped polysilicon 303 having silicide formed on its surface already contains impurities, the impurity implantation into the doped polysilicon 303 is auxiliary implantation. Therefore, by using this manufacturing process, the impurity concentrations of the polysilicon 303 and the second diffusion layer 307 can be optimized.

However, in this manufacturing method, since silicide is formed on the upper surface of the polysilicon 303 containing a high concentration of impurities, a thin line effect that increases the sheet resistance of the silicide occurs.

[0015]

As described above, when the silicide is formed on the surface of the undoped polysilicon which becomes the gate electrode, the thin line effect which increases the sheet resistance of the silicide can be suppressed, but the polysilicon which becomes the gate and It is difficult to perform the impurity implantation with the optimum concentration on both the substrate to be the diffusion layer.

On the other hand, when silicide is formed on the surface of the heavily doped polysilicon that becomes the gate electrode, it becomes possible to perform the impurity implantation with the optimum concentration in both the polysilicon that becomes the gate and the substrate that becomes the diffusion layer. However, if silicide is formed on the upper surface of the doped polysilicon, it becomes difficult to suppress the thin line effect that increases the sheet resistance of the silicide.

The present invention suppresses the thin line effect of silicide as described above, and manufactures a semiconductor device for optimizing the concentration of impurities to be implanted into both polysilicon to be a gate and a substrate to be a diffusion layer. The purpose is to provide a method.

[0018]

In order to achieve the above object, the present invention forms a first polysilicon layer containing impurities on a gate insulating film formed on a semiconductor substrate of one conductivity type. Forming a second polysilicon layer containing no impurities on the first polysilicon layer, applying a resist on the second polysilicon layer, and placing a mask on the resist. A step of exposing, patterning, and selectively removing the first and second polysilicon layers and the gate insulating film, and one conductivity type semiconductor substrate of all and exposed portions of the second polysilicon layer. At the same time as the gate electrode by selectively forming impurities on the surface, and selectively implanting impurities into the silicided second polysilicon layer and the exposed one-conductivity-type semiconductor substrate, Characterized in that it has a forming step diffusion layer used as the over scan and drain.

According to the present invention, since the second non-doped polysilicon layer is formed on the first doped polysilicon layer, even if a silicide is formed on the second non-doped polysilicon layer, the silicide is formed. The thin line effect that increases the sheet resistance of does not occur.

Impurities of opposite conductivity type are implanted so that the impurity concentration of the diffusion layers used as the source and the drain is optimized. At this time, since the polysilicon that will be the gate electrode already contains impurities, it is possible to inject the impurity with an optimum concentration in both the diffusion layer used as the source and drain and the polysilicon used as the gate.

Further, the polysilicon layer serving as the gate electrode does not have to be two layers, and is composed of a multilayer including at least one polysilicon layer containing high-concentration impurities, and the uppermost layer thereof contains impurities. Even if the polysilicon layer is not formed, the same effect as described above can be obtained. Further, even when the uppermost polysilicon layer contains impurities of less than 1.0E18 cm −3, the thin line effect can be suppressed, so that the same effect as described above can be obtained.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device manufacturing process of the present invention is shown in FIGS. As shown in FIG. 1A, an element isolation insulating film 101 is formed on a P-type semiconductor substrate 100 by a normal LOCOS method,
A gate insulating film 102 having a thickness of 6 nm is formed on the P-type semiconductor substrate by a thermal oxidation method.

Next, as shown in FIG. 1B, in the state of FIG. 1A, the impurity concentration on the surface of the device is 1.0E18.
A polysilicon layer 103 containing impurities of cm −3 or more is deposited to a thickness of 200 nm. The impurity-containing polysilicon layer 103 is formed by depositing an impurity-free polysilicon layer and then introducing phosphorus, which is an impurity, into the impurity-free polysilicon layer by a phosphorus diffusion method. To be done. Further, the introduction of the impurities is performed by ion implantation, vapor layer diffusion, solid layer diffusion, in-situ-dope.
It may also be performed by d deposition or the like. Also, the doped polysilicon layer 103 may be a multilayer instead of a single layer.

Next, as shown in FIG. 1C, on the doped polysilicon layer 103 in the state of FIG. 1B,
The non-doped polysilicon layer 108 is formed to a thickness of 100 nm. The non-doped polysilicon layer 103 is 0.0
It may contain impurities of cm-3 or more and less than 1.0E18 cm-3.

Next, as shown in FIG. 1D, a resist is applied on the undoped polysilicon layer 108,
After placing a mask on it, exposing and patterning,
Non-doped polysilicon layer 1 using the resist as a mask
After the 08 and the doped polysilicon layer 103 are selectively etched, the resist is peeled off to form a gate electrode.

Next, as shown in FIG.
From the state of (d) of FIG. 3, arsenic is implanted with an energy of 50 with the gate portion 190 and the element isolation insulating film 101 as a mask.
After the impurity is implanted through the gate insulating film 102 by the ion implantation method under the conditions of Kev and the dose amount of 3.0E14 cm −2, the shallow first diffusion layer 104 used as the source and the drain is formed in a self-aligned manner. Sidewalls 105 are formed by depositing silicon nitride over the entire surface of the device and isotropically etching the silicon nitride.

Next, as shown in FIG.
In the state (e), the gate insulating films of the portions 180 and 185 to be the source and the drain are selectively removed by immersing the semiconductor element in an HF-based etching solution, so that the entire surface of the semiconductor element is highly etched. The melting point metal Ti is deposited to a thickness of 50 nm by a sputtering method, and a heat treatment is performed to expose the entire non-doped polysilicon layer 108 and the P-type semiconductor substrate.
After selectively forming silicides 106 and 116 at 85, unreacted Ti is removed. The refractory metal is C
It may be o, Ni, Mo, Zr, Hf, Ta, Pd, Pt, W or the like.

Next, as shown in FIG.
In the state (f) of FIG.
05 and the element isolation insulating film 101 are used as a mask to implant impurities to form a second diffusion layer 107 serving as a source and a drain. This impurity implantation is carried out by the ion implantation method under the conditions of phosphorus as the implantation impurity, implantation energy of 60 Kev, and dose amount of 7.0E15 cm −2. In this case, since the polysilicon layer 103 contains impurities in advance, the polysilicon layer 103 is an auxiliary implant. As described above, the semiconductor element is formed by using the manufacturing method of the present invention.

In the ion implantation process for forming the first shallow diffusion layer in FIG. 1E, impurities are implanted into the portions 180 and 185 to be the source and drain, and at the same time, the undoped polysilicon 108 is also implanted. Impurities are injected. In this case, the dose of implanted impurities is 3.
Since it is about 0E14 cm −2, the non-doped polysilicon 180 after implantation and the portion 18 to be the source and drain
Since the impurity concentrations of 0 and 185 do not exceed 1.0E18 cm −3, the thin line effect does not occur even if silicide is formed in the relevant portion.

In the step of FIG. 1F, the case where all of the non-doped polysilicon layer 108 is silicidized is shown. However, when only the upper surface of the non-doped polysilicon layer 108 is silicidized, or all of it is silicided. And underlying doped polysilicon layer 10
It is possible that the upper surface of 3 is silicided. When only the upper surface of the non-doped polysilicon layer 108 is silicidized, the heat treatment after this step causes the impurities contained in the doped polysilicon layer 103 and the Ti contained in the silicide portion 116 to react with the non-doped polysilicon layer. And the unreacted undoped polysilicon layer is silicided or doped polysilicon.
Therefore, in any of the above cases, the unreacted non-doped polysilicon layer is completely silicified or doped polysilicon after the completion of this manufacturing process. Further, although the manufacturing process of the semiconductor device having the LDD structure is assumed in the present embodiment, the semiconductor device may be a manufacturing process such as a CMOS or a non-volatile semiconductor device.

In this manufacturing method, since the silicide is formed on the non-doped polysilicon layer 108, the thin line effect of increasing the sheet resistance of the silicide can be suppressed. Further, since the polysilicon to be the gate before forming the second diffusion layer 107 contains impurities in advance, depletion of the gate electrode can be suppressed, and the gate made of the second diffusion layer 107 and the polysilicon. The impurity concentration of the electrodes can be optimized at the same time.

The polysilicon layer serving as the gate electrode does not have to have two layers, and may have a three-layer structure. For example, the lowermost first layer is a polysilicon layer containing no impurities,
The second layer thereover may be a polysilicon layer containing a high concentration of impurities, and the uppermost layer thereover may be a polysilicon layer containing no impurities. That is, the same effect as described above is obtained even if the polysilicon layer to be the gate electrode is a multilayer including at least one polysilicon layer containing high-concentration impurities and the topmost polysilicon layer does not contain impurities. Is obtained. In addition, the uppermost polysilicon is 1.0E18c
Even if it contains impurities less than m-3, the thin line effect can be suppressed, and the same effect as described above can be obtained.

[0033]

Since the present invention is configured as described above, it is possible to suppress the thin line effect of silicide and optimize the concentration of impurities to be implanted into both polysilicon to be a gate and a substrate to be a diffusion layer. You can do it.

[Brief description of drawings]

FIG. 1 is a process drawing of an embodiment using the manufacturing method of the present invention.

FIG. 2 is a process chart of an embodiment using a conventional manufacturing method.

FIG. 3 is a process chart of an embodiment using a conventional manufacturing method.

[Explanation of symbols]

100, 200, 300 P-type semiconductor substrate 101, 201, 301 Element isolation insulating film 102, 202, 302 Gate insulating film 103, 203, 303 Polysilicon layer containing no impurities 104, 204, 304 Shallow first diffusion layer 105, 205, 305 Sidewalls 106, 116, 206, 216, 306, 316 Silicide portions 107, 207, 307 Diffusion layers 180 and 185, 280, 285, 380, 385 Source and drain portions 108 Impurities Polysilicon layer including gate 190 Gate part

Claims (3)

[Claims] 1. A first polysilicon layer containing an impurity having an impurity concentration of 1.0E18 cm −3 or more is formed on an insulating film formed on a semiconductor substrate of one conductivity type, and the first polysilicon layer is formed. A step of forming a second polysilicon layer containing no impurities on the top, applying a resist on the second polysilicon layer, patterning by a lithography method, using the patterned resist as a mask, After selectively removing the first and second polysilicon layers, a step of forming a gate electrode composed of the first and second polysilicon layers, and peeling the resist,
Forming sidewalls on both sides of the gate electrode; removing an insulating film on a portion where the sidewalls and the gate electrode are not formed to expose a surface of the first conductivity type semiconductor substrate; A high melting point metal film is formed on the upper surface and side surfaces of the gate electrode and on the upper surface and side surfaces of the gate electrode, and heat treatment is performed, thereby forming a high temperature on at least the surface of the second polysilicon layer and the surface of the exposed one conductivity type semiconductor substrate. A step of selectively forming a melting point metal silicide and then removing an unreacted refractory metal, and selectively implanting an impurity of opposite conductivity type into at least the exposed surface of the one conductivity type semiconductor substrate to form a source and a drain. And a step of forming a diffusion layer to be used, the method for manufacturing a semiconductor device. 2. A first polysilicon layer containing an impurity having an impurity concentration of 1.0E18 cm −3 or more is formed on an insulating film formed on a semiconductor substrate of one conductivity type, and the first polysilicon layer of the first polysilicon layer is formed. Impurity concentration above 0.0 cm-3 1.0E18
a step of forming a second polysilicon layer containing impurities of less than cm −3, applying a resist on the second polysilicon layer, patterning by a lithography method, and using the patterned resist as a mask ,
After selectively removing the first and second polysilicon layers, a step of forming a gate electrode composed of the first and second polysilicon layers, and removing the resist, on both sides of the gate electrode A step of forming a side wall, removing the insulating film on the side wall and a portion where the gate electrode is not formed,
Exposing the surface of the first conductivity type semiconductor substrate, and forming a refractory metal film on the exposed surface of the first conductivity type semiconductor substrate and on the upper surface and the side surface of the gate electrode, and performing a heat treatment, Removing at least the unreacted refractory metal after selectively forming a refractory metal silicide on at least the surface of the polysilicon layer and the exposed surface of the one conductivity type semiconductor substrate, and at least the exposed one conductivity type semiconductor substrate. And a step of selectively implanting impurities of opposite conductivity type to form a diffusion layer used as a source and a drain. 3. A first layer comprising a plurality of layers including at least one polysilicon layer containing an impurity having an impurity concentration of 1.0E18 cm −3 or more on a gate insulating film formed on a semiconductor substrate of one conductivity type. And a step of forming a second polysilicon layer containing no impurities on the polysilicon layer composed of the plurality of layers, and a resist on the second polysilicon layer. After coating and patterning, using the patterned resist as a mask, after selectively removing the first polysilicon layer composed of the second polysilicon layer and the plurality of layers,
Forming a gate electrode composed of a polysilicon layer composed of the plurality of layers and a polysilicon layer containing no impurities in the uppermost layer; and removing the resist to form sidewalls on both sides of the gate electrode. A step of removing the insulating film on the side wall and the portion where the gate electrode is not placed to expose the surface of the one-conduction-type semiconductor substrate; and the exposed one-conduction-type semiconductor substrate and the top and side surfaces of the gate electrode. An unreacted refractory metal is formed after a refractory metal silicide is selectively formed on at least the surface of the second polysilicon layer and the exposed one-conductivity-type semiconductor substrate surface by forming a refractory metal film and performing heat treatment. The step of removing
And a step of selectively implanting an impurity of opposite conductivity type into at least the exposed surface of the semiconductor substrate of one conductivity type to form a diffusion layer used as a source and a drain.