KR100372634B1 - Salicide type transistor in a semiconductor device and fabricating method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a salicide structure transistor of a semiconductor device and a method of manufacturing the same. In particular, in a MOS transistor having a polyside structure, a gate polysilicon is formed of a laminate of impurity doped polysilicon and undoped polysilicon Small concentrations of impurity diffusion regions are formed after salicide completion, so that impurity ions do not interfere with silicide formation, and thus, silicides or salicides are stably formed by reaction of the silicide-forming metal with undoped polysilicon to improve transistor performance. It relates to a silicide of a semiconductor device and a method of manufacturing the same. The salicide structure transistor of the semiconductor device according to the present invention runs long in the first direction on the surface of the central region of the active region of the first conductivity type semiconductor substrate and is doped on the first polysilicon layer doped with impurity ions for ensuring conductivity. A gate electrode having a laminated structure consisting of a second polysilicon layer, a gate insulating film interposed between the first polysilicon layer and the substrate, and a first silicide layer positioned on an upper surface of the second polysilicon layer of the laminated gate And a gate sidewall spacer comprising an insulating film positioned on a side of the first silicide layer / second polysilicon layer / first polysilicon layer / gate insulating film, and overlapping the gate electrode edge and the sidewall spacer. A lightly doped region doped with a second conductivity type impurity formed on a substrate, and the lightly doped region And a high concentration doped region, which is doped with a region and doped with a second conductivity type impurity formed in the substrate active region outside the gate electrode, and a second silicide layer covering an upper surface of the high concentration doped region.

Description

Salicide type transistor in a semiconductor device and fabricating method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a salicide structure transistor of a semiconductor device. In particular, in a MOS transistor having a polyside structure, a gate polysilicon is formed as a laminate of impurity doped polysilicon and undoped polysilicon and has a small concentration. The impurity diffusion region is formed after the completion of the salicide so that the impurity ions do not interfere with the formation of the silicide, and thus the silicide or salicide is stably formed by the reaction of the silicide-forming metal with the undoped polysilicon to improve the performance of the transistor. A method for manufacturing a silicide structure transistor of a semiconductor device.

As semiconductor devices are highly integrated, the widths of impurity regions and gates used as source and drain regions are reduced. Accordingly, the semiconductor device has a problem in that an operating speed decreases due to an increase in the contact resistance of the impurity region and the sheet resistance of the gate.

Therefore, when the wirings of the elements in the semiconductor device are formed of a low resistance material such as aluminum alloy and tungsten, or when the gate electrode is formed of polysilicon, a silicide layer is formed to reduce the resistance. When the silicide layer is formed on the gate formed of polysilicon, a silicide layer is also formed on the surface of the impurity region to reduce the contact resistance.

As described above, as the design rules of the semiconductor devices become more stringent, high sheet resistance at the gate becomes a major cause of lowering the operation speed of the devices. Therefore, fabrication of the low resistance gate electrode is essential for improving the device operation speed. In order to improve the resistance, a gate electrode having a silicide (refractory metal silicide) formed of a heat resistant metal having a low specific resistance is manufactured. The gate electrode having such a structure is called a polycide (silicide on doped polycrystalline silicon) gate electrode.

In addition, a structure or a technique of simultaneously forming a polyside reducing gate resistance and a silicide for reducing contact resistance in an impurity diffusion region of a substrate in a self-aligning manner is called salicide.

WSi ₂ is most widely used to form polyside structures, but as the integration of devices increases and the area occupied by unit devices decreases, formation of silicides having lower resistance values is required. At this time, the specific resistance value of WSi2 is 60-200 micrometer-cm. CoSi ₂ and TiSi ₂ which are the most potent silicides meeting these demands, their specific resistance values are 15 to 20 mu Ω-cm.

The method of forming a polyside structure can be broadly divided into two methods.

First, a metal layer is deposited on a conductive doped polysilicon layer and then heat-treated to form silicide by reaction of metal and silicon. However, the silicide of the metal-silicon formed at this time is difficult to form a silicide layer having a thick and uniform thickness.

In general, the reaction between pure metal and silicon is very violent, so that the interfacial morphology of silicide and silicon becomes rough, which makes it difficult to accurately pattern the gate electrode. In this regard, J.S. Byun et al. J. Electrochem. Soc., Vol. 144,3175 (1997)] dp.

In addition, since highly doped polysilicon and metal react, it is difficult to form uniform silicide due to the high concentration of dopant.

Second, there is a method of depositing a silicide material directly on a conductive doped polysilicon layer instead of a thermal process. In general, a silicide layer is directly formed on a polysilicon layer doped by a sputtering method using a silicide composite target. However, this method generates particles upon silicide formation. That is, since the sputtering rate of each element is different in the composite target composed of two components, metal and silicon, it is difficult to deposit silicide of uniform composition and generate particles.

1A to 1E are cross-sectional views illustrating a method of manufacturing a salicide structure transistor of a semiconductor device according to the related art.

Referring to FIG. 1A, a field oxide film 11 is formed on a predetermined portion of a silicon substrate 10, which is a semiconductor substrate, by a device isolation method such as a local oxide of silicon (LOCOS) or shallow trench isolation (STI) method. The active region and the device isolation region are formed.

The surface of the semiconductor substrate 10 is thermally oxidized to form an oxide film as the gate insulating film.

Next, an in-situ doped polycrystalline silicon is formed by chemical vapor deposition on the gate oxide layer to form a gate electrode, or an undoped polysilicon layer is undoped. polycrystalline silicon) is deposited by chemical vapor deposition and then doped by ion implantation. The polysilicon layer doped with impurity ions forming the predetermined conductive type thus formed is patterned in a subsequent process to form a lower structure of the gate electrode. In this case, the deposited polysilicon layer is formed to a thickness obtained by subtracting the thickness of the silicide layer to be formed in consideration of the height of the entire gate electrode.

The doped polysilicon layer and the oxide film are sequentially patterned by photolithography to form a gate electrode 13 and a gate insulating film 12 including the remaining polysilicon layer 13 and the oxide film 12.

Next, a low concentration impurity doped region 14 for a lighrly doped drain (LDD) source / drain is formed in the active region of the substrate on which the gate 13 is not formed by a suitable conductivity type low concentration impurity ion implantation.

Referring to FIG. 1B, an oxide film having a predetermined thickness is deposited on the entire surface of the substrate 10 including the gate electrode 13 by chemical vapor deposition. At this time, the oxide film insulates the side surface of the gate electrode 13 and is used for forming sidewall spacers used as part of an ion implantation mask for forming a highly doped impurity doped region when forming a transistor having an LDD structure.

Next, an oxide film is etched back to form a sidewall spacer 15 made of an oxide film remaining on the side surface of the gate electrode 13. At this time, the etch back is performed by anisotropic etching such as dry etching until the impurity doped region of the substrate and the upper surface of the gate electrode 13 are simultaneously exposed.

Thus, the upper surface of the exposed gate electrode 13 becomes a silicide formation region.

In the LDD structure, the transistor is formed using an ion implantation using the gate electrode 13 and the sidewall spacer 15 as an ion implantation mask at a high concentration to expose the active region of the substrate exposed with the same conductivity type impurities used to form a low concentration impurity ion buried layer. A highly doped impurity doped region 16 is formed.

Referring to FIG. 1C, the silicide forming metal layer 17 is formed on the entire surface of the substrate 10 including the active region in which the exposed high concentration impurity doped region 16 is formed and the exposed gate electrode 13 surface. At this time, the metal layer is formed of a metal capable of reacting with the silicon of the gate electrode 13 to form a silicide in the form of metal-silicon bond, Ti is used as the metal, and the deposition method uses sputtering. do. At this time, the formation thickness of the metal layer 17 is combined with the thickness of the gate electrode 13 so that the overall height conforms to the design rule of the gate electrode to be formed later.

Referring to FIG. 1D, a first rapid thermal annealing is performed on the gate electrode 13 and the impurity doped region 14 on which the metal layer 17 is formed at a low temperature of 650-750 ° C. to react Ti and Si. The first silicide layer 171 and the second silicide layer 172 for resistance reduction are simultaneously formed. At this time, the phases of the first and second silicide layers 171 and 172 become C49 TiSi ₂ .

Referring to FIG. 1E, a salicide structure is formed by wet etching a metal layer 170 remaining at a portion where the first silicide layer 171 and the second silicide layer 172 is not formed. To prepare a silicide layer. At this time, removal of the remaining metal layer is performed by selective wet etching with NH ₄ : H ₂ O ₂ : H ₂ O mixed solution.

Next, a second rapid heat treatment is performed to transform the phases of the first and second silicide layers 171 and 172 from C49 to C54. In this case, the second rapid heat treatment is performed at a relatively high temperature of 800-900 ° C. to form first and second silicide layers 171 ′ and 172 ′ transformed into a C54 phase.

As described above, the salicide structure MOS transistor according to the related art and a method of manufacturing the same have a high impurity surface concentration of a gate electrode made of a source / drain region surface and a doped polysilicon, and impurity ions prevent diffusion of silicon into titanium. This prevents the formation of TiSi ₂ smoothly. In particular, when the impurity ions are As ⁷⁵ or P ³¹ having a large atomic weight, the effect is maximized, and incomplete formation of silicide in polysilicon is intensified rather than single crystal silicon. Accordingly, there is a problem that silicide formation becomes unstable in the polysilicon gate and source / drain regions of the NMOS.

Accordingly, an object of the present invention is to form a gate polysilicon in a MOS transistor having a polyside structure by forming a stack of impurity doped polysilicon and undoped polysilicon and forming a small concentration impurity diffusion region after salicide completion. The present invention provides a method of manufacturing a silicide of a semiconductor device in which silicide or salicide is stably formed by reaction of a silicide-forming metal with undoped polysilicon so that ions do not interfere with silicide formation, thereby improving transistor performance. .

In order to achieve the above object, a method of manufacturing a salicide structure transistor of a semiconductor device according to an embodiment of the present invention includes an insulating film, a first polysilicon layer doped with impurities, and a second undoped second polysilicon layer on a first conductive semiconductor substrate. Forming and patterning a gate insulating film comprising the remaining insulating film and a lamination structure consisting of the remaining second and first polysilicon layers; Forming a low impurity doped region, forming sidewall spacers on both sides of the gate electrode, forming a silicide forming metal layer on the substrate including the gate electrode of the structure, and forming the metal layer and the second poly A first rapid heat treatment was performed on the silicon layer / low doping region at a temperature of 650-750 ° C. 1, forming a second silicide layer, removing the metal layer not participating in the reaction, and performing a second rapid heat treatment on the first and second silicide layers on C49 at a temperature of 800 to 900 ° C. And converting the phase into a phase, and forming a second conductivity type high concentration doped region in the resultant substrate using the gate electrode and the sidewall spacer as a mask.

1A to 1E are cross-sectional views illustrating a method of manufacturing a salicide structure transistor of a semiconductor device according to the related art.

2A to 2F are cross-sectional views illustrating a method of manufacturing a salicide structure transistor of a semiconductor device according to the present invention.

3 is a cross-sectional view of a salicide structure transistor of a semiconductor device according to the present invention.

As the line width of other gates decreases to submicrons due to high integration of semiconductor products, the sheet resistance at the gate contact portion increases. In order to reduce the sheet resistance, a gate electrode having a polyside structure for stably forming silicide on the upper surface of the gate is formed.

In addition, a silicide layer is also formed on the surface in order to reduce the contact resistance on the source / drain surface.

Thus, the formation of the silicide layer on the gate upper surface and the source / drain surface simultaneously by the self-aligning method is called salicide.

In the present invention, in order to solve the problems of the prior art, the gate is formed in a laminated structure consisting of a polysilicon layer doped at the bottom and an undoped polysilicon layer at the top, and a high concentration impurity diffusion region in the source / drain of the LDD structure The silicide layer is stably provided by preparing after forming the salicide layer.

In general, As, P, B, Ar, N2, Si, etc., which are used as ion implantation dopants, do not have a relatively large atomic radius as compared to Ti, and As, P, and B have a high bonding force with Ti, and thus Ti- Interfere with the formation of silicides (J. Appl. Phys. 66 (11), 1 December, 1989).

Therefore, in the present invention, such interference of impurity ions is essentially eliminated.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views illustrating a method of manufacturing a salicide structure transistor of a semiconductor device according to the present invention.

Referring to FIG. 2A, a field oxide film 21 is formed on a predetermined portion of a silicon substrate 20, which is a semiconductor substrate, by a device isolation method such as a local oxide of silicon (LOCOS) method or a shallow trench isolation (STI) method. The active region and the device isolation region are formed.

The surface of the semiconductor substrate 20 is thermally oxidized to form an oxide film as the gate insulating film.

Subsequently, a first polysilicon layer doped with n-type or p-type impurities on the gate oxide layer is deposited by chemical vapor deposition to form a gate electrode, or the first poly-doped The undoped polycrystalline silicon is deposited by chemical vapor deposition and then doped by ion implantation. The first polysilicon layer doped with impurity ions forming the predetermined conductive type thus formed is patterned in a subsequent process to form a substructure of the gate electrode. In this case, the first polysilicon layer to be deposited may be formed by subtracting the thickness of the silicide layer to be subsequently formed in consideration of the sum of the thickness of the second polysilicon layer and the height of the entire gate electrode.

In addition, an undoped polycrystalline silicon layer is formed by chemical vapor deposition on the first polysilicon layer doped with an impurity.

Accordingly, the first polysilicon layer and the second polysilicon layer on which the gate electrode is to be formed are stacked in this order.

Next, the second polysilicon layer 24 / first polysilicon layer 23 remaining after patterning the second undoped second polysilicon layer, the doped first polysilicon layer, and the oxide layer by photolithography is sequentially patterned. A gate electrode and a gate insulating film 22 are formed.

A low concentration impurity doped region 25 for a lighrly doped drain (LDD) source / drain is formed in an active region of a substrate on which a gate electrode is not formed by a suitable conductivity type low concentration impurity ion implantation.

Referring to FIG. 2B, an oxide film having a predetermined thickness is deposited on the entire surface of the substrate 20 including the gate electrode by chemical vapor deposition. At this time, the oxide film insulates the side surfaces of the gate electrodes composed of the second and first polysilicon layers 24 and 23 and is used as part of an ion implantation mask for forming a high concentration impurity doped region when forming a transistor having an LDD structure. For spacer formation.

Then, the oxide film is etched back to form a sidewall spacer 26 made of the oxide film remaining on the side of the gate electrode. At this time, the etch back is performed by anisotropic etching such as dry etching until the lightly doped impurity doped region 25 of the substrate and the upper surface of the gate electrode are simultaneously exposed.

Thus, the exposed top surface of the gate electrode then becomes a silicide or salicide forming region.

However, in the embodiment of the present invention, a high concentration impurity diffusion region for completing the source / drain of the LDD structure is formed in this step, but not in this step.

Referring to FIG. 2C, the silicide forming metal layer 27 is formed on the entire surface of the substrate 20 including the active region in which the exposed lightly doped impurity doped region 25 is formed and the exposed gate electrode surface 24. In this case, the metal layer may react with silicon of the undoped second polysilicon layer 24 of the gate electrode 23 to form silicides in which metal-silicon is bonded to Ti, Ni, W, Mo, Co, and Ta. Or a high melting point metal (refractorymetal) such as Pt. In an embodiment of the present invention, Ti is used as the metal, and the deposition method uses sputtering. At this time, the formation thickness of the metal layer 27 is combined with the thickness of the gate electrode so that the overall height conforms to the design rule of the gate electrode to be formed later.

Referring to FIG. 2D, a first rapid thermal annealing is performed on the upper surface of the gate electrode 240 on which the metal layer is formed and the low concentration impurity doping region 25 to react Ti and Si at a low temperature of 650-750 ° C. The first silicide layer 271 and the second silicide layer 272 for resistance reduction are simultaneously formed. In this case, the phases of the first and second silicide layers 271 and 272 become C49 TiSi ₂ , and the impurity concentrations of the low concentration impurity diffusion region 25 and the second polysilicon layer 24 are low or zero. The formation of the silicide is made stable.

Referring to FIG. 2E, a salicide structure is formed by wet etching the remaining metal layer 270 at a portion where the first silicide layer 271 and the second silicide layer 272 are not formed. The first and second silicide layers 271 and 272 remain. At this time, removal of the remaining metal layer is performed by selective wet etching with NH ₄ : H ₂ O ₂ : H ₂ O mixed solution.

Referring to FIG. 2F, a second rapid heat treatment is performed to transform the phases of the first and second silicide layers from C49 to C54. In this case, the second rapid heat treatment is performed at a relatively high temperature of 800-900 ° C. to form first and second silicide layers 271 ′ and 272 ′ transformed into a C54 phase.

In order to complete the LDD transistor, ion implantation using the gate electrode and the sidewall spacers 26 as an ion implantation mask is performed at high concentration with impurity ions of a predetermined conductivity type to form a low concentration impurity ion buried layer. A high concentration impurity doped region 26 is formed in the active region of the substrate exposed with impurities. At this time, the high concentration impurity doped region 26 partially overlaps the low concentration impurity doped region.

3 is a cross-sectional view of a salicide structure transistor of a semiconductor device according to the present invention.

Referring to FIG. 3, a field oxide film 21 defining a device active region and a field isolation region is formed on a silicon substrate 20, which is a first conductivity type semiconductor substrate.

On the surface of the center portion of the active region of the silicon substrate 20, a gate electrode having a lamination structure running in the first direction is formed, and the lamination structure of the gate electrode has a first polysilicon layer doped with impurity ions for securing conductivity in the lower portion thereof. 23 and a second polysilicon layer 240 undoped on the top.

A gate insulating film 22 made of an oxide film is interposed between the first polysilicon layer 23 and the substrate 20, and the first silicide layer 271 ′ is formed on an upper surface of the second polysilicon layer 240 of the multilayer gate. ) Is located.

Gate sidewall spacers 26 made of an insulating film such as an oxide film are formed on side surfaces of the first silicide layer 271 ′, the second polysilicon layer 240, the first polysilicon layer 23, and the gate insulating layer 22. have.

A lightly doped region 25 doped with a second conductivity type impurity is formed in the active region substrate so as to overlap the gate edge and the sidewall spacers 26. The substrate active region outside the gate forms a section with the lightly doped region 25. A heavily doped region 28 doped with a second conductivity type impurity is formed in the substrate.

The upper surface of the heavily doped region 28 is covered with a second silicide layer 272 '.

Accordingly, the present invention improves the performance of the transistor by stably forming silicide or salicide by reacting the silicide-forming metal with undoped polysilicon or low-doped region while preventing impurity ions from interfering with silicide formation. There is this.

Claims (8)

delete delete An insulating film, a first polysilicon layer doped with impurities, a second undoped second polysilicon layer are sequentially formed on the first conductive semiconductor substrate, and then patterned to form a gate insulating film comprising the remaining insulating film and the second, Forming a gate electrode having a laminated structure made of a first polysilicon layer, Forming a second conductivity type impurity low concentration doping region in the substrate at a lower side of the gate electrode; Forming sidewall spacers on both sides of the gate electrode; Forming a silicide forming metal layer on a substrate including the gate electrode of the structure; Forming first and second silicide layers on C49 by subjecting the metal layer and the second polysilicon layer / the low concentration doping region to a first rapid heat treatment at a temperature of 650-750 ° C .; Removing the metal layer not participating in the reaction; Converting the first and second silicide layers of the C49 phase into a C54 phase by performing a second rapid heat treatment at a temperature of 800-900 ° C .; And forming a second conductivity type high concentration doped region in the resulting substrate using the gate electrode and the sidewall spacers as a mask to form a section with the low concentration doped region in the resulting substrate. delete delete delete The method of claim 3, wherein the metal layer selectively forms any one of a high melting point metal such as Ti, Ni, W, Mo, Co, Ta, or Pt. The method of claim 3, wherein in the step of removing the metal layer, the metal layer that does not participate in the reaction is removed by selective wet etching.