TW501205B - Use of silicon germanium and other alloys as the replacement gate for the fabrication of MOSFET - Google Patents

Abstract

A method of fabricating a MOSFET is provided, including: depositing an oxide layer on a silicon substrate for device isolation; forming a silicon based alloy island above a gate region in the substrate, wherein the silicon based alloy comprises a silicon germanium alloy or a silicon tin alloy or another alloy of group IV-B elements; building a sidewall about the silicon based alloy island; forming a source region and a drain region in the substrate; removing the silicon based alloy island, thereby leaving a void over the gate region; filing the void and the areas over the source region and the drain region; and planarizing the upper surface of the structure by chemical mechanical polishing. Alternative embodiments providing conventional and raised source/drain structures are disclosed.

Description

501205 V. Description of the invention (l) Manmin's background and abstract This application is a continuation of the part of the serial number 009 / 〇28,157, which was filed on February 23, 1998, and the title is " Chemical mechanical polishing and replacement of nitrides to produce planar metal-oxide-semiconductor field-effect transistors π with raised source and drain, by David Russell Evans and Sheng Teng

Hsu invented. The present invention relates to the manufacture of integrated circuits, and in particular to the manufacture of metal oxide semiconductor field effect transistor devices using gate replacement. . Metal oxide semiconductors are well known. Such technology is shown in No. 4,702,792. The structure in the US patent owned by Chow et al. 'Discloses the replacement or "casting" process for making small-sized conductive channels is a good candidate method in which there are many gate materials to choose transistors. Because of the controllability of the process, this process is not widely used. Control of gate critical dimension.

Chatterjee et al. Wrote in the IEDM Technical Digest, page 77 ?, 1 988, that they replaced the gate process, specifically using polycrystalline silicon as the second material. The disadvantage of using polycrystalline silicon as a replacement gate material is the difficulty in removing polycrystalline silicon using a selective wet etching process using silicon compounds. '' A ¢ 1

Yagishita et al. Also in the IEDM Technical Digest, page 785, replace the gate process. Yagishita also revealed the use of 8 to 8 years' writing materials. Xi Xi Ri Shi Xi to replace the gate

Page 5 — 501205 91. 2. 2 6 _ Case No. 89120365 _ year month day __ 5. Description of the invention (2)

Evans et al., Filed a patent application serial number 09/028, 157, and filed on February 23, 1998. This application is part of a continuum that discloses the use of silicon nitride as a replacement gate material. The use of silicon nitride as a replacement gate material is effective, but the use of dry etch patterning silicon nitride to replace the gate can be difficult. To optimize dry silicon nitride etching, an etchant must be selected between silicon and silicon dioxide. To date, alloys of silicon germanium and other IV-B group elements have not been used as dummy or to replace gates during the fabrication of metal oxide semiconductor field effect transistor devices. It would be beneficial to have a replacement gate metal-oxide-semiconductor field-effect transistor manufacturing process and improved etch selectivity between replacement gate materials and for spacers and other structurally adjacent materials. Although the aforementioned references discuss the manufacture of metal oxide semiconductor field effect transistor devices, they do not provide the advantages of the present invention. An object of the present invention is to provide a method of manufacturing a metal oxide semiconductor field effect transistor device ', in which the source and drain regions are formed before the gate is formed. Another object of the present invention is to provide a metal-oxide-semiconductor field-effect transistor device, which may be built on both conventional silicon and a silicon-on-insulator substrate. A further object of the present invention is to provide the manufacture of a metal oxide semiconductor field effect transistor device, which allows the use of any kind of gate dielectric material. Another object of the present invention is to provide metal oxygen with a highly conductive material

O: \ 66 \ 66693.ptc Page 6 V. __month (3) ___ 2 Manufacturing of semiconductor field effect transistor devices Steel is used as the gate electrode. A further purpose of refractory metal or invention is to provide the manufacture of gold electro-mechanical devices, in which manufacturing materials + conductor field effect control are achieved to achieve the desired critical gate size, and to strengthen the etching process. The method of the present invention includes: forming a base material: a fossil evening, or a similar alloy island, on a material domain, and using the shape as a group IV-R to open: Γ evening island (the wrong fossil evening is here, Wusu One of the preferred alloys used by the medium and preferred alloys, M: > feizi) An oxide or nitride is established around the side wall representing the case area and π ^ lice compounds, forming a source on the substrate Extreme: Cause: 5 ί 'Remove Wrong Fossil Evening Island' ❿ Do not need to remove the wide area around the island: Full! ί = leaving a gap above the domain; and stepping up the second gap with the gate structure according to the steps, the step preferably includes: forming a 1-pole dielectric on the gate region of the gap, and using the gate electrode material Fill up the remaining gaps. The step of removing silicon germanium (or other IV-B group alloy) islands preferably includes depositing a layer of non-island material on the island and above the source and drain regions, which allows the alloy selection of the island It can be dissolved or removed in other ways without removing the deposited non-island material layer at the same time. The non-island material layer may provide polycrystalline silicon (or polycrystalline silicon for those who are familiar with this field) when providing the source / drain region, or when providing traditional source / non-polar The region can be a suitable dielectric such as silicon nitride or H oxide. After filling the gap with the gate structure, the method preference includes planarizing the upper region of the structure by chemical mechanical polishing. In a specific embodiment of the present invention, in which a raised source / drain region is formed, the method proceeds

Page 7 V. Description of Invention (4)

One step includes the structure of the structure to form the source and electrode. ^ A metal layer is deposited on the surface of the layer; and the first specific embodiment of the first specific embodiment of the metallization that electrically contacts the gate region and the drain region is described in Fig. 1-1 2 describes the sequential steps of metal according to the source / dead region of the present invention. FIG. 13 depicts the device described on the substrate “Description of the device on this substrate. The structure of the device after the device. In addition-the specific embodiment of the embodiment of the barrier layer deposition Figure 15 describes the completed device structure and deposition obstacles _ Material device and gate barrier layer deposited on the substrate by oxygen implantation isolation (SIM0X). Description According to another specific embodiment of the present invention, metal oxide + conductor% efficiency transistor Sequential steps of device manufacturing. For a detailed description of the specific embodiment, turn to the illustration, starting with Figure 1, a substrate, in this example, the only single-crystal silicon substrate, usually described in 20. Used here The "substrate" or "Shi Xi substrate" means a large piece of silicon, single crystal silicon substrate, or silicon on insulator (soi) substrate, including by oxygen implantation isolation (SIM). x) substrate. The base 20 will be specially treated to form electrically active and / or isolated areas, and the fabrication of the device will be described here after it is suitable. Pre-processing can include, without limitation, the traditional definition and isolation of n-wells 611) and / or p-wells; trenches and trench isolation caused by refilling with polycrystalline stone or tritium; traditional or fully embedded walls formula

Page 8 501205 V. Description of the invention (5) The area oxidation (L0C0S); and / or the structure of the silicon on the insulator, is produced by the area stone oxidation method (L0C0S) or etching. Such steps can be mixed or used individually. The silicon-on-insulator (SOI) substrate can be manufactured by implanting single-crystal silicon with high-dose oxygen and then annealing (annealing) to form silicon crystals that are bonded by the oxygen implant isolation method (SIM0X). Round and etchback, heteroepitaxy and so on. An example of the method of isolation by oxygen implantation (SIM0X) is implantation of oxygen at a dose of about 2 × 10 × 8 cm2 at about 2000 kV. The wafer is then at 1300 () to anneal for 4 to 8 hours. The thickness of the buried oxide layer is about 300 nanometers. Once the previous process is completed, the substrate can be flat & The entire plane is planarized by the mechanical polishing method (CMP). 1 The oxide layer 22 is formed on the substrate 20 to a thickness of about 5-30 nanometers (nm). ) The oxide layer 22 refers to the welding layer (_ 22 22. It belongs to the periodic table] ^ 4 groups of elements, the material layer is deposited on the oxide layer 22. In the illustrated example of Bai Xian described here, Ιν_β Preference is given to misformed polycrystalline stones, which are deposited by chemical vapor deposition: 2. The thickness of gold is about 150 nanometers to 50 nanometers. Germanium fossils are here, and Beirentian Cong "# " u " ' You will use it as a suitable δ 2 as the island material, and the representative of the IV_B group element alloy will be described below. The μ column with a mismatched silicon layer is more preferably represented by SiixGex, in the range of χ 0.5, but can be Any sound in the range of about 0.05 to about 丨 · 〇 .: The distorted silicon alloy layer is formed by lithography and the deposited silicon germanium layer, respectively. Lane 4 ... of two Shaw removed by the recorder is in the area of (iv) in FIG. 23 in phantom i

501205 91.2.2 6 ____Case No. 89120365_ Year Month Amendment ___ V. Description of Invention (6)-Instructions. Outside of island region 24, etching of region 23 stops at pad oxide layer 22. In other words, the silicon germanium layer 23 is masked in the gate region and then the remaining silicon germanium layer is etched to form islands 24. The pad oxide layer outside the masked π island π area 2 4 can be partially etched or completely removed during the etching process, although it can also be stopped as a worm in the subsequent step. In this illustrated embodiment, the pad oxide layer 22 is not removed. Silicon germanium islands 2 4 replace π casting for gate electrode formation. In other words, ’SiGe 2 2 4 forms a dielectric image that will become the gate electrode. This image will preferably be used as a pattern or form of a metal gate electrode or a gate electrode of another material without a separate lithography step, which will be described later. For example, the image of island 24 can be transferred to a gate electrode that is highly doped with polycrystalline silicon or germanium polycrystalline silicon alloy material. The figure here describes the formation of a metal oxide half-mass-effect transistor that can be of the η-channel or ρ-channel type. If both types are formed at the same time during the manufacturing process, a photoresist is used to mask the 11-channel transistor during low-dose (or lightly doped with impurities) drain (^ ⑽) ion implantation. The low-dose drain (LDD), regions, 26 and 28, shown in Figure 1, are formed by implantation of boron fluoride (βρ2) ions or plasma doping with impurities (ρ 1 a s m a d o p i n g). The preferred ion dose is 5-50 x 10 cm3, and boron fluoride (BFS) ion energy ranges from 10 kV to 80 kV. The ion energy is low enough so that no ion crosses the fragmentation layer. The photoresist was peeled off and a low-dose non-polar (LDD) ion implant was used to mask the p-channel transistor with a new photoresist. A low-dose drain (LDD) region is formed by or ion implantation. The ion dose is 5-5 0 X l (^ cm2, and the ion energy of arsenic is 40k electron volts to ι〇 & electricity ^).

Page 10 501205 Case No. 89120365 Amendment V. Description of the invention (7) Volt. The ion energy filled in is from 10 kV to 60 kV. The transistor shown in the figure shows either an n-channel transistor or a p-channel transistor. For the purpose of thickening the pad oxide 22, a selective oxidation step may be performed, which results in the formation of a "bird's beak" (b i r d s s b e a k) at the edge of the island, as described in Figs. 2 30 and 32. The bird's beak can increase the breakdown voltage of the gate oxide at the edge of the gate electrode. The oxidation step can be accomplished by heating the structure of Fig. 1 with oxygen to thicken the pad oxide region 22 which is not covered by the 'island π 24, which is well known. During this oxidation step, ions at the low-dose drain (L D D) diffuse and extend beyond the length of the bird's beak, as shown in Figure 2. The stone nitride layer 34 is deposited on the structure by any of the most advanced processes such as plasma-assisted chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD), resulting in a composition as shown in FIG. 2. In another embodiment, the oxide may be used as the material of the layer 34. Suppose that silicon nitride is used in layer 34 (Figure 2). After that, the wafer is susceptible to the anisotropic nitride. It leaves a thin layer of nitrides 3 6 and 3 8 around the side wall of the germanium fossil layer. As shown in Figure 3. Referring now to FIG. 4, a layer of alloy material different from that used for the island 24IV-B group is deposited on the structure of FIG. Layer 40 (Figure 4) refers to a non-island material because it must be different from the material of island 24 to allow the island to be easily removed without simultaneously removing the material used for layer 40. In the first specific embodiment of the present invention, the island 40 prefers deposited polycrystalline stones. Polycrystalline stone layer 40 is deposited on the golden island of the wafer, the sidewall of the island, and the source and drain regions. The layer 40 is thicker than the silicon germanium layer 24 by ff T ”. The layer 40 is also referred to herein as the first polycrystalline silicon layer 40. This

O: \ 66 \ 66693.ptc Page 11 501205 V. Description of the invention (8) The structure is then processed by chemical mechanical polishing (CMP) to expose the silicon germanium island 24, as shown in FIG. 5. The photoresist mask 33 is then applied to cover the active area of the device. The polycrystalline silicon layer 40 in the field region 35 (shown in cross-hatched lines) is not covered by a photoresist. The polycrystalline silicon layer 40 and any suitable portion of the substrate 20 are etched to remove the field region 35. The resist layer 33 is then peeled off. At this time, only the source region 26 and the drain region 28 of both the p-channel and n-channel transistors are covered by the polycrystalline silicon layer 40. The wafer is covered with a layer of oxide (shown by dashed line 37 in Fig. 6) 'which is equal in thickness or greater than the depth of the oxide deposited in the field region 35. The oxide layer is planarized by chemical mechanical polishing (CM p) and stops on the upper surface of the polycrystalline silicon and silicon germanium layers. Highly selective slurries, which remove oxides faster than polycrystalline silicon, are satisfactory for this process. This results in an isolation oxide region 41, which surrounds the polycrystalline silicon layer 40 as shown in Figs. Region 41 isolates the device on the substrate from another. The area 41 is only shown in FIGS. 7 and 8. After describing the steps associated with FIGS. 5 and 6, it should be understood that it also exists in other figures. The next step is that source / drain ion implantation continues to exist in the polycrystalline region 40 of Figs. 5-7. It is assumed that both p and n-channel devices are being processed, and implantation is performed first in the p-channel device. Photoresist is applied while the n-channel transistor is masked. The p-channel source / dead region includes polycrystalline silicon region 40 in FIG. 5 and is implanted with bF2 ions. The preferred ion dose is from 1.0 to 5.0 X 1 015 cm2, and the bf2 ion energy is f 10 k electron volts to 8 Ok electron volts. In addition, the ion energy is low enough that no ions can be implanted through the gate dielectric layer and into the channel region. Ion implantation produces lifted p + source region and p + drain of p-channel transistor

Page 12 501205 V. Description of Invention (9) Area. The photoresist is peeled off and the new photoresist is used to mask the p-channel transistor for n-channel source / drain ion implantation. The η channel source / drain is formed by implantation of god (or phosphorus) ions, the ion dose is 1 · 0-5 · ο X 1 015cm2, the ion energy of arsenic is 40k electron volts to 100k electron volts or phosphorus , The energy of 10k electron volts to 60k electron volts. Masked. Resistance to spalling and the wafer is in the air around the inert gas, the temperature is about 8000C to 11000, and it is annealed for 5 seconds to 60 minutes. The source and drain of the p-channel transistor are doped with impurities to become p +, while the corresponding regions of the n-channel transistor are doped with impurities to become η +. Referring to FIG. 9, the silicon germanium island 24 is removed by any of various methods such as highly selective wet etching '. There are many wet etching processes that can selectively remove silicon germanium on silicon, including a mixture of acetic acid, nitric acid, and hydrogen fluoride ^ It shows that the selectivity of germanium fossils on the stone is better than 100: 1. Better than 1000: 1 on silicon oxide. A mixture of ammonium hydroxide (0401) and hydrogen peroxide (200) and water will selectively etch silicon germanium, at least 5 times faster than silicon. Mixtures of hydrogen peroxide (Η202), hydrogen fluoride (HF), and water will also etch the wrong fossils on Shi Xi. Any of these wet etching methods will result in the composition of FIG. Because of the high selectivity and appropriate pattern control during the etching of the silicon germanium island 24, the key size ', in other words, the gate length can be controlled. In other words, the inner walls of the spacers 36 and 38 are disclosed herein during the manufacturing process. The surface of the gate region remains close to normal so that the critical dimensions of the poles do not change during the manufacturing steps. In the specific embodiment shown, the gate bond size is between 0.1 μm and 0.2 μm, preferably about 0.3 μm, which extends from region 26 to region 28. The gate The width of the area. shift

Page 13 5〇2205 $ :, the description of the invention (10), the area of # towel island 24 is m will be 4 to complete 4 # crystal above the transport area 42 ′ here means the gap 45. The gap 45 is also a gap above. ^ After removing silicon germanium, the remainder of the original pad oxide 22 is exposed. In FIG. 9, only line 22 indicates that it is not. Although this oxide layer can be used as the gate dielectric to remove: after the silicon island, the remaining pad oxide is not polluted or injured. The pad oxide 22 can be used for unmasked contamination. Because of ⑶, the oxide core is removed; =: = removed, the channel area 42 is exposed, which needs to be at the gate electrode ... · 料 Although the best way to form the gate dielectric is to re-grow the dielectric on the road silicon in the channel area 42 Electricity, such a heavy length will cause the edges to become thin, and the device produced after the basin has an unwanted low-interval collapse effect: hunting = careful design of the previous oxidation step as described in Figure 2 The mouths 30 and 32 are shaped around the island of the staggered fossil, and the pad oxide at the edge of the gate becomes thicker. If the residual oxygen is carefully controlled, the "toe" will be formed at the spacer (36,3), which compensates for the thinning of the edges. 広 1 Dielectric can be formed by some form of deposition. These 1 people I :: materials other than silicon oxide may be used, others》: Shao (II: properties such as high dielectric constant and / or high collapse strength such as nitrogen oxide are aluminum oxide (Al2O3) , Titanium oxide (Τί〇2), oxidized hammer (Zr〇2) secondary emulsification group (Ta205). In addition, zirconium oxide and 2

Page 14 V. Description of the invention (11): l ^ a, fnium) oxide compounds can be used, such as aluminum doped erbium oxide with silicon doped erbium oxide, erbium oxide, doped with ming ° MA? Oxide is not needed in oxygen. In these examples, the oxidation process is described in the process flow ^ ^ t # 1 9 to form a bird's beak and this step can be deposited from which method process tube is used. The final result is not at the gate. The lightning strike is the formation of the gate dielectric layer 44, as shown in Figure 10. On the structure: After the map, the gate electrode material 46 is deposited on the entire junction. Gates and drains, = fill gaps with use and edit (Ta), correct Pt), or two: two domains; metals, such as cranes, 1 (Cu), and obstacles t =, or 疋咼 Conductive metallic copper is tungsten nitrideΐ:;: Nitrogen = (TiN), nitrided nitride), or silicon can also be used for gate formation. One planarization to remove multiple = two; Partly, such as selective auto-alignment metallization technology (Wici line to minimize gate, source, and square), it is easy to implement 12, silicide layers 52, and 54 can be used by Quanyu Parasitic resistance. Reference% belongs to ... (1e) system = a problem with the technology of metal silicidation e, ▲ = fire. First, 36, 38 unetched metal and disk $ =: / may borrow By remaining Interval, source and / or drain are shorted. This problem is 501205. V. INTRODUCTION TO THE INVENTION (1¾-a very short CMP step to resolve the "strict grinding process". The device of Figure 12 is now ready for conductor metallization, It can use any technique known to those skilled in the art to form the source, gate region, and: the electrodes in this area, where the electrodes are electrically connected to their individual areas. 可以 can be used by traditional Patterning and post-metallization can be achieved with alloys such as Shao. However, because the surface has been fully planarized, embedded metallization using copper and mechanical polishing (CMP) can be easily implemented. Dry Weir Now Referring to Fig. 13, the structure is shown on a substrate by oxygen implantation isolation (sim0x), which has a bulk silicon layer 60 and a buried oxide layer 62. The remaining structure is used before 14 and 15 show another specific embodiment of the present invention, in which a barrier layer is deposited in the void 45 of FIG. 9. The barrier layer 70 is preferred to be a suitable barrier layer material such as nitride. Titanium (TiN), nitride button (Ta N) or tungsten nitride (WN) is used with the copper gate electrode 73, which is then deposited in the gap 45 (see FIG. 15). The excess barrier material on the anode and drain is removed by chemical mechanical polishing, This results in a natural self-alignment of the barrier electrode 73 barrier material, as shown. Figure 6 shows a specific implementation of Figure 15 on a substrate by oxygen implantation isolation (SIM0X) "2. The gates of Figures 14-16 Dielectric 44 by any suitable method such as a high dielectric constant material such as an oxide button (T 〇5), titanium oxide (T i 〇2), hafnium oxide (ZrO2), hafnium oxide (Hf〇2) Any one of them can be selectively doped with impurities, whether silicon or aluminum, or other suitable dielectric materials. A similar process can be used to provide & implementation 2 and gate dielectric 44 as described with reference to FIG. 10.

Π

Page 16 501205 Case No. 89120365 91. 2. 2 6 6 Rev. 5 Description of the invention (13) Other I V-B group alloys such as silicon tin can also be used as false or replaced gates in the process described above. Similar processing steps and process variables can also be used for silicon germanium and silicon tin alloy processes based on the similar chemistry of these materials. These new fake gate materials can also be used in the manufacture of other devices such as ferroelectric memory and ferroelectric memory. The foregoing specific embodiments of the present invention use a raised source / drain composition; the specific embodiments of FIGS. 17-2 have a conventional source / drain structure. Figures 17, 18, 19, and 20 are shown separately, which is equivalent to the steps shown in the first specific embodiment of Figures 3, 4, 5, and 9. The same reference numbers are used for the same elements as in the two sets of figures. In FIG. 17, the formation of islands 24 and sidewall spacers 3 6, 3 8 is followed by an implantation step to implant a suitable or P-type dopant (depending on the type of device to be formed) Enter the substrate 2 0. After performing appropriate annealing to start the dopants, the result is the formation of source and non-electrode regions 100, 102. In this specific embodiment, the next step (FIG. 18) is to deposit a layer of dielectric 1 6 , Such as silicon dioxide, to alloy islands, island sidewalls, and source and drain regions. The layer 106 is also referred to as a non-island material deposited on the aforementioned structure, or is the "first layer of a dielectric material". Like layer 40 in FIG. 4, layer 106 is thicker than silicon germanium ("island") layer 24 by an amount T (see Figure 4). The structure was then chemically and mechanically ground to expose the germanium fossil xidao 24, as shown in Fig. 19. In FIG. 19, the source / drain regions 100/102 are covered by the silicon dioxide layers 110/112. Field area formation for device isolation can be practiced with reference to the illustrations and descriptions shown in Figures 6-8 above. At this time, the silicon germanium island 2 4 by any selective removal of the island 2 4 material but not

O: \ 66 \ 66693.ptc Page 17 501205 Case No. 89120365 Amendment V. Description of Invention (14) Remove spacers 3, 6, 3, or silicon dioxide area 1 1 0 and 1 1 2 method to remove. There are many wet etching methods known to those skilled in the art that selectively remove silicon germanium on silicon dioxide or silicon nitride. The result of the removal step is the creation of a gap 45 in the gate region, or the creation of a channel region 42, as shown in FIG. In the specific embodiment of FIGS. 17-22, the formation of the gate dielectric layer 44 (FIG. 21) and the deposition of the gate electrode material layer 46 are the same as previously described with reference to FIG. 10. As the gap 45 is filled with the gate structure, the upper surface of the planarized structure is reached to the height shown generally by line 118 in FIG. 22. The planarization step is performed by a chemical mechanical polishing method. Finally, a second layer of dielectric 122 is deposited on the planarized structure. Channels 1 2 4, 1 2 6, 1 2 8 are formed via layers 1 2 2 including channels 1 2 6 extending to the gate structure 130 and channels 124 and 128, which also extend through the first dielectric layers 110 and 112 to The source and drain regions are 100, 102. An appropriate metal layer (not shown) is then deposited on the structure and enters the channel 1 2 4, 1 2 6, 1 2 8 to form a source region 1 0 0, a gate region 1 3 0, and a drain region 1 0 2 Electrically contacted electrodes complete this device. Therefore, a metal oxide semiconductor field effect transistor using silicon germanium or a similar metal instead of a gate has been disclosed. Although a better structure formation method and its application to SI Mox substrates have been disclosed, it should be understood that further changes and modifications can be made without violating the scope of the invention as defined by the scope of the appended patent application. The present invention uses new materials for fake or replaced gates, which can be selectively removed with better control of the critical dimensions of the gates. In particular,

O: \ 66 \ 66693.ptc Page 18 501205 Case No. 89120365 Λ_Ά a Amendment V. Description of the invention (15) The replacement gate of silicon germanium can be etched and patterned more quickly than the replacement gate of the prior art. Moreover, the use of germanium fossils or similar alloys in place of the gate material allows the use of oxide or nitride spacers to form gate islands. Previously, polycrystalline silicon instead of gates could only be formed with oxidized spacers. ring

O: \ 66 \ 66693.ptc page 19 501205 _ case number 89120365 _ year month day _ correction diagram brief description element symbol description 20 substrate 22 oxide pad 23 Μ engraved area 24 silicon germanium island 26p--LDD domain (Source region) 28p--LDD region (drain region) 30 bird's beak 32 bird's beak 33 photoresist mask 34 silicon nitride layer 35 field region 36 nitride layer 37 dotted line 38 nitride layer 40 polycrystalline silicon layer 41 isolation oxidation Object area 42 Gate area (channel area) 44 Gate dielectric layer 45 Void 46 Deposited layer (gate material layer) 48 Polycrystalline silicon layer 50 Polycrystalline silicon layer 52 Silicide layer 54 Silicide layer 60 Bulk silicon layer 62 Buried oxide Physical layer 70 Barrier layer 73 Copper gate electrode 100 Source region 102 Drain region 106 Dielectric layer 110 Silicon dioxide layer 112 Silicon dioxide layer 118 Line 122 Dielectric layer 124 Open π 126 Open π 128 Open Π 130 Gate Polar domain

O: \ 66 \ 66693.ptc Page 20

Claims (1)

501205 91 · 2 · 2 6 _ Case No. 89120365 _ year and month __; _ VI. Patent application scope 1. A method for manufacturing a metal oxide semiconductor field effect transistor structure on a substrate, comprising: An island above the gate region formed in the material, the island is formed by an alloy of ⅤV-B elements; a side wall is built around the island; a source region and a pole region are formed in the substrate, and selectively removed Island without removing the sidewall, thereby leaving a gap above the gate area; and filling the gap with a gate structure. 2. The method according to item 1 of the patent application range, wherein the alloy element of group IV-B is Sii_xGex, and wherein X is in a range of about 0.05 to about 1.0. 3. The method according to item 1 of the scope of patent application, comprising, prior to the step of forming the island, depositing an oxide layer on the substrate, the thickness of which is between 5 and 30 nanometers (nm), and the formation of the island The step includes forming an island on the oxide layer. 4. The method of claim 3, wherein the step of forming an island comprises depositing a layer of material formed from an alloy of a group IV-B element to a thickness of about 150 to 500 nanometers onto the oxide layer. 5. The method of claim 4 in the patent application, wherein the step of forming the island further includes depositing a material layer formed of an alloy of an IV-B group element on the oxide layer, and masking the deposition layer on the island region. And the deposited layer is etched to remove layers other than above the gate region. 6. The method of claim 1, wherein the step of removing the island includes depositing a non-island material layer on the island, its sidewalls, and source and non-electrode regions. O: \ 66 \ 66693.ptc Page 21 501205 _Case No. 89120365_Year_Month__ VI. Above the scope of patent application; chemically and mechanically grinding the structure to the top of the island; and dissolving the island with a solvent, so stay Down the gap. 7. The method according to item 6 of the patent application, wherein the non-island material layer is polycrystalline silicon, the non-island material layer is a first polycrystalline silicon layer, and the step of filling the gap includes depositing a gate material layer to the remaining first Above the island material layer and the gap, the structure is chemically and mechanically ground to remove the material down to the height of the top of the first polycrystalline silicon layer. 8. The method of claim 7 in the scope of patent application, wherein the gate material is made of polycrystalline silicon; tungsten (W); tantalum (T a); platinum (P t); molybdenum (MO); copper (Cu) bonding site Barrier metals such as titanium nitride (TiN), nitride button (TaN) or tungsten nitride (WN); and polycrystalline silicon germanium are selected. 9. The method of claim 6 in which the non-island material layer is a first layer of dielectric material. I 0. The method of claim 9, wherein the first layer of dielectric material is selected from the group consisting of silicon nitride and silicon oxide. II. The method according to item 9 of the patent application, wherein after the step of filling the gap with the gate structure, the method includes planarizing the upper surface of the structure by a chemical mechanical polishing method. 1 2. The method of claim 11 in the scope of patent application, wherein after the step of planarizing the structure, the method includes depositing a second layer of dielectric material onto the planarizing structure to form multiple openings through the second layer of dielectric Material to the gate structure, and forming an opening through the second layer of dielectric material and through the first layer of dielectric material to the source and drain regions and depositing a metal layer over the structure and entering the openings to form the Source region, gate region and drain region are electrically O: \ 66 \ 66693.ptc page 22 501205 _ case number 89120365 _ year month day _ amendment _ VI. Patent application scope Contact electrode. 1 3. The method according to item 1 of the patent application scope, wherein the step of constructing the side wall around the island includes building the side wall from a material selected from the group consisting of nitride and oxide of stone. 14. The method according to item 1 of the scope of patent application, wherein the length of the gap extends from the source region to the drain region, which is between 0.10 and 0.20 microns. 15. The method according to item 1 of the scope of patent application, wherein the step of filling the gap with the gate structure includes depositing a gate dielectric layer on the source region, the drain region, and the gap, thereby forming a gate in the gap. A dielectric and then a layer of gate electrode material is deposited over the gate dielectric layer. 16. The method according to item 15 of the scope of patent application, wherein the step of forming the gate dielectric comprises depositing a material having a high dielectric constant and a high collapse strength. 17. The method according to item 15 of the scope of patent application, wherein the deposited gate dielectric includes materials selected from the group consisting of: tantalum oxide (Ta205), titanium oxide (Ti02), and oxygen north Hafnium (Zr02), hafnium oxide (Hf02); the following materials are doped with silicon: tantalum oxide (Ta205), titanium oxide (Ti02), zirconium oxide (Zr02), hafnium oxide (Hf02); and the following materials doped with aluminum Miscellaneous: Tantalum oxide (Ta2 05), titanium oxide (Ti02), zirconia (Zr02), hafnium oxide (Hf02) 〇1. The method according to item 15 of the scope of patent application, wherein the step of depositing the gate dielectric layer This is accomplished by a process selected from the following: physical vapor deposition (PVD), chemical vapor deposition (CVD), and plasma enhanced chemical vapor deposition (PECVD). O: \ 66 \ 66693.ptc page 23 501205 _ case number 89120365_ year month date__ VI. Patent application scope 1 9. For the method of applying for the first item of patent scope, in which the gap is filled with a gate structure After the step, the method includes planarizing the upper surface of the structure by chemical mechanical polishing. 20. The method according to item 19 of the application scope, wherein, in the step subsequent to planarizing the upper surface of the structure, a metal layer is deposited on the upper surface of the structure and the structure is metallized to form a source region and a gate. An electrode in which the polar region and the non-polar region are in electrical contact. 2 1. The method of claim 20 in the scope of patent application, which includes, after the step of depositing a metal layer on the upper surface of the structure and before the metallized structure, annealing the structure to facilitate automatic alignment of the metallization process (sa 1 pesticide) process. 2 2. A method for manufacturing a metal oxide semiconductor field effect transistor, comprising: depositing an oxide layer on a silicon substrate for device isolation; forming a silicon tin alloy island on a gate region in the substrate; establishing Side wall around the silicon silicide island; forming the source region and the electrode region in the substrate, removing the silicon silicide island, so leaving a gap on the gate region; filling the gap and filling the gap between the source and the electrode The area above the polar region; and planarize the upper surface of the structure by chemical mechanical polishing. 2 3. The method according to item 22 of the patent application scope, wherein the tin alloy is represented by Sii „xSnx and wherein X is in the range of about 0.05 to about 1.0. 2 4. 22. The method of item 2, wherein the step of constructing a side wall around the island of silicon tin alloy includes the steps of O: \ 66 \ 66693.ptc Page 24 501205 _Case No. 89120365_Year_Month__ VI. The side wall materials selected in the patent application group establish the side wall. 2 5. A method for manufacturing a metal oxide semiconductor field effect transistor, comprising: depositing an oxide layer on a Shi Xi substrate for device isolation; a silicon germanium alloy island formed on a gate region in the substrate; Establish sidewalls around silicon germanium islands; form source and non-electrode regions in the substrate; remove silicon germanium islands, leaving gaps in the gate region; The area above the polar region; and planarize the upper surface of the structure by chemical mechanical polishing. 26. The method of claim 25, wherein the silicon germanium alloy is represented by Si ^ _xGex and wherein X is in the range of about 0.05 to about 1.0. 27. The method of claim 25, wherein the step of constructing a sidewall around the silicon germanium island includes establishing a sidewall from a sidewall material selected from the group consisting of nitride and oxide. wall. O: \ 66 \ 66693.ptc Page 25