TW304279B - Method of forming self-aligned salicide - Google Patents

Abstract

A method of manufacturing MOSFET device on semiconductor substrate by one double spacers comprises of the following steps: (1) forming multiple field oxide regions in the semiconductor substrate;(2) growing one gate insulator on the semiconductor substrate, but without covering the field oxide region; (3) growing one polysilicon on the gate insulator and the field oxide region; (4) photolithographying one polysilicon gate structure pattern on the polysilicon on the gate insulator, used to generate the polysilicon gate structure; (5) implanting ion with first conductive impurity in the semiconductor substrate where is not covered by the field oxide, used to generate one first source and one first drain region; (6) depositing one first insulator on the polysilicon gate structure, the first source and the first drain region, and the field oxide; (7) by anisotropic etch generating one first insulating spacer on the first insulator on the polysilicon structure side; (8) implanting ion with second conductive impurity in the semiconductor substrate where is not covered by the polysilicon gate structure, the first insulator, and the field oxide, used to generate one second source and one second drain region; (9) depositing one second insulator on the polysilicon gate structure, the first insulating spacer, the second source and the second drain region, and the field oxide; (10) by anisotropic etch generating one double insulating spacers including one second insulating spacer on the second insulator of the first insulator on the polysilicon structure side; (11) implanting ion with third conductive impurity in the semiconductor substrate where is not covered by the polysilicon gate structure, the double insulating spacer, and the field oxide, used to generate one third source and one third drain region; (12) executing one first annealing procedure, used to activate conductive impurity of the first source and the first drain region, the second source and the second drain region, the third source and the third drain region; (13) executing one pre-metal cleaning procedure; (14) on the polysilicon gate structure, the exposed surface on the third source and the third drain top, and the second insulating spacer and the field oxide surface, depositing one first metal layer; and (15) removing the first metal layer without chemical reaction on the second insulating spacer and the field oxide surface, executing one second annealing procedure, used to form one polysilicon gate structure on the polysilicon gate structure, the exposed surface of the third source and the third drain top.

Description

A7 B7 Printed by the Ministry of Economic Affairs, Central Bureau of Standards, and Consumer Cooperation V. Description of the invention () 5 · 1 Field of invention: The present invention relates to a method of manufacturing metal oxide semiconductor field effect transistors (MOSFETs) and components, especially It is used to reduce the short-circuit effect of gate to drain in the process of metal silicide formation. 5 · 2 Background of the invention ·· The semiconductor industry is constantly stimulating the improvement of MOSFET device manufacturing technology. The sub-micron technical capability has enabled the manufacture of smaller parasitic capacitors and resistors. This result also allows the manufacturing process to obtain While sub-micron technology has achieved great success from advanced semiconductor manufacturing theory. In terms of lithography, the success of complex photographic exposure technology has enabled more sensing photoresist materials to be used in sub-micron routine photoresist technology. In addition, the improvement of dry etching tools and manufacturing processes also enables the photoresist image of the photoresist layer to successfully transfer the covering material onto the structure of the MOSFET. In addition to the contributions made by the advanced MOSFET device manufacturing theory, the use of more conductive materials can increase the functionality. For example, in the case of a polysilicon metal gate structure, a gate structure includes a metal silicide layer covering the polysilicon layer, the resistance of the gate structure, and the polysilicon gate used previously The polar structure has been significantly reduced. The self-aligned silicide (Self-ALigned-sillCIDE) process is used to manufacture the polysilicon gate structure. It can also be applied to the conductive metal silicide coating of the source and drain, and the entire manufacturing process has benefited a lot. This paper scale is applicable to the Chinese National Standard (CNS) a4 specification (210X297mm)-A · (please read the precautions on the back before filling this page) Dream. Order

Is〇4S7 9 A7 B7 Printed by Employee Consumer Cooperative of China National Standards Bureau, Ministry of Economic Affairs 5. Description of invention () Successful metal silicide process capability, and self-aligned silicide process, the insulation gap of the polycrystalline dream gate part Purity is closely related. Taking the conventional metal deposition as an example, the "primary oxide layer exposed by the top layer of the source and drain" and the top layer region of the source and the electrode must be removed so that the subsequent metal silicide process can continue . The original oxide layer prevents the metal from interacting with the exposed silicon surface during tempering. Therefore, a buffered hydrofluoric acid procedure needs to be used before metal deposition. However, if the insulation gap of the polysilicon gate is flawed, or if it is too thin so that more than two stones are exposed, as a result, the buffered hydrofluoric acid procedure used for the removal before metal deposition will produce unacceptable The required metal silicide, and the passage made of metal silicide, will have a short circuit or leakage effect on the substrate on the polysilicon gate structure. The present invention will describe a double insulation interdiffusion process to prevent the occurrence of metallization pathway phenomena 'also allows additional resistance reduction effect through the source and drain engineering sequence'. After lightly doping the source and drain regions, first, an oxidized dream gap is formed beside the polysilicon evening gate, and then a moderately doped region is generated for the source and drain; in the heavily doped source and drain regions After that, two insulating gaps, that is, the silicon nitride layer are also generated. Used to deposit the previously used buffered hydrofluoric acid removal process, it is now possible to increase the expected success rate of self-aligning the chemical process without risking the purity of the nitriding-dream radonization gap insulator. In the conventional technology, such as Bracchita Zhujun US Patent No. 5,51 8,945 'Description 1 contains two substances. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) f— (please read the back side first Note. Please fill out this page again) Order A7 B7 5. Description of the invention () ~ " Insulating gap composed of a mixture of silicon-doped radon compounds. However, the conventional technology does not indicate that the source and drain In the manufacturing process of the electrode, two insulating gaps are added to the manufacturing process concept. 5-3 Object and concept of the invention: The purpose of the present invention is to use a self-aligned silicide process to manufacture MOSFET devices. Another object of the present invention is to Uses a double-insulated interstitial structure to prevent the insulating layer from being thinned by the hydrofluoric acid buffering process used before depositing the metal. This prevents the gate-to-substrate from self-aligning the slashing process, resulting in metal silicide The situation of the material path. A further object of the present invention is to form the source and drain of the impurity after the first insulating gap is generated but before the second insulating gap is generated In order to reduce the resistance of the MOSFET element. According to the above-mentioned purpose, the invention provides a utilization-polycrystalline metal gate, a pair of insulating gaps, and a three-level A method of manufacturing a MOSFET device with a source in the drain region. A gate insulating layer is grown after the field effect oxidation region is formed; a polysilicon layer is deposited, doped, and shaped to produce a polysilicon gate structure ; A lightly doped source and drain regions are also determined by the polysilicon gate structure; forming a silicon oxide chamber with a first gap beside the polysilicon gate structure; the next one is doped The paper standard of the source electrode and the electrode electrode is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). The A7 _B7 is printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. It is decided; the formation-the second gap of the silicon nitride layer is on the side of the first interlayer silicon oxide layer, so that in the polysilicon gate structure, a double insulating gap can be formed and can be used to order heavy doping Miscellaneous sources And drain region. After the hydrofluoric acid buffer removal process used before depositing the metal, a metal deposit is formed; the next tempering process is used to convert the exposed silicon on the top of the polysilicon gate structure, as well as the source and drain The material at the tip of the pole becomes metal silicide; the stable metal covering the double insulating gap is selected to remove the metal silicide covering the polysilicon gate structure in the polysilicon gate structure. 5 · 4 Brief description of the circle type: The purpose and advantages of the present invention will be described by the following preferred embodiments and related reference icons: Figures 1 to 5 use a pair of insulating gaps for the MOSFET device in cross-sectional architecture The main process steps used to improve the source and drain are described. 5-5 Detailed description of the invention: Now a detailed description will be given to the process of MOSFET device using a pair of insulating gaps to improve the manufacturing process of the source and the non-electrode . Selection-Single crystal Zhen, < 100 > crystal orientation p-type substrate 1, and a thick field oxide layer (Field OXide, F0X) 2 for isolation is formed thereon, the field oxide layer 2 is suitable for this paper size China National Standard Falcon (CNS} A4 specification (210X 297mm) (please read the notes on the back before filling in this page) Ordering Line * Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ 04279 V. Description of Invention () Department In an environment filled with oxygen vapor at a temperature of 850 to 1050 * C ', a thickness between 4000 and 6000 angstroms (Angstrom) is manufactured by thermal oxidation, and a layer consisting of an upper layer of silicon nitride and a lower layer is used The compound radon mask of the pad oxide layer is used to separate the regions of each element. After the field radon layer 2 is formed, the hybrid mask will use a thermal peak acid solvent to remove the silicon nitride layer and adjust the part of the oxide layer Then use buffered hydrofluoric acid to remove. A silicon dioxide layer 3 as the gate insulation taste, and then use a temperature of 8 5 〇 to 〇〇〇, filled with oxygen vapor environment, produced by thermal oxidation method The thickness ranges from 50 to 200 Angstroms. A polycrystalline The silicon layer is then deposited by low-pressure chemical vapor deposition (LPCVD) at a temperature of 600 to 800 scoops, and a thickness of about 500 to 5000 angstroms is deposited. The polysilicon layer can be grown in an intrinsic state; or by using one per square The dose of 1E14 to 1E16 particles and the energy of 25 to 75 electron volts are used for the implantation of phosphorus or arsenic ions. The polysilicon layer can also be added to phosphorus or arsenic in a silane environment through a simultaneous doping process. Use the traditional photolithography and reactive ion etching process (Reactive 丨 ⑽ Etching ’R 丨 E), and use gas (c 丨 d as an etchant) to manufacture the polysilicon gate structure 4 in the first ring structure, and the polysilicon The width of the gate structure 4 is between 0.05 i and 2.0 μm. The removal of the photoresist is accomplished by using oxygen plasma and wet removal. A lightly doped source and gate region 5 is used from 5 to 100. The energy of electron volts and the dose of 1E11 to 1E14 particles per square centimeter are formed on the semiconductor substrate 1 by ion implantation of phosphorus or arsenic, and this area is also depicted in the structure of the first figure. Is the second in the framework of the second Section-Insulation gap 6, the paper size is suitable for financial customs (CNS) A4 «i7210X297 ^^) ^ f booking line (please read the precautions on the back before filling this page) Printed by Beigong Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs System A7 —- _____B7_ V. Description of the invention () The first insulation gap 6 is deposited by LPCVD or Plasma enhanced chemical vapor deposition (PECVD) process at a temperature of 300 to 800 * C, and the thickness is deposited A silicon oxide layer of about 200 to 5000 angstroms. The silicon oxide layer used to deposit the first insulating gap 6 can be obtained through a thermal oxidation process. An alternative solution is to use a non-isotropic etching RIE process, using CHF3 or CF3-〇2-He as an etchant, to manufacture the first insulating gap 6 beside the polycrystalline broken gate structure 4 described above. The alternative RIE process stops when the laser used detects the end point of exposure to the lightly doped source and drain silicon materials, that is, the silicon material on the top of the polysilicon gate structure 4 Throughout the manufacturing process, the width of the first insulating interstitial 6 is almost equal to the thickness of the deposited silicon oxide, which is also between 200 to 5000 Angstroms. Therefore, in the next step of heavily doping the source and drain regions, if only the first insulating gap 6 described above is used as the insulating gap, excessive side diffusion will occur, so the source and drain regions need to be The lightly doped regions do more compensation, and the injection of too many thermoelectric carriers will have adverse side effects, and therefore there are so-called stability considerations. In addition, if only one first insulation gap 6 is used in the subsequent self-aligned silicide process, the buffered hydrofluoric acid used in the removal process before depositing the metal will make the first insulation gap 6 thinner, This will cause a short circuit or leakage due to the path formed by the metal silicide between the closed pole and the substrate. Therefore, the present invention provides a compensation effect between the lightly doped region of the source and the metal in the following series of processes. After the first insulation gap 6 is formed, a source and source paper standard General Chinese National Standard (CNS) A4 specification (210X297 Gongchu) is generated (please read the precautions on the back before filling this page) r A7 B7 Printed by the Consumers ’Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. The description of the invention (in the middle zone 7, as shown in the structure of the second circle. With an energy of 5 to 50 electron volts, Yuyi per square centimeter 1E12 to 5E14 particle amount of _ or arsenic ion implantation method can produce the above-mentioned mid-doped region 7 °. This mid-doped region 7 is not like the subsequent heavily doped source and drain regions. For the purpose of contact, the side diffusion effect will be smaller than the lightly doped source and drain regions, so it also reduces the presence of thermoelectric carriers in the process of heavily doped source and drain regions. In addition, the medium-doped source and non-electrode regions 7 also reduce the resistance of the lightly doped source and drain regions 5 covered under the first insulating compartment 6, and also improve the implementation effect. The second picture describes _the formation of the second insulating intertaste 8 "-the second must The gap is deposited through an LPCVD or PECVD process at a temperature of 200 to 800 in an environment with a thickness of about 200 to 5000 angstroms. The same 'an alternative solution is to use anisotropic etching R The E process, using CHF3 or SFrO2 as an etchant, can be used to make the second insulating gap β '. The alternative rie process also stops when silicon is detected. The third circle also depicts the use as a low resistance The generation of heavily doped source and drain regions 9 for contact purposes can be generated by an energy of 5 to 150 electron volts and an arsenic ion implantation method with a dose of 1E15 to 5E16 particles per cm 2. The rapid thermal tempering (Rapid

Thermal Anneal (RTA) tempering process, which lasts 5 to 120 seconds in an environment with a temperature of 800 to 1100 ° C, to activate the doped impurities in the source and drain regions. This paper scale is applicable to China National Standard (CMS) A4 (210X29? Mm) --------- '1 ^-, ---- 11 ------ year (please read first (Notes on the back then fill this page)

Printing by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs followed by the self-aligned silicide process. First, a pre-deposition process for the pre-metal deposition is required to remove the original oxide layer in the exposed silicon material area. It can be obtained by flushing with hydrofluoric acid and treating for 5 to 120 seconds. If the second insulating gap 8 of silicon nitride is not used, the first insulating gap 6 of the silicon oxide layer will not withstand the buffering hydrofluoric acid treatment process and become thinner, and the defective first insulating gap 6 will It is impossible to prevent the generation of metal silicide on the side of the polysilicon gate structure 5, and as a result, a short circuit or leakage of the gate to the substrate may occur. After the above-mentioned buffered hydrofluoric acid treatment process, a radio frequency injection process is used to deposit a titanium metal layer with a thickness of 50 to 1000 Angstroms, and an RTA process for 20 to 90 seconds at a temperature in the range of 550 to 700, It is used to form a titanium silicide layer 10 on the top surface of the heavily doped source and drain regions 9 and the polysilicon gate structure 4. In this second insulating gap 8, titanium that does not chemically react with the surface of FOX 2 can be removed by selecting the following solvents H202-H2S04, so a self-calibrating titanium silicide layer is thus formed. The polysilicon metal gate structure covering the polysilicon gate structure 4 and the titanium silicide layer 10 is also drawn in the frame circle of the fourth circle. The fifth figure describes the formation of the connecting metal in the heavily doped source and drain regions 9, which is in contact with the metal silicide. Although not shown in the fifth figure, the connecting metal is also formed of polysilicon metal. First, the silicon monoxide layer 11 is grown through a PECVD process to a thickness of 3000 to 6000 Angstroms in a temperature range of 350 to 540 °. In traditional lithography and RIE processes, CHF3 can be used as an etchant to open a contact hole 12, and the photoresist can be removed through the paper standard applicable to the Chinese National Standard (CNS) Λ4 specification (2I0X297mm). (Please read the precautions on the back before filling in this page) Ordering-! A7 B7 5. Description of the invention (Oxygen plasma and wet removal are completed. One contains 1 to 3% copper metal, and about 0.5 to 1% silicon The metal aluminum layer can be deposited to a thickness of 4000 to 8 000 Angstroms using a radio frequency injection process. The conventional lithography and R | E process can use C! 2 as a social etching agent 'in the framework of the fifth circle to produce With a metal connection structure 13, the photoresist can also be removed using oxygen plasma and wet removal. The above embodiment uses a double insulating gap to produce a MOSFET device process to improve the manufacturing process of the source and drain , The sister uses N-channel MOSFET devices to illustrate 'but the technology can also be applied to p-channel MOSFET devices, complementary MOS devices, and bipolar CMOS (bipolar-CMOS, BiCOMS) devices. The above is only The preferred embodiment of the present invention is not intended to limit The scope of patent application for this invention · Any other equivalent changes or modifications made without departing from the spirit disclosed by this invention should be included in the following patent application garden. (Please read the notes on the back before filling in This page) 'f. 、 1Ί Printed by the Consumer Cooperative of the Central Sample Falcon Bureau of the Ministry of Economic Affairs 10 papers for Chinese HU materials (CNS> A4W (21GX 297 male thin

Claims (1)

'Scope of patent application • A method of manufacturing a gold transistor (MOSFE) using a double insulating gap on a semiconductor substrate. The method includes the following steps: field effect to form a plurality of field oxide regions in the semiconductor substrate. Oxidized f insulating layer In the semiconductor substrate, a polysilicon layer is grown on the gate insulating layer and the field oxide region without covering the field; a polysilicon gate structure a • a crystal formed on the gate insulating layer * 5 evening layer, used to generate the polysilicon gate structure; ions of the first conductive impurities are implanted on the semiconductor substrate in areas not covered by the oxide region to generate a first source electrode and a sum electrode Region; depositing a first insulating layer on the polysilicon gate structure, the first source 'the first drain region, and the field oxidation region; using an anisotropic etch potential, to produce-a first insulating gap On the first insulating layer beside the polysilicon structure; ions of the second conductive impurity implanted into the semiconductor substrate are not the polysilicon gate structure, the first insulating gap, and the field Covered by oxidation zone For generating a second source and second drain region; depositing a second insulating layer on the polysilicon gate structure, the first insulating gap, the second source and the second drain region And on the field oxide region; using anisotropic etching, a double insulating gap including a second insulating gap is generated on the second insulating layer on the first insulating layer beside the polysilicon structure; 11 / iy The Ministry of Economic Affairs, Central Standards Bureau, employee cooperation, cooperation, du printing, patent application, implantation of the third conductive compound, and the temporary ion from the ω, the received ion in the semi-conductive male substrate 'is not the polycrystalline eve The gate structure, the alternate insulation gap, and the area covered by the field oxide region are used to generate-the _, the second source and the third drain region; execute a first Return, ί5 I * input procedure, used to activate the first source and the first-drain region, the second source and the second source into a second drain region, the third source and the third drain Conductive impurities in the pole region; perform a metal pre-clearing procedure; the exposed surface of the polycrystalline stone evening closed structure, the third source and the top of the third electrode, and the second insulating gap and the A first metal layer is deposited on the surface of the field oxidation region; and—after removing the second insulating gap and the surface of the field oxidation region, the first metal layer that has not undergone a chemical reaction, a second round is performed Fire procedure for exposing the top of the polysilicon gate structure, the third source electrode and the third drain electrode The surface _L forms a polysilicon gate structure. 2. The method as described in the patent application section, in which the above-mentioned gate insulating layer is composed of silicon dioxide, and the silicon dioxide layer is grown in an oxygen vapor environment at a temperature of 85 ° to 100 ° C. To a thickness of 200 Angstroms. 3. The method as claimed in item 1 of the patent application, in which the above-mentioned polysilicon layer is deposited to a thickness of 500 to 5000 Angstroms in an environment with a temperature of 600 to 800 * C through a low pressure chemical vapor deposition (LPCVD) procedure. 4. For example, the method of applying for the patent item scope item, in which the above-mentioned polysilicon gate 12 paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling this page) Order production! The structure uses C 丨 TuJi 丨 2 as a single engraving agent ’through the reactive ion etching (RIE) process of the polysilicon layer. The sequence grows out’ The width of the structure is between 0.05 and 2.0 microns. The method of patent scope $ 1, wherein the above-mentioned first-conducting impurities used to generate the first source and the second-drain regions utilize energy of 5 to 100 electron volts, and 1E11 to 1E14 per square centimeter Phosphorus ions implanted in a dose of three particles. 6 'The method as claimed in the patent application, wherein the first insulating layer is a silicon oxide layer, the silicon oxide layer is using low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (pECVD) The process is in an environment with a temperature of 300 to 800, and a thick and wide layer of 200 to 5000 Angstroms is deposited. 7 As the method of the patent application, the first insulation gap is through the silicon oxide. The isotropic etching process uses CHF3 or CF3-02-He as an etchant. --------- f ·! (please read the precautions on the back before filling in this page) 〇 · If you are a profit-seeking fan, the Ministry of Economic Affairs Central Standard Falcon Bureau Beigong Consumer Cooperative printed source and the The second conductive impurity in the second drain region is arsenic or ions implanted using an energy of 5 to 50 electron volts and a dose of 1E12 to 5E 14 particles per square centimeter. 9. The method as claimed in item 1 of the patent application park, in which the above-mentioned second insulating layer is a silicon nitride layer, the silicon nitride layer is manufactured by LPCVD or PECVD, and the paper size is applicable to the Chinese National Standard (CNS) M size (210X297 mm) Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ 04279« D8_____ 6. The range of patent applications is at a temperature of 200 to 800. The method of item 1 of the patent group, wherein the above-mentioned second insulating gap is formed through anisotropic etching of the silicon nitride layer by the R 丨 E process, using CHF3 or SFe-02 as the etchant. For example, in the method of applying for patent patent item item # 3, the bismuth third conductive impurity used to generate the third source and the third drain region utilizes an energy of 5 to 150 electron volts, and 1E15 per square centimeter Implanted into a dose of 1E16 particles. 12. The method as described in item 1 of the patent application, in which the aforementioned metal pre-clearing procedure uses a buffered hydrofluoric acid solution (Buffered hydr 〇f I u 〇 ricacids ο IU ti ο π) treatment for 5 to 120 seconds. 13. The method as claimed in item 1 of the patent application, wherein the first metal layer is titanium metal, and is deposited to a thickness of 50 to 1000 angstroms through a radio frequency injection procedure 14. The method as claimed in item 1 of the patent application park, in which the above metal silicide is titanium silicide 'is to use rapid thermal tempering (Rapid. Thermal Anneal, F ^ TA> procedure' at a temperature of 550 to 700 · 〇 In the environment, the processing time is 20 to 90 seconds. ------- ίμ ^ 丨 丨 (Please read the precautions on the back and then fill out this page) *-· β 一 丨 This paper standard is applicable to the Chinese National Falcon ( CNS) Α4 specification (210Χ297 mm) A8 BS C8 ____ D8 printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. Scope of patent application 15. For example, the method of applying for patent item No. 10, in which the above-mentioned chemical The reacted first metal layer is selected to be removed by using H2〇2-H2S04 solution. 16. The method as claimed in item 1 of the patent application park, wherein the contact hole opened in the above-mentioned insulating layer is due to metal deposition and After the development process, so that the third source The structure of the metal connection between the third drain region and the polysilicon metal gate structure "· 1 7.-A kind of semiconductor substrate 'using silicon nitride-silicon radon layer' a pair of insulating gaps, and forming a light The doped source and the doped drain region, a mixed source source and the doped drain region, a heavily doped source and heavily doped drain region are used to manufacture metal oxide half field effect transistor (MOSFET) devices The method includes the following steps: \ Form a plurality of field oxide regions in the semiconductor substrate; grow a gate insulating layer on the semiconductor substrate, but do not cover the field oxide regions; grow a polysilicon layer on the A gate insulating layer and the field oxide region; a lithography-polysilicon evening gate structure ring-shaped on the polysilicon layer on the gate insulating layer to generate the polysilicon gate structure; implanting a first conductive impurity Ions in the semiconductor substrate, which are not covered by the above-mentioned field oxidation region, are used to generate the lightly doped hard source and the lightly doped drain region; > deposit a silicon oxide layer on the crystal Silicon gate structure, the lightly doped source and the paper ruler Use the Chinese National Standard (CNS) A4 specification (210x297 mm) II— II n IIII to set— (please read the notes on the back before filling in this page j. Patent scope A8 B8 C8 D8 Employees of the Central Bureau of Economic Development The consumer cooperative printed the lightly doped area covered by the polysilicon gate implanted with the silicon structure; deposited on the insulating interstitial area; the double-insulated silicon nitride implanted polysilicon gate field radonization area doped the drain to perform doping Anisotropic etching on the source and the source of the mixed-drain electrode, the deposition electrode and the heavy-silicon absolute drain-electrode region, and the field vaporization region, creating a free-valence silicon oxide insulation gap beside the poly On the silicon oxide layer; the ions of the second conductive impurities are used in the semiconductor substrate of the plant, and are not used for the pole structure, the oxide stone, and the gap between the edge of the oxide and the field oxidation area. In order to produce the medium-doped source electrode and the medium-doped drain-nitride hair insulating layer in the polycrystalline closed-electrode structure, the oxidized hair, the medium-doped source electrode and the medium-doped nanometer and pole regions, And the gas anisotropic erosion Engraved-produce silicon nitride-silicon oxide insulation between the smell, known in the polycrystalline hairline description, "_ ^ ^ / on the side of the silicon oxide insulating layer on the insulating layer; third conductive impurities The ions in the semiconductor substrate, the non-polar structure, the oxidized silica-oxide double insulation and the covered area are used to generate the heavily doped source and region, a first tempering process; Conductive impurities used to activate the heavily doped source and the first region, the moderately doped source and the moderately doped drain region, and the lightly doped selective impurity region. A titanium metal pre-clearing process; A titanium metal layer is formed on the exposed surface of the polysilicon gate structure, the top of the heavily doped drain, and the surface of the nitrogen edge gap and the field oxide region; the gap is the hybrid (please first Read the precautions on the back and then fill out this page)-Grade 16 paper size Lai + S ϋ home standard (CNS) Α4 specifications (210X29? I ^ 7 A8 B8 C8 6. The scope of applying for patents is printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs after the removal of the silicon nitride · silicon oxide double insulation and the surface of the field oxidation zone, the titanium metal layer that has not reacted with the chemical, Perform a second tempering process to form a titanium silicide layer on the exposed surface of the polysilicon gate structure, the top of the heavily doped source and the heavily doped drain; and remove the above The silicon nitride-silicon oxide double insulation gap and the unoxidized titanium metal layer on the surface layer of the field oxide region to make a polysilicon metal gate structure, the polysilicon metal gate structure is covered by the The magic titanium layer on the polysilicon closed-pole structure is composed of the titanium silicide layer covering the heavily doped source and the heavily doped drain regions. Factory 18_ The method as claimed in Item 17 of the patent application, in which the above-mentioned gate insulation layer is composed of radon silicon. The silicon dioxide layer is grown in an oxygen vapor environment at a temperature of 850 to 1000 C and grows 50 to 50 200 Angstroms thick. 19_ The method as claimed in item 17 of the patent application group, in which the above polysilicon layer is deposited to a thickness of 500 to 5000 Angstroms in an environment with a temperature of 600 to 800 ° C through a low pressure chemical vapor deposition (LPCVD) procedure . 20. The method of claim 17 of the patent application, wherein the polysilicon gate structure described above is developed using active ion lithography (RIE) procedure of the polysilicon layer using C 丨 2 as an etchant. Between 0.05 and 2.0 microns. 21. The method as claimed in item 7 of the patent application scope, wherein the first conductive impurities used to generate the doped source and lightly doped drain regions described above are applied to the Chinese Weijia standard using this paper standard ( CNS) Α4 specification (210Χ297mm) (Please read the precautions on the back before filling in this page) -α4 · Order- ^ I · A8 B8 SI printed by Beigong Consumer Cooperative of Central Bureau of Standards of the Ministry of Economy The energy in the range of 5 to 100 electron volts and the implanted mouth ions per square centimeter of 1E11 to 1E14 particles. 22. The method as claimed in item 17 of the patent application, wherein the above silicon oxide layer is made by low pressure chemical vapor deposition (LpcvD) or plasma chemical vapor deposition (PECVD) process at a temperature of 300 to 800. The environment deposits a thickness of 200 to 5000 Angstroms. 23. The method as claimed in item 17 of the patent scope, wherein the above silicon oxide oxide is formed by anisotropic etching of silicon oxide R | E process, using CHF3, or CF3-〇2-He as an etchant to form . 24_ The method as claimed in item 17 of the patent scope 'wherein the second conductive impurities used to generate the mid-doped source and the t-doped drain region utilize energy of 5 to 50 Arsenic or phosphorous ions implanted in a dose of 5 cm14 to 5E14. 25. For example, the method in claim 17 of the patent application, wherein the above-mentioned oxidized silicon layer is deposited by a LPCVD or PECVD process at a temperature ranging from ⑽ to _ .c to a thickness of 200 to 5000 Angstroms. 26. The method as claimed in Item 17 of the patent application, wherein the above silicon nitride gap is formed by anisotropic etching of silicon nitride by the R | E process, using CHF3 or SFe-02 as the etchant. 13 This paper scale is applicable to the Chinese National Standard (CNS) A4 (210X297mm). Please read the notes on the back and fill in the text.) Order i A8 B8 C8 D8 6. The patent application group 27. The method as described in item 17 of the patent application park, in which the third conductive impurities used to generate the heavily doped source core and the heavily doped drain region are utilized. 5 Energy to 150 electron volts, and arsenic ions implanted at a dose of 1E15 to 1E16 particles per square centimeter. 28. The method as claimed in item 17 of the patent application, in which the above-mentioned titanium metal pre-clearing procedure is to use a buffered hydrofluoric acid solution (Bufferedhydrofluoric acid solution) for 5 to 120 seconds. 2 9. The method as claimed in Item I? Of the patent application, wherein the above-mentioned titanium metal layer 'is deposited to a thickness of 50 to 1000 angstroms through a radio frequency injection procedure. 30. For example, Fang Feng of item 17 of the scope of patent application, wherein the above titanium silicide layer 'is processed by Rapid Thermal Anneal (RTA) process in a temperature environment of 550 to 700 * C for 20 to 90 seconds. 31. The method as claimed in item 17 of the patent application, wherein the titanium metal layer which has not undergone the above-mentioned chemical reaction is selected to be removed by using H202-H2S04 solution. 32. As for the square enamel of claim 17, the contact hole opened in the above-mentioned insulating layer is deposited and lithography after the metal layer mainly made of aluminum, using a CU RIE procedure to make the The heavily doped source and the heavily doped source are used in 19 papers that use the Chinese National Standard (CNS) A4 specification (210x297 mm) (please read the precautions on the back before filling out this page) Jealous · Booking, · Application Patent scope A8 B8 C8 D8 pole region 'and the polysilicon metal gate structure, forming an aluminum metal connection printed by the Ministry of Economic Affairs of the Ministry of Economic Affairs of the Ministry of Economic Affairs Bureau of Consumer Cooperative 33.-A variety of MOSFET device structures, including: multiple field oxidation Zone, located on the surface of a semiconductor substrate;, a device scratching zone, between the field oxidation zone; a polysilicon metal structure, consisting of: a metal on a polycrystalline gate structure on the semiconductor substrate Composed of silicide layer; the first insulating gap 1 is located beside the polysilicon gate structure; the second insulating gap is located on the first insulating gap; a lightly doped source and lightly doped drain region are located in the Semiconductor-based Surface, between the polysilicon gate structure and the field oxidation interval;, a medium-doped source and a doped drain region located on the surface of the semiconductor substrate, between the first side of the polysilicon gate structure An insulating gap and the field oxidation interval; a heavily doped source and heavily doped drain region, located on the surface of the semiconductor substrate, between the second insulating gap and the field radonization interval; and a metal connection structure for The heavily doped source and the heavily doped drain region. 34. The mosFEt device structure as claimed in item 33 of the patent scope, wherein the above-mentioned first insulating gap 'is composed of a silicon oxide having a thickness of 200 to 5000 angstroms. The size of this paper & China National Standard (CNS) from the secret (210 × 297mm) ----- Discarded (Please read the notes on the back side before filling in this page) -β 3 ^ S79 --- ~ — .—. Scope of patent application 5. For example, the 33rd item of the patent application, the second insulation compartment is from a thickness of 200 to = Angstrom. Formed by. The gas of Wang 5000 Ang 36. The m〇sFET _ μ of the above-mentioned lightly doped source and device structure as in patent application No. 33, where ... 1 w particles m complex; 1 pole region / cm 2 < The dose consists of implanted phosphorus ions. 37, as claimed in the scope of patent application. ^ ^ 罘 3 items; MOSFET device structure, in which, Guangzhong holds the mixed source and the doped non-electrode region, is implanted by a dose of 5E14 particles per square centimeter Or phosphorus ions composed of 0 38_ such as patent application Fan Gudi Hui Le ^ 3 MOSFET device structure, where the above-mentioned re-emphasis of hetero-source electrode and goods tongue exchange this heavy-doped drain £, by each square Centimeter * 1 E 1 5 to 1 E 16 grain years> jjfel JL Agi AJr -V JLU -λΙ. It is composed of arsenic ions implanted at a sufficient dose. (Please read the precautions on the back before filling in this page) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 21 This paper scale is applicable to the Chinese National Standard (CNS) A4 (210X297mm)