Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0144—Manufacturing their gate insulating layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
  • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
  • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
  • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
  • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/68—Capacitors having no potential barriers
  • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
  • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/981—Utilizing varying dielectric thickness

Definitions

• the present invention relates generally to semiconductor devices, and more particularly to semiconductor devices formed having dual gate dielectric thicknesses and utilizing high-k gate dielectric materials such as metal oxides.
• transistors for input/output (I/O) devices may require thicker gate dielectrics than, e.g., transistors used for the core logic.
• a conventional process for forming differing thickness is called a DGO process, which stands for Dual Gate Oxide.
• a "thick" silicon dioxide layer e.g. for the I/O devices
• a resist mask is used to mask the thick silicon dioxide layer in the I/O regions.
• the thick silicon dioxide layer is then etched away or otherwise removed from the unmasked region, where the core logic devices are to be formed.
• the mask is removed and a thin silicon dioxide layer is then grown over the core logic device region.
• the gate electrode material typically polysilicon, is then deposited over the substrate, which at this point includes gate dielectrics of two different thicknesses.
• the gate electrode material and gate dielectrics are then patterned and etched to form the gate electrode and oxide stack of each transistor.
• the DGO process described above has found acceptance in the industry as a manufacturable and cost effective way of producing transistors having two different gate dielectric thicknesses.
• transistor sizes shrink there is a move in the semiconductor industry to replace traditional silicon dioxide gate dielectrics with higher-k dielectric materials (i.e. dielectrics having higher dielectric constants), such as metal oxides.
• metal oxides cannot be thermally grown on a silicon substrate as silicon dioxide can there are problems associated with multiple metal oxide depositions to form differing oxide thicknesses and with etching of the metal oxide if one were to attempt to merely substitute a metal oxide for silicon dioxide in a conventional DGO process. Accordingly, there is a need for a semiconductor manufacturing process in which dual gate dielectric thicknesses can be achieved with metal oxides or other high-k dielectric materials.
• FIGs. 1-4 illlustrate partial cross-sectional views of a semiconductor device formed to have two gate dielectric thickness (e.g. one for core devices and one for I/O devices) as it undergoes processing in accordance with one embodiment of the present invention
• FIG. 5 is a partial cross-sectional view of a semiconductor device formed in accordance with another embodiment of the present invention in which three different gate dielectric thicknesses are formed; and FIG. 6 is a partial cross-sectional view of a semiconductor device formed in accordance with yet another embodiment of the present invention in which a stack of metal oxide layers, rather than a single metal oxide layer, is used as part of the gate dielectric for each type of device to be formed (e.g. for both core devices and I/O devices).
• the present invention integrates a high-k dielectric material, preferably a metal oxide, in a dual gate process sequence using a single metal oxide deposition to form multiple gate dielectric stacks of differing thicknesses.
• the metal oxide is formed over prepared surfaces of the substrate that already provide a difference in equivalent oxide thickness (EOT) between two different regions of the substrate (e.g. the core logic region and the I/O region).
• EOT equivalent oxide thickness
• a single metal oxide layer is deposited over two different thicknesses of silicon dioxide or silicon oxynitride.
• the metal oxide need not be etched selective to the underlying silicon substrate (which can damage the substrate surface) where a gate quality surface is required.
• the single metal oxide layer forms an interface with a high quality silicon dioxide or silicon oxynitride layer, as opposed to an interface with a silicon surface which has been damaged or otherwise treated as a result of using conventional DGO processing methods with a metal oxide dielectric.
• devices formed in accordance with the invention do not suffer from degraded performance, e.g. current leakage, due to interface irregularities as a result of contamination or damaged surfaces.
• semiconductor device 10 is fabricated in accordance with one embodiment of the invention.
• semiconductor device 10 includes a semiconductor substrate 12 which in a preferred embodiment is a single crystal silicon substrate (also sometimes referred to as a wafer), but which can instead be formed from other semiconductor substrate materials.
• substrate 12 Within substrate 12, trench isolation regions 14, preferably shallow trench isolation regions, are formed in a conventional manner for the purpose of electrically isolating different individual devices to be formed.
• a first gate dielectric 16 is formed over substrate 12.
• First gate dielectric 16 is preferably silicon dioxide or silicon oxynitride, and is preferably formed by thermal oxidiation in accordance with conventional practices. The thickness of gate dielectric 16 is determined by the particular device requirements for devices to be formed in I/O device region 24 as further explained below, but generally will be within a range of 30-50 Angstroms (3-5 nanometers).
• a (photo)resist mask 18 is formed over the substrate to mask off a portion of the first gate dielectric layer.
• semiconductor device 10 includes two different device regions, namely a core device region 22 and an I/O device region 24.
• devices to be formed in core device region 22 require thinner gate dielectrics that operate at lower voltages than, e.g., I/O devices to be formed in I/O device region 24 that can withstand higher voltages required for I/O functions.
• resist mask 18 is formed to protect the portion of first gate dielectric 16 which will serve, in part, as a gate dielectric for the higher voltage I/O devices.
• Other dielectric materials may instead be used for first gate dielectric 16.
• Silicon dioxide and silicon oxynitride are attractive choices because of the industry's understanding of these materials, the ability to form high gate quality films, and because they can be formed by selective growth techniques rather than requiring blanket depositions and etch steps.
• Semiconductor device 10 is then etched to remove unprotected portions of first gate dielectric 16 in core device region 22, as shown in FIG. 2.
• the resist mask 18 is then removed and a second gate dielectric 20 is formed on exposed portions of substrate 12 within the core device region 22.
• second gate dielectric 20 is also silicon dioxide or silicon oxynitride, but like first gate dielectric 16 other materials could be used. This second gate dielectric can be formed by thermal oxidiation and/or chemical oxidation in accordance with conventional practices.
• the thickness of gate dielectric 20 is also determined by the particular device requirements for devices to be formed in core device region 22 as further explained below, but generally will be within a range of 4-12 Angstroms (0.4-1.2 nanometers). Because second gate dielectric 20 is so thin, it may be difficult to adequately control the thickness or obtain an oxide of sufficient quality using thermal oxidation processes and therefore chemical oxidation may be useful. For instance, the thin dielectric may be formed by growing a thin oxide by rinsing the substrate in ozonated water. A combination of thermal and chemical treatment may also be used to form second dielectric 20. It may also be sufficient for second gate dielectric 20 to be a native oxide which is grown on substrate 12 as a result of exposing the substrate to ambient or other oxygen containing environment.
• second gate dielectric 20 can be deposited, e.g., by atomic layer deposition.
• the thickness of first gate dielectric 16 may change, depending on the technique used to form the second gate dielectric 20, and should be taken into account in choosing the initial deposited or grown thickness of first gate dielectric 16. Generally, however, it is not anticipated that the thickness of first gate dielectric 16 will change significantly unless second gate dielectric 20 is deposited over first gate dielectric 16 rather than forming it through a thermal or chemical reaction of the substrate surface.
• a high-k dielectric (generally with k>4, preferably with k>6, and most preferably with k>7) is deposited over semiconductor device 10.
• this high-k dielectric is a metal oxide, such as metal oxide 26 shown in FIG. 3.
• Suitable materials for metal oxide 26 preferably include hafnium oxide (Hf0 2 ), hafnium silicate (Hf x Si y O z ), or lanthanum aluminate (LaA10 3 ), but lanthanum oxide, hafnium aluminate, zirconium oxide, and zirconium silicate, and other like materials, may also be suitable high-k dielectrics.
• the thickness of the high-k dielectric layer will be dependent on the particular device requirements in each region of the substrate (the core region and the I/O region), but generally it is believed the thickness of a metal oxide will be between about 15-50 angstroms (1.5-5.0 nanometers).
• the underlying thicknesses of first gate dielectric 16 and second gate dielectric 20 will also affect the choice of thickness of the high-k dielectric.
• the thickness of the high-k dielectric should be chosen so that its equivalent oxide thickness (EOT), when added to the EOT of the first gate dielectric 16 (I/O device dielectric) thickness or second gate dielectric 20 (core device dielectric) thickness, provides a total EOT appropriate for the I/O and core device, respectively.
• EOT equivalent oxide thickness
• this calculation should be used to determine the initial deposited or grown thicknesses of the first and second gate dielectrics. Because metal oxide 26 is deposited as a single blanket deposition, its thickness will not vary much across the substrate surface and thus one should use the thicknesses of the first and second dielectrics as the "variables" to achieve the final EOTs for the core and I O devices.
• a single metal oxide layer can be used while still achieving two different EOTs for different devices on the same substrate. If one were to incorporate a metal oxide into a conventional dual gate oxide (DGO) process, two different metal oxide thicknesses would be required to satisfy both core device and I/O device requirements. Problems associated with forming two different metal oxide thickness on the same substrate include: 1) difficulty in uniformly and selectively etching a metal oxide over a silicon substrate, and 2) difficulty in forming high quality interfaces between the metal oxide and silicon substrate and between the metal oxides deposited on top of one another in the I/O device region.
• DGO dual gate oxide
• a single metal oxide deposition is used, and the metal oxide is formed over prepared surfaces of the substrate which already provide a difference in EOT between the core device region 22 and I/O device region 24.
• the metal oxide need not be etched selective to the underlying silicon substrate where a gate quality surface is required.
• the metal oxide forms an interface with a high quality silicon dioxide or silicon oxynitride layer, as opposed to a silicon surface which has been damaged or otherwise treated as a result of conventional DGO processing with a metal oxide.
• Another benefit of the invention is that there is no metal oxide deposition on a metal oxide layer which has been damaged or treated as a result of conventional DGO processing.
• Gate electrode material 28 is deposited over the metal oxide, and semiconductor device 10 is patterned and etched to form the gate stacks as shown in FIG. 4.
• Gate electrode material 28 will generally be conductive (doped) polysilicon or a metal (e.g. titanium nitride).
• etch mask is used to pattern gate stacks in both the I/O and core device regions, but etch requirements may make it more desirable to use two masks, one for each of the two regions.
• conventional processing occurs to complete the transistor and integrated circuit formation (e.g. implants, spacers, interlayer dielectrics, interconnects, and passivation formation).
• a semiconductor device 50 includes gate dielectrics 52, 54, and 56 with respectively increasing physical thicknesses.
• Gate dielectric 52 could serve as the gate dielectric for a core logic device.
• Gate dielectric 54 could serve as the gate dielectric for an I/O device.
• gate dielectric 56 could serve as the gate dielectric for a high voltage device.
• the first dielectric layer formed would be the thickest dielectric needed (e.g. for the highest voltage devices), and that prior to forming the thinnest dielectric needed for the core devices, the intermediate thickness gate dielectric (e.g. for the I/O devices) would be formed.
• a single high-k dielectric such as a metal oxide would be deposited over the substrate and processing would continue as previously described in reference to FIGs. 3-4.
• a process in accordance with the invention includes a metal oxide stack as opposed to a single metal oxide layer.
• a semiconductor device 60 is fabricated having two different EOTs as previously described in reference to FIGs. 1-2. Thereafter, a first metal oxide layer 62 is blanket deposited over the substrate, followed by a blanket deposition of a second metal oxide layer 64.
• the two metal oxide layers are of different materials.
• One advantage in using two different metal oxides is that the grain boundaries within the layers can be misaligned to reduce current leakage in the transistor.
• Another reason for using two different materials is that one material may have desirable properties as a gate dielectric but may not be compatible with the material used to form the overlying gate electrode.
• first metal oxide layer is zirconium oxide (Zr0 2 ) or hafnium oxide (Hf0 2 ) and the second metal oxide is alumina (A1 2 0 3 ).
• the alumina may alleviate some of the compatability concerns between polysilicon and hafnium oxide or zirconium oxide.
• the second or top metal oxide layer will be thinner than the first metal oxide layer because it is being used principally as a capping layer rather than the bulk gate dielectric of the transistor.
• Metal gate electrodes may also benefit from use of a capping layer over the bulk dielectric material.

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• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Electrodes Of Semiconductors (AREA)

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• 2002
  • 2002-08-15 US US10/219,522 patent/US6787421B2/en not_active Expired - Lifetime
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