JP2005536053A - 金属酸化物を用いてデュアルゲートオキサイドデバイスを形成するための方法および形成されるデバイス - Google Patents

金属酸化物を用いてデュアルゲートオキサイドデバイスを形成するための方法および形成されるデバイス Download PDF

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Publication number
JP2005536053A
JP2005536053A JP2004529077A JP2004529077A JP2005536053A JP 2005536053 A JP2005536053 A JP 2005536053A JP 2004529077 A JP2004529077 A JP 2004529077A JP 2004529077 A JP2004529077 A JP 2004529077A JP 2005536053 A JP2005536053 A JP 2005536053A
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gate
metal oxide
dielectric
dielectric layer
gate dielectric
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JP2004529077A
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Japanese (ja)
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JP2005536053A5 (enExample
Inventor
シー． ギルマー、デイビッド
シー． ホッブス、クリストファー
ツェン、シン−ホワン
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NXP USA Inc
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NXP USA Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2004529077A 2002-08-15 2003-06-16 金属酸化物を用いてデュアルゲートオキサイドデバイスを形成するための方法および形成されるデバイス Pending JP2005536053A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/219,522 US6787421B2 (en) 2002-08-15 2002-08-15 Method for forming a dual gate oxide device using a metal oxide and resulting device
PCT/US2003/018939 WO2004017403A1 (en) 2002-08-15 2003-06-16 Method for forming a dual gate oxide device using a metal oxide and resulting device

Publications (2)

Publication Number Publication Date
JP2005536053A true JP2005536053A (ja) 2005-11-24
JP2005536053A5 JP2005536053A5 (enExample) 2006-07-20

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JP2004529077A Pending JP2005536053A (ja) 2002-08-15 2003-06-16 金属酸化物を用いてデュアルゲートオキサイドデバイスを形成するための方法および形成されるデバイス

Country Status (7)

Country Link
US (1) US6787421B2 (enExample)
JP (1) JP2005536053A (enExample)
KR (1) KR20050054920A (enExample)
CN (1) CN1675759A (enExample)
AU (1) AU2003285819A1 (enExample)
TW (1) TW200414529A (enExample)
WO (1) WO2004017403A1 (enExample)

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WO2010150332A1 (ja) * 2009-06-24 2010-12-29 パナソニック株式会社 半導体装置及びその製造方法
CN102332398A (zh) * 2011-10-28 2012-01-25 上海华力微电子有限公司 一种双高k栅介质/金属栅结构的制作方法
WO2012035684A1 (ja) * 2010-09-14 2012-03-22 パナソニック株式会社 半導体装置及びその製造方法

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US6946349B1 (en) * 2004-08-09 2005-09-20 Chartered Semiconductor Manufacturing Ltd. Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses
DE102004040943B4 (de) * 2004-08-24 2008-07-31 Qimonda Ag Verfahren zur selektiven Abscheidung einer Schicht mittels eines ALD-Verfahrens
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US7071038B2 (en) * 2004-09-22 2006-07-04 Freescale Semiconductor, Inc Method of forming a semiconductor device having a dielectric layer with high dielectric constant
US20060088962A1 (en) * 2004-10-22 2006-04-27 Herman Gregory S Method of forming a solution processed transistor having a multilayer dielectric
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US7214590B2 (en) * 2005-04-05 2007-05-08 Freescale Semiconductor, Inc. Method of forming an electronic device
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KR100762239B1 (ko) * 2006-05-03 2007-10-01 주식회사 하이닉스반도체 반도체 소자의 ｐｍｏｓ 트랜지스터, 이를 포함하는 반도체소자와 그의 제조 방법
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Publication number Priority date Publication date Assignee Title
WO2010150332A1 (ja) * 2009-06-24 2010-12-29 パナソニック株式会社 半導体装置及びその製造方法
JP2011009313A (ja) * 2009-06-24 2011-01-13 Panasonic Corp 半導体装置及びその製造方法
WO2012035684A1 (ja) * 2010-09-14 2012-03-22 パナソニック株式会社 半導体装置及びその製造方法
JP2012064648A (ja) * 2010-09-14 2012-03-29 Panasonic Corp 半導体装置及びその製造方法
CN102332398A (zh) * 2011-10-28 2012-01-25 上海华力微电子有限公司 一种双高k栅介质/金属栅结构的制作方法

Also Published As

Publication number Publication date
AU2003285819A1 (en) 2004-03-03
WO2004017403A1 (en) 2004-02-26
CN1675759A (zh) 2005-09-28
TW200414529A (en) 2004-08-01
KR20050054920A (ko) 2005-06-10
US20040032001A1 (en) 2004-02-19
US6787421B2 (en) 2004-09-07

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