CN1675759A - 使用金属氧化物形成双重栅极氧化物器件的方法及其合成器件 - Google Patents
使用金属氧化物形成双重栅极氧化物器件的方法及其合成器件 Download PDFInfo
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- 229910052746 lanthanum Inorganic materials 0.000 claims description 4
- -1 lanthanum aluminate Chemical class 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
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Abstract
使用单层高k电介质层,优选使用金属氧化物,形成具有两种不同栅极电介质厚度的半导体器件(10)。在用于更高的电压需要的器件的区,例如I/O区(24)中形成较厚的第一栅极电介质(16)。在用于更低的电压需要的器件的区,例如磁心器件区(22)中形成较薄的第二栅极电介质(20)。优选第一和第二电介质为二氧化硅或氮氧化硅。在两种电介质上淀积金属氧化物(26),随后是栅电极材料(28)的淀积。通过使用单层金属氧化物层以形成每个晶体管的栅极电介质堆栈,与高质量二氧化硅或氮氧化硅电介质层一起,可避免与金属氧化物的选择性蚀刻有关的问题,如与金属氧化物与损坏或处理的表面之间的各种界面有关的问题。
Description
技术领域
本发明涉及一种半导体器件,更具体地涉及一种形成为具有双重栅极电介质厚度并使用例如金属氧化物的高-K栅极电介质材料的半导体器件。
背景技术
在集成电路的制造中,通常需要在相同的半导体衬底或晶片上形成具有不同栅极电介质厚度的晶体管。例如,用于输入/输出(I/O)器件的晶体管需要比例如用于磁心逻辑的晶体管更厚的栅极电介质。用于形成不同厚度的常规工艺称为DGO工艺,其代表双重栅极氧化物。在常规DOG工艺中,形成“厚”二氧化硅层(例如用于I/O器件),并使用抗蚀剂掩膜来遮蔽I/O区中的厚二氧化硅层。然后蚀刻掉厚二氧化硅层,或换句话说自非遮蔽区移去厚二氧化硅层,其为应形成磁心逻辑器件的区。移去掩膜且接着在磁心逻辑器件区上生长薄的二氧化硅层。然后在衬底上淀积栅极电极材料,一般为多晶硅,在这一点包括两种不同厚度的栅极电介质。然后将栅极电极材料和栅极电介质图形化,并蚀刻以形成每个晶体管的栅电极和氧化物堆栈。
作为生产具有两种不同栅极电介质厚度的晶体管的可制造的和成本效率的方法,在该产业中,上述的DGO工艺获得了肯定。但是由于晶体管尺寸的缩小,半导体产业转而以例如金属氧化物的高K电介质材料(即,具有更高介电常数的电介质)替代传统二氧化硅栅极电介质。但是因为在硅衬底上金属氧化物不能如二氧化硅般热生长,因此在常规DGO工艺中,如果技术人员企图仅仅以金属氧化物替代二氧化硅,则存在与以多重金属氧化物淀积物形成不同氧化物厚度相关以及与金属氧化物的蚀刻相关的问题。此外,在半导体制造工艺中,需要以金属氧化物或其它高K电介质材料达到双重栅极电介质厚度。
附图说明
通过例证描述本发明,本发明不被附图所限制,其中同样的参考符号指相似的元件,其中:
图1-4是依照本发明的一个实施例描述随着其经受的工艺而形成具有两种栅极电介质厚度(例如一种厚度用于磁心器件,且一种用于I/O器件)的半导体器件的部分截面图;
图5是依照本发明的另一个实施例、在其中形成三个不同栅极电介质厚度而形成的半导体器件的部分截面图;和
图6是依照本发明的又一个实施例、在其中使用金属氧化物层堆栈而不是单层金属氧化物层作为用于每种将形成的类型的器件的栅极电介质部分(例如用于磁心器件和I/O器件)而形成的半导体器件的部分截面图。
本领域技术人员应理解,为了简明和清楚而描述附图中的元件,元件不必按比例画出。例如,可相对于其它元件放大附图中某些元件的尺寸,以帮助增进对本发明的实施例的理解。
具体实施方式
本发明整合高K电介质材料,优选金属氧化物,在双重栅极工艺程序中,使用单层金属氧化物淀积物来形成不同厚度的多重栅极电介质堆栈。依据本发明,在制备的衬底表面上形成金属氧化物,其在衬底的两个不同区域(例如磁心逻辑区和I/O区)之间,该衬底已具有氧化物厚度当量(equivalent oxide layer)(EOT)差。例如,在两种不同厚度的二氧化硅或氮氧化硅上淀积单层金属氧化物层。因此,不需要将金属氧化物选择性地蚀刻至需要栅极质量表面的硅衬底下面(其可破坏衬底表面)。而且依据本发明,单层金属氧化物层形成具有高质量的二氧化硅或氮氧化硅层界面,因为相反于具有硅表面的界面,该硅表面已被破坏,或换句话说因为以金属氧化物电介质、使用常规DGO工艺方法的结果处理。由此,由于污染物或破坏的表面的结果而造成界面的不规则性,依照本发明形成的器件不具有退化的性能,例如漏电流。
现在参照图1-4,依照本发明的一个实施例制造半导体器件10。如图1所示,半导体器件10包括半导体衬底12,其在优选实施例中为单晶硅衬底(且有时称为晶片),但是其可替代由其它半导体衬底材料形成。在衬底12中,为了将即将形成的各个单个器件电隔离,以常规方法形成沟槽隔离区14,优选浅沟槽隔离区。当形成沟槽隔离区14之后,在衬底12上形成第一栅极电介质16。第一栅极电介质16优选为二氧化硅或氮氧化硅,优选依照常规习惯通过热氧化而形成。栅极电介质16的厚度由将在I/O区24中形成的器件的具体器件需要来决定,在下面将进一步解释,但是通常在30-50(3-5nm)的范围内。
当形成第一栅极电介质16之后,在衬底上形成(光致)抗蚀剂掩膜18以遮蔽掉部分第一栅极电介质层。如图1所示,半导体器件10包括两个不同的器件区,即磁心器件区22和I/O器件区24。操作中,在磁心器件区22中将形成的器件需要更薄的栅极电介质,其操作比例如在I/O器件区24中将形成的I/O器件更低的电压,该I/O器件可承受用于I/O操作所需的更高的电压。此外,形成抗蚀剂掩膜18以保护部分第一栅极电介质16,其将部分地作为用于更高电压I/O器件的栅极电介质。其它电介质材料可替代用于第一栅极电介质16。由于对这些材料的工业理解、形成高栅极质量膜的能力和由于其可通过选择性地生长技术而不需要均厚淀积及蚀刻步骤来形成,二氧化硅和氮氧化硅是具有吸引力的选择。
接着蚀刻半导体器件10以移去磁心器件区22中第一栅极电介质16的无保护部分,如图2所示。接着移去抗蚀剂掩膜18,并在磁心器件区22内的衬底12的暴露部分上形成第二栅极电介质20。优选实施例中,第二栅极电介质20也是二氧化硅或氮氧化硅,但是与第一栅极电介质16相似,可使用其它材料。依照常规惯例,可通过热氧化和/或化学氧化来形成第二栅极电介质。栅极电介质20的厚度也由下面将进一步解释的在磁心器件区22中将形成的器件的具体器件需要来决定,但是通常4-12(0.4-1.2nm)的范围内。由于第二栅极电介质20非常薄,使用热氧化工艺难以恰当地控制厚度或得到足够质量的氧化物,由此化学氧化是有用的。例如,通过在臭氧水(ozonatedwater)中清洗衬底,通过生长薄氧化物可形成薄的电介质。可使用热处理和化学处理的组合来形成第二电介质20。对于第二栅极电介质20来说,由于将衬底暴露在周围环境中或其它含氧环境中的结果、其为在衬底12上生长的天然氧化物就足够了。在另一个实施例中,例如可通过原子层淀积来淀积第二栅极电介质20。
在形成第二栅极电介质20的进程中,取决于用来形成第二栅极电介质20的技术,可改变第一栅极电介质16的厚度,并应当考虑第一栅极电介质16的原始淀积或生长厚度的选择。但是,除非在第一栅极电介质16上淀积第二栅极电介质20,而不是通过衬底表面的热反应或化学反应来形成第二栅极电介质20,通常不预先考虑第一栅极电介质16的厚度将重大地改变。
现在形成了两种不同厚度的栅极电介质,在半导体器件10上淀积高K电介质(通常k>4,优选k>6,且更优选k>7)。在优选实施例中,该高k电介质为金属氧化物,例如图3所示的金属氧化物26。用于金属氧化物26的适当材料优选地包括氧化铪(HfO2),硅化铪(HfxSiyOz),或铝酸镧(LaAlO3),但是氧化镧、铝酸铪、氧化锆和硅化锆及其它类似材料,也是适合的高k电介质。高K电介质层的厚度将取决于衬底的每个区中(磁心区和I/O区)具体器件的需要,但是通常相信金属氧化物的厚度位于大约15-50(1.5-5.0nm)之间。第一栅极电介质16和第二栅极电介质20的下层厚度也将影响高k电介质的厚度的选择。可选择高k电介质的厚度,由此当加上第一栅极电介质16(I/O器件电介质)厚度或第二栅极电介质20(磁心器件电介质)厚度的EOT时,其氧化物厚度当量(EOT)提供分别适用于I/O器件和磁心器件的EOT总量。类似地,将使用该计算来决定第一和第二栅极电介质的原始淀积或生长厚度。由于淀积金属氧化物26作为单层均厚淀积,跨越衬底表面其厚度将不改变多少,且由此本领域技术人员可使用第一和第二电介质的厚度作为“变量”来得到用于磁心和I/O器件的最终EOT。
如图3所示,当在相同衬底上仍然得到用于不同器件的两个不同EOT时,可使用单层金属氧化物层。如果本领域技术人员将金属氧化物组合到常规双重栅极氧化物(DGO)工艺中,将需要两个不同的金属氧化物厚度以满足磁心器件和I/O器件的需要。与在相同衬底上形成两个不同金属氧化物厚度相关的问题包括:1)在硅衬底上均匀地和选择性地蚀刻金属氧化物的难度;和2)在金属氧化物和硅衬底之间以及在I/O器件区中的各个顶部淀积的金属氧化物之间形成高质量的界面的难度。依据本发明,使用单层金属氧化物淀积物,在制备的衬底表面上形成金属氧化物,该衬底具有磁心器件区22和I/O器件区24之间的EOT差。不需要将金属氧化物选择性地蚀刻至硅衬底下面,该下面的硅衬底需要栅质量表面。同时依据本发明,由于与硅表面相对,该硅表面已损坏或换句话说以金属氧化物的常规DGO工艺处理,金属氧化物形成具有高质量二氧化硅或氮氧化硅层的界面。本发明的另一个益处在于:在金属氧化物层上没有金属氧化物淀积物,该金属氧化物层已损坏或由常规DGO工艺来处理。
当淀积了金属氧化物层26之后,在金属氧化物上淀积栅电极材料28,图形化和蚀刻半导体器件10以形成栅极堆栈,如图4所示。通常栅电极材料28为导电的(掺杂的)多晶硅或金属(例如氮化钛)。优选地,使用相同的蚀刻掩膜来图形化I/O与磁心器件区中的栅极堆栈,但是蚀刻需求使得使用两个掩膜更加理想,每一个用于两个区中的每一个。这一点,常规工艺完成了晶体管和集成电路的构造(例如,平面,间隙壁,层间绝缘层,互连和钝化构造)。
依照本发明的另一个实施例,可使用相似的工艺以形成三重栅极氧化物(TGO)器件。在某些应用中,除了磁心或I/O器件以外,需要甚至更高压的器件且由此需要三种不同栅极电介质厚度。如图5所示,半导体器件50包括分别具有增大的物理厚度的栅极电介质52、54和56。栅极电介质52可作为用于磁心逻辑器件的栅极电介质。栅极电介质54可作为用于I/O器件的栅极电介质。而且,栅极电介质56可作为用于高压器件的栅极电介质。可以与参考图1-2中所述的栅极电介质16和20的方法相似的方法形成这些栅极电介质。差别在于:形成的第一电介质层为所需的最厚的电介质(例如,用于最高压器件),且在形成用于磁心器件所需的最薄电介质之前,形成中间厚度的栅极电介质(例如用于I/O器件)。这将通过以下实现:1)在将形成高压器件的区中遮蔽最厚的电介质;2)在磁心器件和I/O器件区中蚀刻该(最厚)电介质;3)在磁心器件区和I/O器件区中都形成用于I/O器件的栅极电介质;4)在I/O和高压器件区中遮蔽I/O栅极电介质和最厚电介质;5)在磁心器件区中蚀刻I/O电介质;6)形成磁心器件的栅极电介质。当形成三种不同的EOT之后,在衬底上淀积例如金属氧化物的单层高k电介质,且其工艺将继续如参考图3-4中先前所述的。
在又一个实施例中,依照本发明的工艺包括与单层金属氧化物层相对的金属氧化物堆栈。如图6所示,如参照图1-2中的先前所述,形成具有两种不同EOT的半导体器件60。此后,在衬底上均厚淀积第一金属氧化物层62,然后是第二金属氧化物层64的均厚淀积。在优选实施例中,两个金属氧化物层为不同的材料。使用两种不同金属氧化物的一个优点是:层内的晶粒边界可以不对准以减小晶体管中的漏电流。使用两种不同材料的另一个原因在于:一种材料可具有作为栅极电介质的所需性能,但是可以不与用来形成上覆栅电极的材料一致。由此,可选择与栅电极一致的第二金属氧化物。在一个实施例中,第一金属氧化物层为氧化锆(ZrO2)或氧化铪(HfO2),且第二金属氧化物为氧化铝(Al2O3)。当使用多晶硅栅电极材料时,氧化铝将减轻多晶硅与氧化铪或氧化锆之间的某些兼容关系。通常,由于主要用来作为覆盖层而不是晶体管的栅极电介质锭,因此第二或上部金属氧化物层比第一金属氧化物层薄。金属栅电极也受益于电介质材料锭上的覆盖层的使用。
在前述说明中,参考具体实施例描述了本发明。但是,本领域技术人员可以理解,不脱离如权利要求所提出的本发明的范围,可进行各种修改和变化。例如,当将本发明描述为形成磁心逻辑器件与I/O器件以具有不同的栅极电介质厚度时,可将本发明用于结合具有或需要两种不同栅极电介质厚度的任意两种器件。此外,将说明书和附图看成是说明性的而不是限制性的,且所有这样的修改都包括在本发明的范围内。
上面以相关具体实施例描述了益处、优点和问题的解决方案。但是,益处、优点和问题的解决方案,以及可导致益处、优点或解决方案发生或使之变得更加明确的元素,不应被视为任何或所有权利要求的决定性的、必须的或必要的特征或元素。如下文中所用的,术语“组成”、“包括”、或其它任何变化,是用来覆盖非排除性的包含,例如包括一系列的要素的工艺、方法、物品或装置,其不仅包括那些列出的要素,而且还包括没有特意列出的或工艺、方法、物品或装置所固有的其它要素。
Claims (21)
1.一种形成半导体器件的方法,包括:
提供半导体衬底;
形成覆盖半导体衬底的第一栅极电介质层;
移去覆盖半导体衬底的第一区的部分第一栅极电介质层;
形成覆盖半导体衬底的第一区的第二栅极电介质层;和
形成覆盖第一栅极电介质层和第二栅极电介质层的金属氧化物层。
2.如权利要求1的方法,其中第一栅极电介质层包括选自由氧化硅和氮氧化硅构成的组的材料。
3.如权利要求1的方法,其中第二栅极电介质层包括选自由氧化硅和氮氧化硅构成的组的材料。
4.如权利要求1的方法,其中金属氧化物层包括选自由二氧化铪、硅化铪和铝酸镧构成的组的材料。
5.如权利要求1的方法,还包括:
形成覆盖金属氧化物层的栅极层;和
将栅极层、金属氧化物层、第一栅极电介质层和第二栅极电介质层图形化,以形成第一栅极堆栈和第二栅极堆栈。
6.如权利要求5的方法,其中在磁心逻辑器件中使用第一栅极堆栈,且在I/O器件中使用第二栅极堆栈。
7.如权利要求1的方法,还包括:
移去覆盖半导体衬底的第二区的部分第二栅极电介质层;和
形成覆盖半导体衬底的第二区的第三栅极电介质层;
其中,形成金属氧化物层包括:形成覆盖第一栅极电介质层、第二栅极电介质层和第三栅极电介质层的金属氧化物层。
8.如权利要求1的方法,其中第一和第二电介质层具有不同的厚度。
9.一种形成半导体器件的方法,包括:
提供半导体衬底;
形成覆盖半导体衬底的第一电介质材料,其中覆盖半导体衬底的第一区的第一电介质材料的第一部分具有第一厚度,且覆盖半导体衬底的第二区的第一电介质材料的第二部分具有与第一厚度不同的第二厚度;
形成覆盖第一电介质材料的高k电介质层;
形成覆盖高k电介质层的栅极层;和
将栅极层和高k电介质层图形化以在半导体衬底的第一区内形成第一器件的栅极,且在半导体衬底的第二区内形成第二器件的栅极。
10.如权利要求9的方法,其中第一电介质材料包括选自由氧化硅和氮氧化硅构成的组的材料。
11.如权利要求9的方法,其中高k电介质层包括金属氧化物。
12.如权利要求11的方法,其中金属氧化物包含选自由二氧化铪、硅化铪和铝酸镧构成的组的材料。
13.一种半导体器件,包括:
覆盖半导体衬底的第一器件,所述第一器件包括:
覆盖半导体衬底且具有第一厚度的第一电介质;和
覆盖第一电介质的第一金属氧化物;和
覆盖半导体衬底、与第一器件间隔的第二器件,所述第二器件包括:
覆盖半导体衬底且具有不同于第一厚度的第二厚度的第二电介质;和
覆盖第二电介质的第二金属氧化物。
14.如权利要求13的半导体器件,还包括覆盖第一金属氧化物的第一栅极和覆盖第二金属氧化物的第二栅极。
15.如权利要求14的半导体器件,其中第一和第二栅极的每一个包含金属。
16.如权利要求14的半导体器件,其中第一和第二栅极的每一个包含多晶硅。
17.如权利要求16的半导体器件,还包括覆盖第一金属氧化物和在第一栅极下面的第三电介质,以及覆盖第二金属氧化物和在第二栅极下面的第四电介质。
18.如权利要求14的半导体器件,其中第一和第二电介质的每一个包含选自由氧化硅和氮氧化硅构成的组的材料。
19.如权利要求14的半导体器件,其中第一金属氧化物和第二金属氧化物包含相同的金属氧化物。
20.如权利要求19的半导体器件,其中第一金属氧化物和第二金属氧化物具有相同的厚度。
21.如权利要求19的半导体器件,其中第一和第二金属氧化物的每一个包括选自由二氧化铪、硅化铪和铝酸镧构成的组的材料。
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- 2003-06-16 CN CNA038194023A patent/CN1675759A/zh active Pending
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AU2003285819A1 (en) | 2004-03-03 |
WO2004017403A1 (en) | 2004-02-26 |
KR20050054920A (ko) | 2005-06-10 |
US6787421B2 (en) | 2004-09-07 |
US20040032001A1 (en) | 2004-02-19 |
JP2005536053A (ja) | 2005-11-24 |
TW200414529A (en) | 2004-08-01 |
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