CN1443367A - 用于cmos过程的双金属栅极晶体管 - Google Patents

用于cmos过程的双金属栅极晶体管 Download PDF

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CN1443367A
CN1443367A CN01811029A CN01811029A CN1443367A CN 1443367 A CN1443367 A CN 1443367A CN 01811029 A CN01811029 A CN 01811029A CN 01811029 A CN01811029 A CN 01811029A CN 1443367 A CN1443367 A CN 1443367A
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素查里塔·马德胡卡
比奇·云·恩古云
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Abstract

公开了一种用于在一个半导体基片(102)中形成第一导电类型的第一晶体管(130)和第二导电类型的第二晶体管(132)的过程。该基片(102)具有第一导电类型的第一孔道(106)和第二导电类型的第二孔道(104)。一个栅极电介质(108)形成于各孔道上。一层第一金属层(110)然后形成于栅极电介质(108)上。第一金属层(110)中位于第二孔道上的部分然后被去除。然后在各孔道上形成一层不同于所述第一金属的第二金属层(114)并且在第二金属(114)上形成一个栅极掩膜。各金属层(110、114)然后被形成图形以便将第一栅极遗留于第一孔道(106)上及第二栅极遗留于第二孔道(104)上。源极/漏极(138、142)然后被形成于第一(106)和第二(104)孔道上以便形成第一(130)和第二(132)晶体管。

Description

用于CMOS过程的双金属栅极晶体管
技术领域
本发明涉及半导体制造领域，更具体地涉及一种包括为n沟道和p沟道器件区别不同栅极金属的制造过程。
背景技术
在半导体制造领域中，通常希望制造具有匹配阈值电压的n沟道和p沟道半导体。此外，希望n沟道和p沟道阈值电压的绝对值接近零值以便增加器件速度。在传统半导体处理过程中，n沟道和p沟道阈值电压通常是通过一个多晶硅栅极的沟道注入和选择性掺杂的组合操作而进行调整的。通常沟道注入对n沟道器件的阈值电压调整是有效的，但对p沟道器件不太有效。此外，多晶硅栅极结构的使用变为不可取，因为栅极电介质厚度在不断减少。更具体地，硼从p型多晶硅栅极到晶体管沟道中的扩散以及与具有低热预算和薄栅极氧化物的器件相关联的多耗尽效应更难于将多晶硅栅极包括入先进技术中。此外，由于半导体处理过程与作为栅极电介质的氧化硅的使用相差甚远，多晶硅与选代的栅极电介质结构之间的化学反应使多晶硅更不适合于被选用作栅极。因此，非常希望实施一种制造过程，其中n沟道和p沟道阈值电压是匹配的而且满意地低。此外，希望该实施的过程与选代的栅极电介质材料相匹配。
附图说明
本发明通过例子进行阐述而不限于附图，附图中相同参考数字标示类似元件，及附图中：
图1是根据本发明实施例的部分地完成的半导体器件的部分剖面图；
图2是随于图1之后的处理步骤，其中一层第一栅极金属被从半导体器件的各部分中选择性地去除；
图3是随于图2之后的部分剖面图，其中一层第二栅极金属被淀积于第一栅极金属之上；；
图4是随于图3之后的处理步骤，其中淀积的金属被形成图形为栅极结构；
图5是随于图4之后的处理步骤，其中已经形成n沟道和p沟道半导体；及
图6A至6E阐述用于形成根据本发明实施例的半导体器件的选代处理过程流。
专业人员知道图中的元件只是为了阐述简单和清晰而没有按照比例画出。例如，图中的某些元件可能相对于其他元件被放大以便有助于理解本发明实施例。
具体实施方式
现在转向附图，图1-5阐述根据本发明的半导体处理过程的一个实施例中不同阶段的剖面图。在图1中阐述一个部分地完成的半导体器件100。被阐述于图1中的半导体器件100包括一片半导体基片102，在其中已经形成一个第一井104和一个第二井106。通常半导体器件102包括一个轻度掺杂的n型或p型单晶硅。使用一个双孔道过程制造所阐述的半导体器件100实施例，其中第一井104被选择性地注入基片102中将要形成第一导电类型器件的部分，而第二井106被选择性地注入基片102中将要形成第二导电类型晶体管的部分。在双孔道处理过程的实施例中，第一井104本身可以被包含于一个桶状沟道(未示出)中，其中第一井104和桶状孔道的导电类型是相反的。在另一个实施例中，基片102可以包括一层形成于一个重度掺杂堆上的轻度掺杂外延层。在一个实施例中，例如基片102的所阐述部分是一层形成于一个p+堆上的的p-外延层，而第一井104被掺杂为n型及第二井106是p型。N型电导率结构可以使用一个合适的n型杂质例如磷或砷注入半导体基片102而形成，而p型结构可以使用一个合适的p型杂质例如硼注入而形成。如图1中所示，第一井104和第二井106由沟隔离结构112彼此隔离。沟隔离结构112可以包括一个合适的绝缘物例如介质材料。在半导体器件100的阐述性实施例中，第一和第二井104和106由一个中间隔离介质结构112在物理上彼此隔离。隔离介质112可以包括一个氧化物、氮化物或其他合适的电气绝缘材料。
一层栅极电介质108形成于基片102的第一和第二井104和106上。在一个实施例中，栅极电介质108包括一层传统热形成的厚度优选地小于10纳米的氧化硅。在另一个实施例中，栅极电介质108可以包括一个选代的栅极材料例如渡越金属氧化物材料。由于这类选代的栅极电介质材料的高介质常数(K)，它们是合适的，允许使用较厚栅极电介质层而不会影响薄膜的电气和电容性特性。从锆、铪、铝、镧、锶、钛、硅的氧化物及其组合中选出的合适的渡越金属氧化物的混合材料可以用作这些选代的栅极电介质。
如图1中进一步描述的，第一金属型的第一金属110被淀积于栅极电介质108上。如以下更详细地描述的，第一金属110将被从半导体基片102的一部分中去除，在该部分中一种导电类型的晶体管被制造以使第一金属110只存在于其他导电类型晶体管存在的地方。优选地，使用化学蒸汽淀积(CVD)过程淀积第一金属110以便保护栅极电介质薄膜108的完整性。在选代的实施例中，第一金属110可以在使用溅射过程的物理蒸汽进行淀积。在第一金属110最终遗留于p型晶体管上的实施例中，希望第一金属型具有一个接近于硅的价带的工作性能。在此实施例中，合适的用于第一金属110的金属包括铼(Re)、铱(Ir)、铂(Pt)和氧化钌(RuO2)。在第一金属110遗留在n型晶体管上的实施例中，希望第一金属110具有接近于硅的导带的工作性能。在此实施例中，合适的用于第一金属110的金属包括钛(Ti)、钒(V)、锆(Zr)、钼(Mo)、钽(Ta)、铝(Al)、铌(Nb)、和氮化钽(TaN)。
现在转向图2，第一金属110的一部分已经被选择性地去除。在所阐述的实施例中，使用一个掩膜和一个使用在形成第二井106中使用的孔道掩膜的蚀刻过程来完成第一金属110的选择性去除。在此实施例中，在第二井106(其中将最终制造第二型晶体管的部分)上的第一金属110被去除。因此，在完成晶体管形成过程之后，第一金属110将遗留在第一导电类型晶体管结构中，而第一金属110将不会出现于第二导电类型晶体管中。希望使用一个临界尺寸(CD)容忍掩膜例如第二孔道掩膜以便形成如图2中所示被选择性地去除的第一金属110，因为随后处理过程中掩膜的对准误差将不会产生坏影响。
现在转向图3，在半导体基片102的第一和第二井104和106上形成一层第二金属114，从而覆盖第一金属110和栅极电介质108的暴露部分。第二金属114属于第二金属型，它具有与用作第一金属110的第一金属不同的工作性能。在其中用作第一金属110的第一金属型具有一个接近于硅价带的工作性能的实施例中，用作第二金属114的第二金属型具有一个接近于硅导带的工作性能。相反，在其中用作第一金属110的第一金属型具有一个接近于硅导带的工作性能的实施例中，用作第二金属114的第二金属型具有一个接近于硅价带的工作性能。
优选地，第一金属110和第二金属114被如此形成以使具有接近于导带工作性能的金属型与p孔道区上的栅极电介质108接触。换言之，希望n沟道晶体管在栅极电介质108上包括一层具有接近于硅导带工作性能的金属，而p型晶体管则制造为在栅极电介质108上具有一层具有接近于硅价带工作性能的金属。如果例如第一井104是一个在其上制造p型晶体管的n孔道结构，则第一金属110的工作性能优选地接近于硅价带，而基片102的p孔道区上的栅极电介质108上的第二金属114则具有接近于硅导带的工作性能。
第二金属114优选地厚于第一金属110。在一个实施例中，第二金属114的厚度至少是第一金属110厚度的两倍，而更优选地至少是十倍。一个实施例中的第一金属110的厚度小于大约100，而第二金属114厚度的范围为大约200-2000。如同第一金属110，第二金属114优选地使用CVD淀积过程形成以便保护第二金属114淀积期间介质薄膜108各部分的完整性。
现在转向图4，其中显示已经完成栅极掩膜和蚀刻过程之后的半导体器件100，第一金属层110和第二金属层114被形成图形，其结果是在第一井104上形成第一栅极120和在第二井106上形成第二栅极122。第一栅极120包括栅极电介质108上的一层第一金属110和形成于第一金属110上的第二金属114。相反，第二栅极122包括与栅极电介质108接触的第二金属114。因为第二金属114的厚度比第一金属110厚度高一个数量级，第一和第二栅极120和122在物理尺寸上基本类似，从而将由于厚度差别而引起的处理困难减至最小。本公开内容的专业人员知道，把在第一导电类型晶体管中使用与栅极电介质108接触的第一金属型的第一金属110和在第二导电类型晶体管中使用与栅极电介质层108接触的第二金属型的第二金属114(其中第一和第二金属型不同)这两者结合起来的优点是，能够将n沟道和p沟道器件的阈值对准而避免那些与多晶硅栅极极相关联的困难，包括硼扩散、多晶硅耗尽效应以及和选代的栅极电介质薄膜的电位不兼容性。因为在形成第一和第二栅极120和122之前第一金属110已从基片102的合适部分中去除，只需要单个掩膜和蚀刻步骤来形成第一和第二栅极120和122。因此，第一栅极120的第一和第二金属是自身对准的。此外，本发明在实施中不会引入第一和第二栅极120和122之间的误对准，而误对准将会影响随后的光刻步骤。由于第一栅极120的所阐述实施例包括两层金属和第二栅极122包括单层金属，附加金属或其他导电元件可以被加至每个栅极叠层上以使例如第一栅极120包括一个三层叠层而第二栅极122包括一个二层叠层。在这类实施例中，第一栅极120可以包括一层铂第一金属110、一层氮化钽(TaN)第二金属114以及一层钨(W)第三金属(图4中未示出)。在此实施例中，第二栅极114将包括一层TaN第一金属和一层W第二金属。第三金属层也可使用另一种导电材料例如掺杂多晶硅来实施。
现在转向图5，已经完成与本公开内容相关的半导体器件100部分，其中制造了第一导电类型的第一晶体管130和第二导电类型的第二晶体管132。第一晶体管130是通过完成合适的源极/漏极注入和制造合适的侧壁结构而制造的。在所阐述的实施例中，如同半导体处理领域中类似过程，第一晶体管130包括一个在形成侧壁136之前的轻度掺杂漏极(LDD)134和随后注入一个重度掺杂杂质分布以便形成源极/漏极区138。
类似地，第二晶体管132是通过注入轻度掺杂杂质分布140、制造侧壁136和随后注入一个重度掺杂杂质源极/漏极区142而形成的，以及在第一晶体管130为p型晶体管的实施例中，杂质分布134和138是硼的p型杂质分布或其他合适的p型掺杂剂。在第一晶体管130为n型晶体管的实施例中，杂质分布134和138是磷、砷的n型杂质分布或其他合适的n型掺杂剂。侧壁136优选地包括一种介质材料例如氮化硅。
如图5中所示的半导体器件100还包括一层层间介质层150以及连至源极/漏极区138的一对触点152和连至第一栅极120和第二栅极122的一对触点154。触点154和152通常包括第三金属例如钨。
可以使用选代的制造技术或过程流制造半导体器件100，例如替代栅极制造技术，其中在形成栅极电介质108和第一金属110之前注入源极/漏极区。在此技术中，如图6A至6E中所示，将替代栅极结构160用作一个注入掩膜而将源极/漏极区138和142注入基片102。使用栅极掩膜在一层氧化物薄膜161上将替代栅极结构160形成图形。替代栅极结构160通常包括一种相对于氧化硅具有好的蚀刻选择性的材料例如多晶硅。
在形成替代栅极160之后，以如下步骤制造结构162，在基片上敷层淀积一层薄膜例如CVD氧化物，然后将淀积的层抛光以便暴露替代栅极162的上表面(图6B)。在图6C中，替代栅极160被蚀刻掉而只遗留结构162。在图6D中，栅极电介质被形成于整个晶片上，及如上所述，第一金属110被选择性地形成于p沟道区上。在图6E和6F中，第二金属114和第三金属116被淀积以及由栅极氧化物108、第一金属110、第二金属114和第三金属116组成的叠层被蚀刻以便形成栅极结构118。在一个实施例中，第一金属110、第二金属114和第三金属116分别是铂、氮化钽和钨。在此例中，栅极结构118在它们相应的源极/漏极上延伸。栅极位于沟道之上并且邻近于源极/漏极而延伸。该延伸部分和栅极构成栅极结构118。
此处描述的替代栅极技术有利地在分别淀积栅极电介质、第一和第二金属层110和112之前进行源极/漏极注入和掺杂剂活性退火。此过程的一个优点是在淀积介质和金属层之前进行高温掺杂剂活性退火，这本来可能会影响栅极电介质和第一和第二金属的质量。
虽然本发明已经结合具体的导电类型或电位极性进行描述，但专业人员知道导电类型和电位极性是可以反置的。
在以上说明中，已经参考具体实施例描述本发明。然而，专业人员知道，能够在不背离以下权利要求书中所述本发明的范围的情况下作出不同修改和变动。因此，说明书和附图应该被认为是阐述性而非限制性的，及所有这类修改意在被包括于本发明的范围之内。
已经结合具体实施例描述了好处、其他优点和问题解决方法。然而好处、其他优点、问题解决方法和任何能够实现任何好处、优点或问题解决方法的(各)元件不应被理解为一个重要的、需要的或主要的特征或权利要求书中的任何或所有项目的元件。如此处所用，“包括”、“构成”项或任何其对应内容意在包含一个非专一的包含内容，以使一个包括一系列元件的过程、方法、物件或设备只是不包括这些元件，但可以包括没有明显地列出的或者这类过程、方法、物件或设备所固有的其他元件。

Claims (16)

1.一种用于在一个具有第一导电类型的第一井和第二导电类型的第二井的半导体基片中形成第一导电类型的第一晶体管和第二导电类型的第二晶体管的方法，包括以下步骤：
在第一和第二井上形成一个栅极电介质；
在栅极电介质上形成一层第一金属类型的第一金属层；
去除第一金属层的一个第一部分，该第一部分位于第二井上；
然后在第一和第二井上形成一层不同于所述第一金属类型的第二金属类型的第二金属层；
在第一井和第二井上形成一个栅极掩膜；
根据该掩膜将第一金属层和第二金属层形成图案以便将一个第一栅极留于第一井上并把一个第二栅极留于第二井上；
在邻近于第一栅极的第一井中形成第二导电类型的第一源极和第一漏极以便形成第二晶体管；及
在邻近于第二栅极的第二井中形成第一导电类型的第二源极和第二漏极以便形成第一晶体管。
2.一种具有第一导电类型的第一井和第二导电类型的第二井的半导体基片中的半导体器件，包括：
一个栅极电介质，位于第一井和第二井的至少一部分之上；
一个第一栅极，位于第一井和栅极电介质之上，该第一栅极具有第一金属类型的第一区和不同于第一金属类型的第二金属类型的第二区，该第一区位于栅极电介质之上；
一个第一源极和第一漏极，它们形成于邻近于第一栅极的第一井中；
一个第二栅极，位于第二井和栅极电介质之上，该第二栅极具有第二金属类型，该第二金属类型不同于第一金属类型；
一个第二源极和第二漏极，它们形成于邻近于第二栅极的第二井中。
3.权利要求2的半导体器件，其中第一区具有第一厚度和第二区具有第二厚度，及其中第二厚度至少两倍大于第一厚度。
4.权利要求2的半导体器件，其中栅极电介质是一种渡越金属氧化物。
5.权利要求4的半导体器件，其中第一层具有第一厚度和第二层具有第二厚度，及其中第二厚度大于第一厚度。
6.权利要求5的半导体器件，其中第二厚度至少两倍大于第一厚度。
7.权利要求6的半导体器件，其中第一金属类型是氮化钽。
8.权利要求7的半导体器件，其中第二金属类型是铂。
9.一种用于在一个具有第一导电类型的第一井和第二导电类型的第二井的半导体基片中形成第一导电类型的第一晶体管和第二导电类型的第二晶体管的方法，包括以下步骤：
在第一井上形成第一可移动栅极和在第二井上形成第二可移动栅极；
在邻近于第一可移动栅极的第一井中形成第二导电类型的第一源极和第一漏极；
在邻近于第二可移动栅极的第二井中形成第一导电类型的第二源极和第二漏极；
去除第一和第二可移动栅极；
在第一和第二井上形成一个栅极电介质；
在栅极电介质上形成一层第一金属类型的第一金属层；
去除第一金属层的第一部分，该第一金属层的第一部分位于第二井上；
然后在所述第一和第二井上形成一层不同于所述第一金属类型的第二金属类型的第二金属层；
去除第二金属层的第一部分，该第二金属层的第一部分位于第一与第二井之间；
以此方式在第二井中形成第一晶体管及在第一井中形成第二晶体管。
10.权利要求9的方法，其中栅极电介质是一种渡越金属氧化物。
11.权利要求9的方法，其中第一层具有第一厚度和第二层具有第二厚度，及其中第二厚度大于第一厚度。
12.权利要求11的方法，其中第二厚度至少两倍大于第一厚度。
13.权利要求12的方法，其中形成第一金属层的步骤包括使用化学蒸汽淀积来淀积氮化钽。
14.权利要求12的方法，其中形成第二金属层的步骤包括使用化学蒸汽淀积来淀积铂。
15.权利要求14的方法，其中渡越金属氧化物选自锆、铪、铝、镧、硅、钛的氧化物及其组合中。
16.权利要求1的方法，其中第一金属类型选自氮化钽、铌、铝、钽、钼、和锆、钒、和钛。
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