JP2007123548A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 97
- 229910052751 metal Inorganic materials 0.000 claims abstract description 97
- 238000001039 wet etching Methods 0.000 claims abstract description 52
- 239000000126 substance Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims description 112
- 230000015572 biosynthetic process Effects 0.000 claims description 40
- 238000001312 dry etching Methods 0.000 claims description 34
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 32
- 229920005591 polysilicon Polymers 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 21
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 14
- 239000002253 acid Substances 0.000 claims description 9
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 4
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- NLXLAEXVIDQMFP-UHFFFAOYSA-N Ammonium chloride Substances [NH4+].[Cl-] NLXLAEXVIDQMFP-UHFFFAOYSA-N 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 28
- 239000000243 solution Substances 0.000 description 27
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 9
- 238000004140 cleaning Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 4
- 239000011259 mixed solution Substances 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 229910017604 nitric acid Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910004542 HfN Inorganic materials 0.000 description 1
- 229910019899 RuO Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000008155 medical solution Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
- H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
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Abstract
【解決手段】 本発明に係わる半導体装置の製造方法では、ゲート絶縁膜3上に、ゲート電極を構成するメタル膜4を形成する。その後、当該メタル膜4を加工する際に、所定の薬液を用いたウエットエッチング処理により、当該メタル膜4の一部を除去する。
【選択図】図5
Description
本実施の形態に係わる半導体装置の製造方法を、工程断面図を用いて説明する。なお、以下では、nFET(n型の電界効果トランジスタ)とpFET(p型の電界効果トランジスタ)とが同一半導体基板に形成された半導体装置の製造方法に対して、本発明を適用する場合について説明する。
実施の形態1において、メタル膜4として、TiN膜4aとTi膜4bとが当該順に積層された積層膜を採用する場合について言及した(図7参照)。以下、メタル膜4として、TiN膜4aとTi膜4bとから成る積層膜を採用した場合における、半導体装置の製造方法について説明する。
本実施の形態に係わる半導体装置の製造方法は、実施の形態1で説明した図5の構造から図6の構造に至る工程に関するものである。
Claims (6)
- (A)半導体基板上にゲート絶縁膜を形成する工程と、
(B)前記ゲート絶縁膜上に、ゲート電極を構成するメタル膜を形成する工程と、
(C)所定の薬液を用いたウエットエッチング処理により、前記メタル膜の一部を除去する工程とを、備えている、
ことを特徴とする半導体装置の製造方法。 - 前記半導体基板は、nFET形成領域とpFET形成領域とを有しており、
前記工程(C)は、
前記nFET形成領域に存する前記メタル膜を除去する工程である、
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - (D)前記工程(C)の後に、前記ゲート絶縁膜および前記メタル膜を覆うように、前記半導体基板上にポリシリコン膜を形成する工程と、
(E)前記ポリシリコン膜に対してドライエッチング処理を施し、前記メタル膜に到達した段階で当該ドライエッチング処理を止めることにより、前記ポリシリコン膜の一部を除去する工程と、
(F)前記所定の薬液を用いたウエットエッチング処理により、前記pFET形成領域に存する前記メタル膜の一部を除去する工程とを、さらに備えている、
ことを特徴とする請求項2に記載の半導体装置の製造方法。 - 前記工程(B)は、
第一のメタル膜と少なくともシリコンを含む第二のメタル膜とが、当該順に積層された積層膜である前記メタル膜を形成する工程であり、
前記工程(E)は、
前記ポリシリコン膜および前記第二のメタル膜に対してドライエッチング処理を施し、前記第一のメタル膜に到達した段階で当該ドライエッチング処理を止めることにより、前記ポリシリコン膜の一部および前記第二のメタル膜の一部を除去する工程であり、
前記工程(F)は、
前記ウエットエッチング処理により、前記第一のメタル膜の一部を除去する工程である、
ことを特徴とする請求項3に記載の半導体装置の製造方法。 - 前記工程(C)は、
前記所定の薬液として、過酸化水素水、混酸、過酸化水素水+アンモニア水、および過酸化水素水+混酸のいずれかを用いる工程である、
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記工程(B)は、
TiN、Tiが当該順に積層された積層膜である、メタル膜を形成する工程であり、
前記工程(C)は、
前記所定の薬液として、温度が50℃以上の過酸化水素水を用いる工程である、
ことを特徴とする請求項1に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2005313635A JP2007123548A (ja) | 2005-10-28 | 2005-10-28 | 半導体装置の製造方法 |
US11/551,861 US7537987B2 (en) | 2005-10-28 | 2006-10-23 | Semiconductor device manufacturing method |
CNA2006101436583A CN1956152A (zh) | 2005-10-28 | 2006-10-27 | 半导体装置的制造方法 |
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JP2005313635A JP2007123548A (ja) | 2005-10-28 | 2005-10-28 | 半導体装置の製造方法 |
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JP2007123548A true JP2007123548A (ja) | 2007-05-17 |
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JP2005313635A Pending JP2007123548A (ja) | 2005-10-28 | 2005-10-28 | 半導体装置の製造方法 |
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US (1) | US7537987B2 (ja) |
JP (1) | JP2007123548A (ja) |
CN (1) | CN1956152A (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009044051A (ja) * | 2007-08-10 | 2009-02-26 | Panasonic Corp | 半導体装置及びその製造方法 |
WO2009150770A1 (ja) * | 2008-06-09 | 2009-12-17 | パナソニック株式会社 | 半導体装置 |
WO2010150331A1 (ja) * | 2009-06-24 | 2010-12-29 | パナソニック株式会社 | 半導体装置およびその製造方法 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7790624B2 (en) * | 2008-07-16 | 2010-09-07 | Global Foundries Inc. | Methods for removing a metal-comprising material from a semiconductor substrate |
TWI371085B (en) * | 2008-08-12 | 2012-08-21 | Vanguard Int Semiconduct Corp | Fabrication methods for integration cmos and bjt devices |
CN104538308A (zh) * | 2014-12-25 | 2015-04-22 | 上海芯亮电子科技有限公司 | 降低功率晶体管导通电阻的方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002289700A (ja) * | 2000-12-29 | 2002-10-04 | Hynix Semiconductor Inc | 半導体素子のデュアルゲート製造方法 |
JP2004503932A (ja) * | 2000-06-12 | 2004-02-05 | モトローラ・インコーポレイテッド | Cmosプロセスのためのデュアルメタルゲートトランジスタ |
WO2004093182A1 (en) * | 2003-04-09 | 2004-10-28 | Freescale Semiconductor, Inc. | Process for forming dual metal gate structures |
JP2005123625A (ja) * | 2003-10-17 | 2005-05-12 | Interuniv Micro Electronica Centrum Vzw | シリサイド化された電極を有する半導体装置の製造方法 |
JP2005142539A (ja) * | 2003-10-17 | 2005-06-02 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP2006523008A (ja) * | 2001-05-26 | 2006-10-05 | フリースケール セミコンダクター インコーポレイテッド | 半導体素子とその作製法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5258095A (en) * | 1989-01-20 | 1993-11-02 | Fujitsu Limited | Method for producing a device having an insulator sandwiched between two semiconductor layers |
US6258729B1 (en) * | 1999-09-02 | 2001-07-10 | Micron Technology, Inc. | Oxide etching method and structures resulting from same |
US7316950B2 (en) | 2003-04-22 | 2008-01-08 | National University Of Singapore | Method of fabricating a CMOS device with dual metal gate electrodes |
US7005330B2 (en) * | 2003-06-27 | 2006-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for forming the gate electrode in a multiple-gate transistor |
JP3790237B2 (ja) | 2003-08-26 | 2006-06-28 | 株式会社東芝 | 半導体装置の製造方法 |
US20070152276A1 (en) * | 2005-12-30 | 2007-07-05 | International Business Machines Corporation | High performance CMOS circuits, and methods for fabricating the same |
US7605077B2 (en) * | 2006-03-29 | 2009-10-20 | International Business Machines Corporation | Dual metal integration scheme based on full silicidation of the gate electrode |
JP2007288096A (ja) * | 2006-04-20 | 2007-11-01 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
-
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- 2005-10-28 JP JP2005313635A patent/JP2007123548A/ja active Pending
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- 2006-10-23 US US11/551,861 patent/US7537987B2/en not_active Expired - Fee Related
- 2006-10-27 CN CNA2006101436583A patent/CN1956152A/zh active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004503932A (ja) * | 2000-06-12 | 2004-02-05 | モトローラ・インコーポレイテッド | Cmosプロセスのためのデュアルメタルゲートトランジスタ |
JP2002289700A (ja) * | 2000-12-29 | 2002-10-04 | Hynix Semiconductor Inc | 半導体素子のデュアルゲート製造方法 |
JP2006523008A (ja) * | 2001-05-26 | 2006-10-05 | フリースケール セミコンダクター インコーポレイテッド | 半導体素子とその作製法 |
WO2004093182A1 (en) * | 2003-04-09 | 2004-10-28 | Freescale Semiconductor, Inc. | Process for forming dual metal gate structures |
JP2005123625A (ja) * | 2003-10-17 | 2005-05-12 | Interuniv Micro Electronica Centrum Vzw | シリサイド化された電極を有する半導体装置の製造方法 |
JP2005142539A (ja) * | 2003-10-17 | 2005-06-02 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009044051A (ja) * | 2007-08-10 | 2009-02-26 | Panasonic Corp | 半導体装置及びその製造方法 |
WO2009150770A1 (ja) * | 2008-06-09 | 2009-12-17 | パナソニック株式会社 | 半導体装置 |
WO2010150331A1 (ja) * | 2009-06-24 | 2010-12-29 | パナソニック株式会社 | 半導体装置およびその製造方法 |
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US20070099406A1 (en) | 2007-05-03 |
US7537987B2 (en) | 2009-05-26 |
CN1956152A (zh) | 2007-05-02 |
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