JP5401244B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5401244B2 JP5401244B2 JP2009229225A JP2009229225A JP5401244B2 JP 5401244 B2 JP5401244 B2 JP 5401244B2 JP 2009229225 A JP2009229225 A JP 2009229225A JP 2009229225 A JP2009229225 A JP 2009229225A JP 5401244 B2 JP5401244 B2 JP 5401244B2
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- insulating film
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Description
本実施の形態の半導体装置を図面を参照して説明する。
本実施の形態では、上記ステップS6(Hf含有絶縁膜4a,4b形成工程)の工程の他の例について説明する。図22は、上記ステップS6(Hf含有絶縁膜4a,4b形成工程)の他の例(すなわち本実施の形態2)を示す製造プロセスフロー図であり、上記実施の形態1の上記図3に対応するものである。また、図23〜図28は、本実施の形態の半導体装置の製造工程中の要部断面図である。
1A nMIS形成領域
1B pMIS形成領域
2 素子分離領域
3 界面層
4 Hf含有膜
4a,4b Hf含有絶縁膜
5 Al含有膜
6 La含有膜
7 金属膜
8 シリコン膜
9 絶縁膜
11 絶縁膜
12 ストッパ絶縁膜
13 絶縁膜
14 配線溝
21 エッチング残渣または堆積物(反応生成物)
31 マスク層
CNT コンタクトホール
EX1 n−型半導体領域
EX2 p−型半導体領域
GE1,GE2 ゲート電極
M1 配線
NW n型ウエル
PG プラグ
PW p型ウエル
Qn nチャネル型MISFET
Qp pチャネル型MISFET
SD1 n+型半導体領域
SD2 p+型半導体領域
SW サイドウォール
Claims (16)
- nチャネル型の第1MISFETを半導体基板の第1領域に有し、pチャネル型の第2MISFETを前記半導体基板の第2領域に有する半導体装置の製造方法であって、
(a)前記半導体基板を用意する工程、
(b)ハフニウムとランタンと酸素とを主成分として含有する第1高誘電率ゲート絶縁膜を前記半導体基板上の前記第1領域に、ハフニウムとアルミニウムと酸素とを主成分として含有する第2高誘電率ゲート絶縁膜を前記半導体基板上の前記第2領域に、それぞれ形成する工程、
(c)前記第1領域の前記第1高誘電率ゲート絶縁膜および前記第2領域の前記第2高誘電率ゲート絶縁膜上に、金属膜を形成する工程、
(d)前記金属膜をドライエッチングによりパターニングして、前記第1領域に前記第1MISFETの第1メタルゲート電極を、前記第2領域に前記第2MISFETの第2メタルゲート電極を形成する工程、
(e)前記(d)工程後、前記第1領域における前記第1メタルゲート電極で覆われていない部分の前記第1高誘電率ゲート絶縁膜と、前記第2領域における前記第2メタルゲート電極で覆われていない部分の前記第2高誘電率ゲート絶縁膜とを、ウェットエッチングにより除去する工程、
を有し、
前記(e)工程は、
(e1)フッ酸を含有しない第1酸性溶液で前記半導体基板をウェット処理する工程、
(e2)アルカリ性溶液で前記半導体基板をウェット処理する工程、
(e3)前記(e1)および(e2)工程後、フッ酸を含有する第2酸性溶液で前記半導体基板をウェット処理する工程、
を含むことを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(d)工程では、前記第1領域における前記第1メタルゲート電極で覆われていない部分の前記第1高誘電率ゲート絶縁膜と、前記第2領域における前記第2メタルゲート電極で覆われていない部分の前記第2高誘電率ゲート絶縁膜とが露出されることを特徴とする半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記第1酸性溶液は、フッ酸と硫酸とを含有していないことを特徴とする半導体装置の製造方法。 - 請求項3記載の半導体装置の製造方法において、
前記第1酸性溶液は、塩酸の水溶液であることを特徴とする半導体装置の製造方法。 - 請求項4記載の半導体装置の製造方法において、
前記アルカリ性溶液はアンモニアの水溶液であることを特徴とする半導体装置の製造方法。 - 請求項5記載の半導体装置の製造方法において、
前記(c)工程後で、前記(d)工程前に、
(c1)前記金属膜上にシリコン膜を形成する工程、
を更に有し、
前記(d)工程では、前記シリコン膜および前記金属膜をドライエッチングによりパターニングして、前記第1領域に前記第1メタルゲート電極を、前記第2領域に前記第2メタルゲート電極を形成することを特徴とする半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記(e1)工程では、前記第1領域における前記第1メタルゲート電極で覆われていない部分の前記第1高誘電率ゲート絶縁膜の表層部分が除去され、
前記(e2)工程では、前記第2領域における前記第2メタルゲート電極で覆われていない部分の前記第2高誘電率ゲート絶縁膜の表層部分が除去され、
前記(e3)工程では、前記第1領域における前記第1メタルゲート電極で覆われていない部分の前記第1高誘電率ゲート絶縁膜の残存部分と、前記第2領域における前記第2メタルゲート電極で覆われていない部分の前記第2高誘電率ゲート絶縁膜の残存部分とが除去されることを特徴とする半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、
前記第2酸性溶液はフッ酸および塩酸の水溶液であることを特徴とする半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
前記(b)工程は、
(b1)前記半導体基板上の前記第1領域および前記第2領域に、前記第1および第2高誘電率ゲート絶縁膜形成用でかつハフニウムおよび酸素を主成分として含有する第1Hf含有膜を形成する工程、
(b2)前記第2領域の前記第1Hf含有膜上にAlを含有するAl含有膜を形成し、前記第1領域の前記第1Hf含有膜上にLaを含有するLa含有膜を形成する工程、
(b3)前記(b2)工程後、熱処理を行って、前記第1領域の前記第1Hf含有膜と前記La含有膜とを反応させて前記第1高誘電率ゲート絶縁膜を形成し、前記第2領域の前記第1Hf含有膜と前記Al含有膜とを反応させて前記第2高誘電率ゲート絶縁膜を形成する工程、
を含むことを特徴とする半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記La含有膜は、酸化ランタン膜であることを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記Al含有膜は、酸化アルミニウム膜、酸窒化アルミニウム膜またはアルミニウム膜であることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(b)工程前に、
(a1)前記半導体基板上の前記第1領域および前記第2領域に、酸化シリコンまたは酸窒化シリコンからなる第1絶縁膜を形成する工程、
を更に有し、
前記(b)工程では、前記第1領域の前記第1絶縁膜上に前記第1高誘電率ゲート絶縁膜を、前記第2領域の前記第1絶縁膜上に前記第2高誘電率ゲート絶縁膜を、それぞれ形成することを特徴とする半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記(e3)工程では、前記第1領域における前記第1メタルゲート電極で覆われていない部分の前記第1絶縁膜と、前記第2領域における前記第2メタルゲート電極で覆われていない部分の前記第1絶縁膜とが除去されることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(b)工程は、
(b11)前記半導体基板上の前記第1領域および前記第2領域に、前記第1および第2高誘電率ゲート絶縁膜形成用でかつハフニウムおよび酸素を主成分として含有する第1Hf含有膜を形成する工程、
(b12)前記第1および第2領域に形成された前記第1Hf含有膜上に、前記第2高誘電率ゲート絶縁膜形成用でかつAlを主成分として含有するAl含有膜を形成する工程、
(b13)前記第1および第2領域に形成された前記Al含有膜上にマスク層を形成する工程、
(b14)前記(b13)工程後、前記第1領域の前記マスク層および前記Al含有膜を除去し、前記第2領域の前記マスク層および前記Al含有膜を残す工程、
(b15)前記(b14)工程後、前記第1高誘電率ゲート絶縁膜形成用でかつLaを主成分として含有するLa含有膜を、前記第1領域の前記第1Hf含有膜上および前記第2領域の前記マスク層上に形成する工程、
(b16)前記(b15)工程後、熱処理を行って、前記第1領域の前記第1Hf含有膜と前記La含有膜とを反応させて前記第1高誘電率ゲート絶縁膜を形成し、前記第2領域の前記第1Hf含有膜と前記Al含有膜とを反応させて前記第2高誘電率ゲート絶縁膜を形成する工程、
(b17)前記(b16)工程後、前記第2領域の前記マスク層上の前記La含有膜と前記マスク層とを除去する工程、
を含むことを特徴とする半導体装置の製造方法。 - 請求項14記載の半導体装置の製造方法において、
前記(b13)工程で形成された前記マスク層は、窒化金属膜または炭化金属膜であることを特徴とする半導体装置の製造方法。 - 請求項15記載の半導体装置の製造方法において、
前記(b11)工程で形成される前記第1Hf含有膜は、HfO膜、HfON膜、HfSiO膜またはHfSiON膜であり、
前記(b12)工程で形成される前記Al含有膜は、酸化アルミニウム膜、酸窒化アルミニウム膜またはアルミニウム膜であり、
前記(b15)工程で形成される前記La含有膜は、酸化ランタン膜であることを特徴とする半導体装置の製造方法。
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JP2009177007A (ja) * | 2008-01-25 | 2009-08-06 | Panasonic Corp | 絶縁膜のエッチング方法 |
JP2011003664A (ja) * | 2009-06-17 | 2011-01-06 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
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