WO2011042955A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- WO2011042955A1 WO2011042955A1 PCT/JP2009/067421 JP2009067421W WO2011042955A1 WO 2011042955 A1 WO2011042955 A1 WO 2011042955A1 JP 2009067421 W JP2009067421 W JP 2009067421W WO 2011042955 A1 WO2011042955 A1 WO 2011042955A1
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- rare earth
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 407
- 238000000034 method Methods 0.000 title claims abstract description 75
- 229910052761 rare earth metal Inorganic materials 0.000 claims abstract description 310
- 229910052751 metal Inorganic materials 0.000 claims abstract description 228
- 239000002184 metal Substances 0.000 claims abstract description 228
- 150000002910 rare earth metals Chemical class 0.000 claims abstract description 188
- 229910052735 hafnium Inorganic materials 0.000 claims abstract description 94
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims abstract description 92
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 90
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 89
- 239000001301 oxygen Substances 0.000 claims abstract description 89
- 239000000758 substrate Substances 0.000 claims description 115
- 238000004519 manufacturing process Methods 0.000 claims description 107
- 238000009826 distribution Methods 0.000 claims description 104
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 103
- 229910052710 silicon Inorganic materials 0.000 claims description 103
- 239000010703 silicon Substances 0.000 claims description 103
- 238000010438 heat treatment Methods 0.000 claims description 79
- 238000006243 chemical reaction Methods 0.000 claims description 72
- 229910052782 aluminium Inorganic materials 0.000 claims description 54
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 51
- 238000005468 ion implantation Methods 0.000 claims description 41
- 230000008569 process Effects 0.000 claims description 36
- 239000012535 impurity Substances 0.000 claims description 31
- 229910004143 HfON Inorganic materials 0.000 claims description 27
- 229910004129 HfSiO Inorganic materials 0.000 claims description 27
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- 229910001404 rare earth metal oxide Inorganic materials 0.000 claims description 23
- 229910052746 lanthanum Inorganic materials 0.000 claims description 12
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical group [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 12
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 8
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims description 4
- 239000010408 film Substances 0.000 description 1636
- 239000010410 layer Substances 0.000 description 189
- 230000015572 biosynthetic process Effects 0.000 description 125
- 239000000203 mixture Substances 0.000 description 42
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 38
- 229910021332 silicide Inorganic materials 0.000 description 26
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 26
- 230000000052 comparative effect Effects 0.000 description 23
- 238000009792 diffusion process Methods 0.000 description 21
- 229920002120 photoresistant polymer Polymers 0.000 description 21
- 229910052757 nitrogen Inorganic materials 0.000 description 19
- 238000000137 annealing Methods 0.000 description 18
- 230000007423 decrease Effects 0.000 description 18
- 239000011810 insulating material Substances 0.000 description 18
- 238000002156 mixing Methods 0.000 description 17
- 230000004913 activation Effects 0.000 description 16
- 238000005530 etching Methods 0.000 description 15
- 239000004020 conductor Substances 0.000 description 14
- 238000001039 wet etching Methods 0.000 description 13
- 239000000463 material Substances 0.000 description 12
- 229910000449 hafnium oxide Inorganic materials 0.000 description 11
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 11
- 230000000694 effects Effects 0.000 description 10
- 125000005843 halogen group Chemical group 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 9
- 238000002955 isolation Methods 0.000 description 9
- 239000012528 membrane Substances 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 238000005121 nitriding Methods 0.000 description 9
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000012212 insulator Substances 0.000 description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 7
- 239000012298 atmosphere Substances 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 229910003855 HfAlO Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000003247 decreasing effect Effects 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000009828 non-uniform distribution Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 4
- 229910003468 tantalcarbide Inorganic materials 0.000 description 4
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 4
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 4
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 3
- 239000011261 inert gas Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000007800 oxidant agent Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910017109 AlON Inorganic materials 0.000 description 1
- -1 Co (cobalt) Chemical compound 0.000 description 1
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- 229910052765 Lutetium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052747 lanthanoid Inorganic materials 0.000 description 1
- 150000002602 lanthanoids Chemical class 0.000 description 1
- OHSVLFRHMCKCQY-UHFFFAOYSA-N lutetium atom Chemical compound [Lu] OHSVLFRHMCKCQY-UHFFFAOYSA-N 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 229910052706 scandium Inorganic materials 0.000 description 1
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02192—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02194—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing more than one metal element
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
Definitions
- the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a MISFET having a high dielectric constant gate insulating film and a metal gate electrode and a technology effective when applied to the manufacturing technology.
- a MISFET Metal Insulator Semiconductor ⁇ Field Effect Transistor
- a gate insulating film on a semiconductor substrate, forming a gate electrode on the gate insulating film, and forming source / drain regions by ion implantation or the like. it can.
- a gate electrode a polysilicon film is generally used.
- the gate insulating film has been made thinner, and the influence of depletion of the gate electrode when a polysilicon film is used as the gate electrode cannot be ignored. For this reason, there is a technique for suppressing the depletion phenomenon of the gate electrode by using a metal gate electrode as the gate electrode.
- the gate insulating film has been made thinner, and when a thin silicon oxide film is used as the gate insulating film, the electrons flowing through the channel of the MISFET tunnel through the barrier formed by the silicon oxide film to form the gate. A so-called tunnel current flowing in the electrode is generated. Therefore, by using a material having a higher dielectric constant than the silicon oxide film (high dielectric constant material) as the gate insulating film, the leakage current is reduced by increasing the physical film thickness even if the capacitance is the same. There is technology.
- Patent Document 1 describes a technique in which an AlO film, an HfAlO film, and an AlO film are laminated to form a high dielectric constant insulating film having a laminated structure.
- Patent Document 1 also describes a high dielectric constant insulating film in which an AlO film, a LaO film, and an AlO film are stacked.
- Al and oxygen are the main components as a high dielectric constant insulating film, and a leakage current is too high as a high dielectric gate insulating film for a 32-22 nm node. Therefore, there is a problem in application.
- Patent Document 2 a Si nitride film exists at the interface between the High-k film and the Si substrate, and nitrogen is applied to the interface between the High-k film and the TiN / Al metal gate film.
- a technique is described in which a CVD-HfO 2 film is present.
- the problem of depletion of the gate electrode can be solved, but the absolute value of the threshold voltage (threshold value) of the MISFET becomes larger than when the polysilicon gate electrode is used.
- the absolute value of the threshold voltage becomes large in both the n-channel MISFET and the p-channel MISFET. For this reason, when a metal gate electrode is applied, it is desired to lower the threshold value (decrease the absolute value of the threshold voltage).
- an Hf-based gate insulating film that is a high-dielectric constant film containing Hf is excellent.
- a rare earth element is used as an Hf-based gate insulating film in an n-channel MISFET.
- an element particularly preferably lanthanum
- the threshold value of the n-channel MISFET can be lowered.
- aluminum is introduced into the Hf-based gate insulating film in the p-channel type MISFET, the threshold value of the p-channel type MISFET can be lowered.
- the rare earth element when a rare earth element is introduced into the Hf-based gate insulating film, the rare earth element is likely to diffuse to the metal gate electrode or the semiconductor substrate side, which may cause various problems. For example, if the rare earth element diffuses into the metal gate electrode, the effective work function of the metal gate electrode changes, so that the threshold value of the n-channel MISFET deviates from the design value (target value). As a result, variations (fluctuations) in threshold values are caused, and the performance of a semiconductor device having a MISFET is degraded.
- the Hf-based gate is formed from the side of the gate electrode. Oxidizing agents such as oxygen, moisture, or OH groups can easily enter through the interface between the insulating film and the metal gate electrode, leading to oxidation of the metal gate electrode.
- the metal gate electrode is oxidized, the effective work function of the metal gate electrode changes, so that the threshold value of the n-channel MISFET deviates from the design value (target value), and the threshold value varies (fluctuates). And the performance of a semiconductor device having a MISFET is degraded.
- the rare earth element diffuses into the semiconductor substrate, the characteristics of the MISFET deteriorate due to a decrease in channel mobility, leading to a decrease in performance of the semiconductor device having the MISFET. For this reason, in order to further improve the performance of a semiconductor device including a MISFET having a high dielectric constant gate insulating film and a metal gate electrode, it is caused by diffusion of such rare earth elements to the metal gate electrode or the semiconductor substrate side. It is desirable to suppress the malfunctions.
- An object of the present invention is to provide a technique capable of improving performance in a semiconductor device including a MISFET having a high dielectric constant gate insulating film and a metal gate electrode.
- a semiconductor device is a semiconductor device including an n-channel MISFET having a gate insulating film and a metal gate electrode containing hafnium, a rare earth element, and oxygen as main components.
- the concentration distribution of the rare earth element in the thickness direction is lower in the vicinity of the lower surface and the upper surface of the gate insulating film than in the central region of the gate insulating film.
- a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device including an n-channel MISFET having a gate insulating film and a metal gate electrode containing hafnium, a rare earth element, and oxygen as main components. is there.
- the gate insulating film includes a first Hf-containing film containing hafnium and oxygen as main components, a rare earth-containing film containing rare earth elements as main components, and a second Hf-containing film containing hafnium and oxygen as main components. Are formed in order from the bottom, and these are reacted.
- the performance of the semiconductor device can be improved.
- FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3;
- FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4;
- 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5;
- FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6;
- FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3;
- FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4;
- 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5;
- FIG. FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6;
- FIG. 4 is a fragmentary cross-sectional view of the semiconductor
- FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7;
- FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8;
- FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9;
- FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10;
- FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11;
- FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12;
- FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13;
- FIG. 13 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13;
- FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14;
- FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; It is a manufacturing process flowchart which shows a part of other manufacturing process of the semiconductor device which is one embodiment of this invention.
- 7 is a fragmentary cross-sectional view of the semiconductor device during another manufacturing step following that of FIG. 6;
- FIG. FIG. 19 is an essential part cross sectional view of the semiconductor device during another manufacturing step following FIG. 18;
- FIG. 20 is an essential part cross sectional view of the semiconductor device during another manufacturing step following FIG. 19;
- FIG. 21 is an essential part cross sectional view of the semiconductor device during another manufacturing step following FIG. 20;
- FIG. 22 is a fragmentary cross-sectional view of the semiconductor device during another manufacturing step following that of FIG. 21;
- FIG. 2 is an explanatory diagram of an n-channel MISFET of the semiconductor device of FIG. 1. It is a graph which shows the rare earth concentration distribution of the thickness direction before reaction of a Hf containing film
- FIG. 2 is a graph showing a rare earth concentration distribution and a Hf concentration distribution in the thickness direction in the vicinity of the gate insulating film of the p-channel type MISFET of the semiconductor device of FIG. It is explanatory drawing of the semiconductor device which is one embodiment of this invention. It is explanatory drawing of the semiconductor device of a 1st comparative example. It is explanatory drawing of the semiconductor device of the 2nd comparative example. It is a graph which shows the narrow channel characteristic of n channel type MISFET. It is explanatory drawing of a gate width. It is principal part sectional drawing of the semiconductor device which is other embodiment of this invention. It is a manufacturing process flowchart which shows a part of manufacturing process of the semiconductor device which is other embodiment of this invention.
- FIG. 35 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 34;
- FIG. 36 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 35;
- FIG. 37 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 36;
- FIG. 38 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 37;
- FIG. 39 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 38;
- FIG. 40 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 39;
- FIG. 39 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 39;
- FIG. 39 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 39;
- FIG. 39 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 39;
- FIG. 39 is an essential part cross sectional view
- FIG. 41 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 40;
- FIG. 42 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 41;
- FIG. 43 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 42;
- FIG. 44 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 43;
- FIG. 45 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 44;
- FIG. 46 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 45;
- FIG. 47 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 46;
- FIG. 46 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 45;
- FIG. 47 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 46;
- FIG. 46 is an essential part cross sectional view
- FIG. 48 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 47;
- FIG. 33 is an explanatory diagram of a p-channel MISFET of the semiconductor device of FIG. 32. 33 is a graph showing Al concentration distribution and Hf concentration distribution in the thickness direction in the vicinity of the gate insulating film of the p-channel MISFET of the semiconductor device of FIG.
- FIG. 33 is an essential part cross sectional view of the semiconductor device of FIG. 32 during another manufacturing step.
- FIG. 52 is an essential part cross sectional view of the semiconductor device during another manufacturing step following FIG. 51;
- FIG. 53 is an essential part cross sectional view of the semiconductor device during another manufacturing step following FIG. 52;
- FIG. 54 is an essential part cross sectional view of the semiconductor device during another manufacturing step following FIG. 53;
- FIG. 55 is an essential part cross sectional view of the semiconductor device during another manufacturing step following FIG. 54;
- hatching may be omitted even in a cross-sectional view in order to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.
- FIG. 1 is a cross-sectional view of a principal part of a semiconductor device according to an embodiment of the present invention, here, a semiconductor device having an n-channel type MISFET.
- the semiconductor device of the present embodiment has an n-channel MISFET (Metal Insulator Semiconductor Semiconductor Field Effect Transistor) Qn formed on a semiconductor substrate 1.
- MISFET Metal Insulator Semiconductor Semiconductor Field Effect Transistor
- the semiconductor substrate 1 made of p-type single crystal silicon or the like has an active region defined by the element isolation region 2, and a p-type well PW is formed in this active region.
- a gate electrode (metal gate electrode) GE1 of the n-channel type MISFET Qn is interposed via an Hf-containing insulating film (first gate insulating film) 5 functioning as a gate insulating film of the n-channel type MISFET Qn. Is formed.
- the Hf-containing insulating film 5 can be formed directly on the surface (silicon surface) of the semiconductor substrate 1 (p-type well PW) (that is, the interface layer 3 is omitted). It is more preferable to provide an insulating interface layer (insulating layer, insulating film) 3 made of a thin silicon oxide film or silicon oxynitride film at the interface with the substrate 1 (p-type well PW).
- the interface layer 3 made of silicon oxide or silicon oxynitride between the Hf-containing insulating film 5 and the semiconductor substrate 1 (p-type well PW) the interface between the gate insulating film and the semiconductor substrate (the silicon surface thereof) is made SiO 2.
- a 2 / Si (or SiON / Si) structure is used, and the number of defects such as traps can be reduced to improve driving capability and reliability.
- the Hf-containing insulating film 5 is an insulating material film having a higher dielectric constant (relative dielectric constant) than silicon oxide, a so-called High-k film (high dielectric constant film).
- a high-k film, a high dielectric constant film, or a high dielectric constant gate insulating film has a dielectric constant (relative dielectric constant) higher than that of silicon oxide (SiO x , typically SiO 2 ).
- SiO x silicon oxide
- SiO 2 silicon oxide
- the Hf-containing insulating film 5 functioning as the gate insulating film (high dielectric constant gate insulating film) of the n-channel type MISFET Qn is made of an insulating material containing Hf (hafnium) and O (oxygen) as main components, and further a rare earth element
- Hf (hafnium) and O (oxygen) as main components, and further a rare earth element
- One of the features is that it contains (particularly preferably La (lanthanum)).
- the Hf-containing insulating film 5 contains Hf (hafnium), O (oxygen), and a rare earth element as essential constituent elements, but additionally one or both of N (nitrogen) and Si (silicon, silicon). Can also be contained.
- the reason why the Hf-containing insulating film 5 contains rare earth elements is to reduce the threshold value of the n-channel type MISFET Qn. Note that lowering the threshold value of a MISFET corresponds to reducing (lowering) the absolute value of the threshold value (thre
- the rare earth or rare earth element refers to a lanthanoid from lanthanum (La) to lutetium (Lu) plus scandium (Sc) and yttrium (Y).
- a gate insulating film containing Hf may be referred to as an Hf-based gate insulating film.
- the rare earth element contained in the Hf-containing insulating film 5 is expressed as Ln, an HfLnO film, an HfLnON film, an HfLnSiON film, or an HfLnSiO film can be suitably used as the Hf-containing insulating film 5.
- the rare earth element contained in the Hf-containing insulating film 5 for reducing the threshold value of the n-channel MISFET Qn is particularly preferably La (lanthanum)
- the Hf-containing insulating film 5 is particularly preferably an HfLaO film. , HfLaON film, HfLaSiON film, or HfLaSiO film.
- the HfLnO film is an insulating material film composed of hafnium (Hf), rare earth elements (Ln), and oxygen (O)
- the HfLnON film is composed of hafnium (Hf), rare earth elements (Ln), and oxygen (Ln).
- O an insulating material film composed of nitrogen (N).
- the HfLnSiON film is an insulating material film composed of hafnium (Hf), rare earth elements (Ln), silicon (Si), oxygen (O), and nitrogen (N)
- the HfLnSiO film is hafnium (Hf).
- the HfLaO film is an insulating material film composed of hafnium (Hf), lanthanum (La), and oxygen (O).
- the HfLaON film is composed of hafnium (Hf), lanthanum (La), oxygen (O), and oxygen. It is an insulating material film composed of nitrogen (N).
- the HfLaSiON film is an insulating material film made of hafnium (Hf), lanthanum (La), silicon (Si), oxygen (O), and nitrogen (N), and the HfLaSiO film is made of hafnium (Hf). It is an insulating material film composed of lanthanum (La), silicon (Si), and oxygen (O).
- HfLaSiON film when expressed as an HfLaSiON film, the atomic ratio of Hf, La, Si, O, and N in the HfLaSiON film is not limited to 1: 1: 1: 1: 1. This is because HfLnO film, HfLnON film, HfLnSiON film, HfLnSiO film, HfLaO film, HfLaON film, HfLaSiON film, HfLaSiO film, HfO film, HfON film, HfSiON film, HfAlO film, HfAlON film, HfAlON film, HfAlON film, HfAlON film, HfAlON film, HfAlON film, HfAlON film, HfAlON film.
- membranes and the like the same applies to membranes and the like.
- the gate electrode GE1 is a laminated film (laminated film) of a metal film (metal gate film, metal layer) 7 formed on the Hf-containing insulating film 5 and in contact with the Hf-containing insulating film 5 and a silicon film 8 on the metal film 7. Structure).
- the gate electrode GE1 has a metal film 7 in contact with the Hf-containing insulating film 5 which is a gate insulating film (high dielectric constant gate insulating film), and is a so-called metal gate electrode (metal gate electrode).
- the metal film refers to a conductive film (conductive layer) exhibiting metal conduction, and not only a single metal film (pure metal film) or alloy film, but also a metal compound film exhibiting metal conduction. (Such as a metal nitride film or a metal carbide film). For this reason, the metal film 7 is a conductive film showing metal conduction and has a low resistivity to a metal grade.
- the metal film 7 is a titanium nitride (TiN) film, a tantalum nitride (TaN) film, a tungsten nitride (WN) film, a titanium carbide (TiC) film, a tantalum carbide (TaC) film, or a tungsten carbide (WC) film. It is.
- the concentration (content) of the rare earth element is low in the region on the semiconductor substrate 1 side (that is, the region in contact with the interface layer 3) and the region on the gate electrode GE1 side (in other words, the region in contact with the metal film 7).
- the concentration (content ratio) of the rare earth element is high in the central region (central portion) in the thickness direction. This will be described in more detail later.
- an n ⁇ type semiconductor region (extension region, LDD region) EX1 and an n + type having a higher impurity concentration than that A semiconductor region (source / drain region) SD1 is formed.
- the n + type semiconductor region SD1 has a higher impurity concentration and a deep junction depth than the n ⁇ type semiconductor region EX1.
- a side wall (side wall spacer, side wall insulating film) SW made of an insulator is formed on the side wall of the gate electrode GE1.
- the n ⁇ type semiconductor region EX1 is formed in alignment with the gate electrode GE1
- the n + type semiconductor region SD1 is formed in alignment with the sidewall SW provided on the side wall of the gate electrode GE1. That is, the n ⁇ type semiconductor region EX1 is located below the sidewall SW formed on the side wall of the gate electrode GE1, and is interposed between the channel region of the n channel type MISFET Qn and the n + type semiconductor region SD1. ing.
- a metal silicide layer (metal silicide film) 10 is formed on the surfaces of the n + type semiconductor region SD1 and the silicon film 8.
- the metal silicide layer 10 is formed of silicide such as Co (cobalt), Ni (nickel), or Pt (platinum), and can be formed by a salicide process.
- the formation of the metal silicide layer 10 can be omitted, but if the metal silicide layer 10 is formed on the surfaces of the n + type semiconductor region SD1 and the silicon film 8, diffusion resistance and contact resistance can be reduced. it can.
- the metal silicide layer 10 is formed on the surface of the silicon film 8
- the metal silicide layer 10 is formed on the gate electrode GE1 made of a laminated film of the metal film 7 and the silicon film 8 on the metal film 7.
- the metal silicide layer 10 is also included in the gate electrode GE1, a laminated film (laminated structure) of the metal film 7, the silicon film 8 on the metal film 7, and the metal silicide layer 10 on the silicon film 8 is included. It can also be considered that the gate electrode GE1 is configured.
- an insulating film (interlayer insulating film) 11 described later, a contact hole CNT, a plug PG, a stopper insulating film 12, an insulating film 13 and a wiring M1 (see FIG. 15 and FIG. 16 described later), and an upper multilayer wiring structure are provided. Although formed, illustration and description thereof are omitted here.
- FIG. 2 is a manufacturing process flow chart showing a part of a manufacturing process of the semiconductor device of the present embodiment, here, a semiconductor device having an n-channel type MISFET.
- 3 to 16 are fragmentary cross-sectional views of the semiconductor device of the present embodiment, here, a semiconductor device having an n-channel type MISFET during a manufacturing process.
- a semiconductor substrate (semiconductor wafer) 1 made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 ⁇ cm is prepared (prepared) (step S1 in FIG. 2).
- an element isolation region 2 is formed on the main surface of the semiconductor substrate 1 (step S2 in FIG. 2).
- the element isolation region 2 is made of an insulator such as silicon oxide, and is formed by, for example, an STI (Shallow Trench Isolation) method.
- the element isolation region 2 can be formed by an insulating film embedded in a groove (element isolation groove) formed in the semiconductor substrate 1.
- a p-type well PW is formed in a region of the semiconductor substrate 1 where an n-channel MISFET is to be formed (step S3 in FIG. 2).
- the p-type well PW is formed by ion-implanting a p-type impurity such as boron (B).
- ion implantation for adjusting the threshold value of a MISFET formed later is performed on the upper layer portion of the semiconductor substrate 1 as necessary. It can also be done.
- the surface of the semiconductor substrate 1 is cleaned (cleaned) by removing the natural oxide film on the surface of the semiconductor substrate 1 by wet etching using, for example, a hydrofluoric acid (HF) aqueous solution. Thereby, the surface (silicon surface) of the semiconductor substrate 1 (p-type well PW) is exposed.
- HF hydrofluoric acid
- an interface layer (insulating layer, insulating film) 3 made of a silicon oxide film or a silicon oxynitride film is formed on the surface of the semiconductor substrate 1 (that is, the surface of the p-type well PW) (step S4 in FIG. 2). .
- step S4 is omitted and the interface layer 3 is not formed, an Hf-containing film 4a described later can be formed directly on the surface (silicon surface) of the semiconductor substrate 1 (p-type well PW). If the Hf-containing film 4a described later is formed on the interface layer 3 after the interface layer 3 is formed in step S4, the number of defects such as traps can be reduced and the driving ability and reliability can be improved. More preferable.
- the film thickness of the interface layer 3 is thin, preferably 0.3 to 1 nm, for example, about 0.6 nm.
- the interface layer 3 can be formed using, for example, a thermal oxidation method.
- an Hf-containing film (Hf-containing layer, first Hf-containing film) 4a is formed on the main surface of the semiconductor substrate 1, that is, on the interface layer 3 (step S5 in FIG. 2). ).
- the Hf-containing film 4a, the later-described rare earth-containing film 4b, and the later-described Hf-containing film 4c are films for forming the Hf-containing insulating film 5 which is a high dielectric constant gate insulating film.
- the Hf-containing film 4a is made of an insulating material containing hafnium (Hf) and oxygen (O), and is preferably an HfO film (hafnium oxide film, typically an HfO 2 film), an HfON film (hafnium oxynitride film), or HfSiON.
- HfO film hafnium oxide film, typically an HfO 2 film
- HfON film hafnium oxynitride film
- HfSiON hafnium silicate film
- the Hf-containing film 4a can be regarded as an insulating film containing hafnium (Hf) and oxygen (O) as main components.
- the Hf-containing film 4a preferably does not contain a rare earth element.
- the film thickness (formed film thickness) of the Hf-containing film 4a is preferably in the range of 0.3 to 1.5 nm, for example, about 0.8 nm.
- a rare earth-containing film (rare earth-containing layer) 4b is formed on the main surface of the semiconductor substrate 1, that is, on the Hf-containing film 4a (step S6 in FIG. 2).
- the rare earth-containing film 4b contains a rare earth element as a main component, and particularly preferably contains La (lanthanum).
- the rare earth-containing film 4b is preferably a rare earth oxide film (rare earth oxide layer), and particularly preferably a lanthanum oxide film (typically La 2 O 3 as lanthanum oxide).
- the rare earth-containing film 4b does not contain Hf (hafnium).
- the rare earth-containing film 4b can be formed by a sputtering method or an ALD (Atomic Layer Deposition) method, and the film thickness (formed film thickness) is preferably in the range of 0.2 to 1 nm, for example, It can be about 0.4 nm.
- an Hf-containing film (Hf-containing layer, second Hf-containing film) 4c is formed on the main surface of the semiconductor substrate 1, that is, on the rare earth-containing film 4b (step of FIG. 2). S7).
- the Hf-containing film 4c is made of an insulating material containing hafnium (Hf) and oxygen (O), and is preferably an HfO film (hafnium oxide film, typically an HfO 2 film), an HfON film (hafnium oxynitride film), or HfSiON.
- a film (hafnium silicon oxynitride film) or a HfSiO film (hafnium silicate film) can be used.
- the Hf-containing film 4c can be regarded as an insulating film containing hafnium (Hf) and oxygen (O) as main components. It is preferable that the Hf-containing film 4c does not contain a rare earth element.
- the film thickness (formed film thickness) of the Hf-containing film 4c is preferably in the range of 0.5 to 2 nm, for example, about 1.2 nm, but from the film thickness (formed film thickness) of the Hf-containing film 4a. It is also preferable that the thickness is thick.
- the Hf-containing film 4a forming process in step S5 and the Hf-containing film 4c forming process in step S7 can be formed as follows, for example.
- an HfSiO film is first deposited by using an ALD method or a CVD (Chemical Vapor Deposition) method, and then the HfSiO film is nitrided by a nitriding process such as a plasma nitriding process.
- a nitriding process such as a plasma nitriding process.
- heat treatment may be performed in an inert or oxidizing atmosphere.
- an HfO film (typically an HfO 2 film) is first deposited by using an ALD method or a CVD method, and then this HfO film is nitrided by a nitriding process such as a plasma nitriding process (that is, By changing the HfO film to an HfON film, the HfON film can be formed. After this nitriding treatment, heat treatment may be performed in an inert or oxidizing atmosphere.
- a nitriding process such as a plasma nitriding process
- an HfO film (typically an HfO 2 film) may be deposited using an ALD method or a CVD method, and nitriding treatment is not necessary.
- the HfSiO film may be deposited using the ALD method or the CVD method, and nitriding treatment is not necessary.
- a metal film (metal gate electrode) for the metal gate (metal gate electrode) is formed on the main surface of the semiconductor substrate 1, that is, on the Hf-containing film 4c.
- Layer, metal gate film) 7 is formed (step S8 in FIG. 2).
- the metal film 7 is preferably a titanium nitride (TiN) film, a tantalum nitride (TaN) film, a tungsten nitride (WN) film, a titanium carbide (TiC) film, a tantalum carbide (TaC) film, or a tungsten carbide (WC) film. is there.
- the metal film 7 can be formed by, for example, a sputtering method.
- the film thickness (formed film thickness) of the metal film 7 can be set to about 3 to 15 nm, for example.
- a silicon film 8 is formed on the main surface of the semiconductor substrate 1, that is, on the metal film 7 (step S9 in FIG. 2).
- the silicon film 8 can be a polycrystalline silicon film or an amorphous silicon film. Even when the silicon film 8 is an amorphous silicon film at the time of film formation, heat treatment after film formation (for example, activation of step S14 described later) is performed. A polycrystalline silicon film is formed by annealing.
- the film thickness of the silicon film 8 can be about 100 nm, for example.
- the step of forming the silicon film 8 in step S9 can be omitted (that is, the gate electrode GE1 is formed of the metal film 7 without the silicon film 8).
- the silicon film 8 is formed on the metal film 7 in Step S9 (that is, the gate electrode GE1 is formed of a laminated film of the metal film 7 and the silicon film 8 thereon). The reason for this is that if the thickness of the metal film 7 is too thick, the metal film 7 may be easily peeled off or the substrate may be damaged due to over-etching when the metal film 7 is patterned.
- the thickness of the metal film 7 can be reduced compared with the case where the gate electrode is formed only with the metal film 7, thus improving the above problem. Because it can. Further, when the silicon film 8 is formed on the metal film 7, it is possible to follow the processing method and process of the polysilicon gate electrode (gate electrode made of polysilicon) so far, so that the fine workability, the manufacturing cost, and the yield are obtained. But it is an advantage.
- the interface layer 3, the Hf-containing film 4a, the rare earth-containing film 4b, the Hf-containing film 4c, the metal film 7 and the silicon film 8 are sequentially laminated on the semiconductor substrate 1 (p-type well PW). It is in the state.
- a photoresist pattern PR1 is formed on the silicon film 8 by using a photolithography method. Then, by using this photoresist pattern PR1 as an etching mask, the laminated film of the silicon film 8 and the metal film 7 is etched (preferably dry-etched) and patterned to form the metal film 7 as shown in FIG. Then, the gate electrode GE1 made of the silicon film 8 on the metal film 7 is formed (step S10 in FIG. 2). Thereafter, the photoresist pattern PR1 is removed. FIG. 10 shows a state where the photoresist pattern PR1 is removed.
- the gate electrode GE1 is formed on the Hf-containing film 4c. That is, the gate electrode GE1 composed of the metal film 7 and the silicon film 8 on the metal film 7 is formed by stacking the interface layer 3, the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c on the surface of the p-type well PW. It is formed through a film.
- wet etching is performed to remove portions of the Hf-containing film 4c, the rare earth-containing film 4b, and the Hf-containing film 4a that are not covered with the gate electrode GE1. It is more preferable.
- the Hf-containing film 4c, the rare earth-containing film 4b, and the Hf-containing film 4a located below the gate electrode GE1 remain without being removed by the dry etching in step S10 and the subsequent wet etching.
- the Hf-containing film 4c, the rare earth-containing film 4b, and the Hf-containing film 4a that are not covered with the gate electrode GE1 are dry-etched when the silicon film 8 and the metal film 7 are patterned in step S10, or the subsequent wet etching. Is removed.
- an n ⁇ type semiconductor region EX1 is formed in the p type well PW (step S11 in FIG. 2).
- the n ⁇ type semiconductor region EX1 is formed by ion-implanting n-type impurities such as phosphorus (P) or arsenic (As) into the regions on both sides of the gate electrode GE1 of the p-type well PW using the gate electrode GE1 as a mask. be able to.
- ion implantation for forming the halo region can be performed before or after the formation of the n ⁇ type semiconductor region EX1.
- a halo region (p-type halo region) is formed so as to wrap around the n ⁇ type semiconductor region EX1.
- a sidewall (sidewall spacer, sidewall insulating film) SW made of an insulator is formed on the sidewall of the gate electrode GE1 (step S12 in FIG. 2).
- the stacked film of the silicon oxide film and the silicon nitride film is anisotropically etched (etched).
- FIG. 12 shows the silicon oxide film and the silicon nitride film constituting the sidewall SW in an integrated manner.
- an n + type semiconductor region SD1 is formed in the p type well PW by ion implantation (step S13 in FIG. 2).
- the n + -type semiconductor region SD1 is formed in a region on both sides of the gate electrode GE1 and the sidewall SW of the p-type well PW, using phosphorus (P), arsenic (As), or the like using the gate electrode GE1 and the sidewall SW on the sidewall as a mask.
- the n-type impurity can be formed by ion implantation.
- the n + type semiconductor region SD1 has a higher impurity concentration and a deep junction depth than the n ⁇ type semiconductor region EX1.
- the n ⁇ type semiconductor region EX1 is formed in alignment with the gate electrode GE1, and the n + type semiconductor region SD1 is formed in alignment with the sidewall SW.
- the silicon film 8 constituting the gate electrode GE1 is doped with n-type impurities in the ion implantation process for forming the n ⁇ -type semiconductor region EX1 or the ion implantation process for forming the n + -type semiconductor region SD1.
- the step of forming the n + type semiconductor region SD1 in step S13 is an ion implantation for forming the source / drain region of the n channel MISFET Qn. It can be regarded as a process of performing.
- step S14 After performing ion implantation for forming the n + type semiconductor region SD1 in step S13, heat treatment (annealing treatment, activation annealing) for activating the introduced impurities is performed (step S14 in FIG. 2).
- Impurities introduced into the n ⁇ type semiconductor region EX1, the n + type semiconductor region SD1, the silicon film 8 and the like by the ion implantation in steps S11 and S13 can be activated by the heat treatment in step S14.
- the heat treatment in step S14 can be performed, for example, at a heat treatment temperature of 900 ° C. to 1100 ° C. in an inert gas atmosphere, more preferably in a nitrogen atmosphere.
- the heat treatment in step S14 is a high-temperature heat treatment
- the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c react (mix, mix, and interdiffusion). That is, the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c react (mix, mix, interdiffusion) to form the Hf-containing insulating film 5 as shown in FIG.
- the Hf-containing film 4a and the Hf-containing film 4c contain hafnium (Hf) and oxygen (O) as main components, and the rare earth-containing film 4b contains rare earth elements as main components, preferably made of a rare earth oxide. . Therefore, the Hf-containing insulating film 5 formed by the reaction of the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c contains hafnium (Hf), oxygen (O), and a rare earth element as main components. This is an insulating film.
- the rare earth element contained in the Hf-containing insulating film 5 is the same as the rare earth element contained in the rare earth-containing film 4b.
- the Hf-containing insulating film 5 In addition to hafnium (Hf), oxygen (O), and rare earth elements, nitrogen (N) is also contained. If one or both of the Hf-containing film 4a and the Hf-containing film 4c contain not only hafnium (Hf) and oxygen (O) but also Si (silicon, silicon), the Hf-containing insulating film 5 These contain not only hafnium (Hf), oxygen (O) and rare earth elements but also Si (silicon, silicon).
- the rare earth-containing film 4b is preferably a rare earth oxide film (particularly preferably a lanthanum oxide film) as described above.
- the rare earth-containing film 4b contains oxygen (O) in addition to the rare earth element.
- the rare earth-containing films 4a and 4c also contain oxygen (O)
- the rare earth-containing film 4b contains oxygen (O )
- the Hf-containing insulating film 5 contains oxygen (O). That is, the rare earth-containing film 4b preferably further contains oxygen in addition to the rare earth element, but the rare earth-containing film 4b contains either oxygen (O) or oxygen (O).
- the Hf-containing insulating film 5 contains oxygen (O).
- the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c are formed in order from the bottom, and these react to form the Hf-containing insulating film 5, thereby forming the Hf-containing films 4a and 4c.
- the gate electrode GE1 functions as the gate electrode (metal gate electrode) of the n-channel type MISFET Qn, and the Hf-containing insulating film 5 (and the interface layer 3 below the gate electrode GE1) is the gate insulating film of the n-channel type MISFET Qn. Function as. Then, an n-type semiconductor region (impurity diffusion layer) that functions as the source or drain of the n-channel type MISFET Qn is formed by the n + -type semiconductor region SD1 and the n ⁇ -type semiconductor region EX1.
- a metal silicide layer 10 is selectively formed on the surfaces of the n + type semiconductor region SD1 and the silicon film 8 by using a salicide (Salicide: Self Aligned Silicide) technique. Specifically, after the surface of the n + type semiconductor region SD1 is cleaned, Co (cobalt), Ni (nickel) is formed on the main surface of the semiconductor substrate 1 including the n + type semiconductor region SD1 and the silicon film 8. ) Or Pt (platinum) or the like. Then, after the metal film is reacted with the n + type semiconductor region SD1 and the upper layer portion of the silicon film 8 by heat treatment to form the metal silicide layer 10, the unreacted portion of the metal film is removed by wet etching or the like. Good.
- the metal silicide layer 10 is more preferably formed because it has an effect of reducing diffusion resistance and contact resistance. However, if it is unnecessary, the formation thereof can be omitted.
- an insulating film (interlayer insulating film) 11 is formed on the main surface of the semiconductor substrate 1 so as to cover the gate electrode GE1 and the sidewall SW.
- the insulating film 11 is made of, for example, a single film of a silicon oxide film or a laminated film of a thin silicon nitride film and a thick silicon oxide film thereon.
- the surface of the insulating film 11 is planarized using, for example, a CMP (Chemical-Mechanical-Polishing) method.
- the insulating film 11 is dry etched to form contact holes (through holes, holes) CNT in the insulating film 11. To do.
- the contact hole CNT is formed in the n + type semiconductor region SD1 and the upper part of the gate electrode GE1.
- a conductive plug (connecting conductor portion) PG made of tungsten (W) or the like is formed in the contact hole CNT.
- a barrier conductor film for example, a titanium film, a titanium nitride film, or a laminated film thereof
- a main conductor film made of a tungsten film or the like is formed on the barrier conductor film so as to fill the contact holes CNT, and unnecessary main conductor films and barrier conductor films on the insulating film 11 are formed by CMP or etchback.
- FIG. 15 shows the barrier conductor film and the main conductor film (tungsten film) constituting the plug PG in an integrated manner.
- a stopper insulating film (etching stopper insulating film) 12 and a wiring forming insulating film (interlayer insulating film) 13 are sequentially formed on the insulating film 11 in which the plug PG is embedded.
- the stopper insulating film 12 is a film that serves as an etching stopper when a groove is formed in the insulating film 13, and uses a material having etching selectivity with respect to the insulating film 13.
- the stopper insulating film 12 is a silicon nitride film.
- the insulating film 13 can be a silicon oxide film.
- the first layer wiring M1 is formed by a single damascene method.
- the wiring groove 14 is formed on the main surface of the semiconductor substrate 1 (that is, the wiring groove 14).
- a barrier conductor film (for example, a titanium nitride film, a tantalum film, a tantalum nitride film, or the like) is formed on the insulating film 13 including the bottom and side walls.
- a copper seed layer is formed on the barrier conductor film by a CVD method or a sputtering method, and a copper plating film is further formed on the seed layer by an electrolytic plating method or the like. Embed the inside. Then, the copper plating film, the seed layer, and the barrier metal film in a region other than the inside of the wiring trench 14 are removed by CMP to form a first layer wiring M1 using copper as a main conductive material.
- FIG. 16 shows the copper plating film, the seed layer, and the barrier conductor film constituting the wiring M1 in an integrated manner.
- the wiring M1 is electrically connected to the n + type semiconductor region SD1 for the source or drain of the n channel MISFET Qn through the plug PG. Thereafter, the second and subsequent wirings are formed by a dual damascene method or the like, but illustration and description thereof are omitted here. Further, the wiring M1 and the wiring higher than that are not limited to damascene wiring, and can be formed by patterning a conductor film for wiring, for example, tungsten wiring or aluminum wiring.
- the semiconductor device of this embodiment can be manufactured.
- an Hf-containing film 4a, a rare earth-containing film 4b, and an Hf-containing film 4c are used as films for forming the Hf-containing insulating film 5, and these Hf-containing film 4a, rare earth-containing film 4b, and Hf-containing film 4c are used.
- the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c react to form the Hf-containing insulating film 5 as a high dielectric constant gate insulating film of the n-channel MISFET Qn.
- step S14 If no high-temperature heat treatment other than the activation annealing (heat treatment) in step S14 is performed during the manufacturing process, the reaction between the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c is the activation annealing in step S14.
- the heat treatment is performed before the activation annealing (heat treatment) in step S14, three or two of the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c are formed.
- the Hf-containing insulating film reacts to some extent in the heat treatment before step S14 (activation annealing step), and further proceeds (diffusion of atoms) in the activation annealing step in step S14, and is close to the Hf-containing insulating film 5 in the final form. 5 is formed.
- FIG. 17 is a manufacturing process flowchart showing a part of another manufacturing process of the semiconductor device according to the present embodiment, and corresponds to FIG. 18 to 22 are fragmentary cross-sectional views of the semiconductor device of the present embodiment during another manufacturing process.
- the semiconductor substrate 1 is subjected to heat treatment before the step of forming the Hf-containing film 4c in step S7. Then, the rare earth-containing film 4b and the Hf-containing film 4a are reacted (mixed, mixed, and interdiffused) (step S21 in FIG. 17).
- the heat treatment in step S21 can be performed in an inert gas atmosphere (even in a nitrogen gas atmosphere) at a heat treatment temperature in the range of 600 to 1000 ° C., for example.
- the Hf-containing film 4a and the rare earth-containing film 4b react (mixing, mixing, interdiffusion), and as shown in FIG. 18, the reaction between the Hf-containing film 4a and the rare earth-containing film 4b.
- the Hf-containing film 4a contains hafnium (Hf) and oxygen (O) as main components
- the rare earth-containing film 4b contains rare earth elements as main components
- the Hf-containing film 4a and the rare earth-containing film 4b The Hf-containing film 4d formed by reacting with each other is an insulating film containing hafnium (Hf), oxygen (O), and a rare earth element as main components.
- the rare earth element contained in the Hf-containing film 4d is the same as the rare earth element contained in the rare earth-containing film 4b.
- the Hf-containing film 4d When the Hf-containing film 4a contains not only hafnium (Hf) and oxygen (O) but also nitrogen (N), the Hf-containing film 4d has hafnium (Hf) and oxygen (O). Not only rare earth elements but also nitrogen (N) is contained.
- the Hf-containing film 4a contains not only hafnium (Hf) and oxygen (O) but also Si (silicon, silicon)
- the Hf-containing film 4d has hafnium (Hf) and oxygen (O ) And rare earth elements as well as Si (silicon, silicon).
- the rare earth-containing film 4b is preferably a rare earth oxide film (particularly preferably a lanthanum oxide film) as described above.
- the rare earth-containing film 4b contains oxygen (O) in addition to the rare earth element.
- the Hf-containing film 4a also contains oxygen (O)
- the rare earth-containing film 4b contains oxygen (O).
- the Hf-containing film 4d contains oxygen (O). That is, the rare earth-containing film 4b preferably further contains oxygen in addition to the rare earth element, but the rare earth-containing film 4b contains either oxygen (O) or oxygen (O).
- the Hf-containing film 4d contains oxygen (O).
- the Hf-containing film 4a and the rare earth-containing film 4b are formed in order from the bottom and react to form an Hf-containing film 4d.
- the Hf-containing film 4a contains Hf (hafnium) but contains rare earth elements.
- the rare earth-containing film 4b contains a rare earth element but does not contain Hf (hafnium).
- the formed Hf-containing film 4d is not uniform in composition in the film thickness direction, and maintains the composition distribution before the reaction between the Hf-containing film 4a and the rare earth-containing film 4b to some extent. This will be described in more detail later.
- the subsequent steps are basically the same as the Hf-containing film 4c forming step in step S7 and the subsequent steps (steps shown in FIGS. 7 to 16).
- the Hf-containing film 4c is formed in step 7, but when the heat treatment step in step S21 is not performed, the Hf-containing film is formed on the rare earth-containing film 4b as shown in FIG. In contrast to the film 4c formed, when the heat treatment step of step S21 is performed, the Hf-containing film 4c is formed on the rare earth-containing film 4d as shown in FIG. Then, as shown in FIG. 19, the metal film 7 is formed on the Hf-containing film 4c in step S8, and the silicon film 8 is formed on the metal film 7 in step S9. This is the presence or absence of the heat treatment in step S21. It is the same regardless.
- step S10 after forming a photoresist pattern PR1 on the silicon film 8, the laminated film of the silicon film 8 and the metal film 7 is patterned in step S10 using the photoresist pattern PR1 as an etching mask.
- the gate electrode GE1 made of the metal film 7 and the silicon film 8 on the metal film 7 is formed, and then the photoresist pattern PR1 is removed.
- the n ⁇ type semiconductor region EX1 is formed in step S11
- the sidewall SW is formed in step S12
- the n + type semiconductor region SD1 is formed in step S13, whereby the structure of FIG. 21 is obtained.
- step S14 by performing the heat treatment in step S14, the impurities introduced into the n ⁇ type semiconductor region EX1, the n + type semiconductor region SD1, the silicon film 8 and the like by the ion implantation in steps S11 and S13 are activated.
- the Hf-containing film 4d and the Hf-containing film 4c react (mixing, mixing, mutual diffusion). That is, the Hf-containing film 4d and the Hf-containing film 4c react (mix, mix, and interdiffusion) to form the Hf-containing insulating film 5 as shown in FIG.
- FIG. 22 corresponds to FIG. Since the subsequent steps are the same as those described with reference to FIGS. 14 to 16, the description thereof is omitted here.
- step S21 When the heat treatment process of step S21 is not performed, the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c react to form the Hf-containing insulating film 5 as shown in FIG. .
- the Hf-containing film 4a and the rare earth-containing film 4b react with each other in the heat treatment in step S21 to form the Hf-containing film 4d, which is a reaction layer of both.
- the Hf-containing film 4d and the Hf-containing film 4c react to form the Hf-containing insulating film 5 as shown in FIG.
- Hf-containing film 4a rare-earth-containing film 4b, and Hf-containing film 4c
- HfO film, HfON film, HfSiO film, HfSiON film types of Hf-containing insulating film 5 to be formed
- HfLnO film, HfLnON film The correlation with the film, the HfLnSiO film, or the HfLnSiON film) is the same regardless of the presence or absence of the heat treatment in step S21 and has already been described above.
- the formed Hf-containing film 4d Since the Hf-containing film 4d is formed by the reaction between the Hf-containing film 4a and the rare earth-containing film 4b formed thereon, the formed Hf-containing film 4d has a nonuniform composition in the film thickness direction. The composition distribution before the reaction between the Hf-containing film 4a and the rare earth-containing film 4b is maintained to some extent. Since the Hf-containing film 4d and the Hf-containing film 4d formed thereon react to form the Hf-containing insulating film 5, the formed Hf-containing insulating film 5 has a composition in the film thickness direction. Is not uniform, and the composition distribution before the reaction of the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c is maintained to some extent. This will be described in more detail later.
- the gate electrode GE1 of the n-channel type MISFET Qn has the metal film 7 located on the gate insulating film (here, the interface layer 3 and the Hf-containing insulating film 5). Metal gate electrode). For this reason, since the depletion phenomenon of the gate electrode can be suppressed and the parasitic capacitance can be eliminated, the MISFET element can be downsized (the gate insulating film can be made thinner).
- the Hf-containing insulating film 5 having a dielectric constant higher than that of silicon oxide is used as the gate insulating film of the n-channel type MISFET Qn. That is, a material film having a dielectric constant (relative dielectric constant) higher than that of silicon oxide, that is, a Hf-containing insulating film 5 which is a so-called High-k film (high dielectric constant film) is used as a gate insulating film of the n-channel type MISFET Qn.
- the physical film thickness of the Hf-containing insulating film 5 can be increased compared to the case where a silicon oxide film is used as the gate insulating film of the n-channel type MISFET Qn, the leakage current can be reduced.
- the n-channel MISFET Qn is The threshold can be lowered.
- Hf-containing insulating film 5 contains Hf-containing film 4a containing hafnium and oxygen as main components, rare earth-containing film 4b containing rare earth elements as main components, and hafnium and oxygen as main components.
- the Hf-containing film 4c to be formed is formed in order from the bottom, and these are formed by reaction. Therefore, inevitably, the concentration distribution of the rare earth element and Hf in the thickness direction of the Hf-containing insulating film 5 is as shown in FIG. This will be described below.
- FIG. 23 is an explanatory diagram of the semiconductor device according to the present embodiment, and shows a partial enlarged cross-sectional view of a region in the vicinity of the gate insulating film.
- FIG. 23 corresponds to the case where the heat treatment of step S21 is not performed (in the case of the process flow of FIG. 2).
- the Hf-containing insulating film 5 is formed by the reaction (mixing, mixing, interdiffusion) of the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c.
- FIG. The state before the film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c react is shown. In FIG.
- the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c react.
- the state (the state after FIG. 13 described above) that has become the Hf-containing insulating film 5 is shown.
- the manufactured semiconductor device corresponds to the state shown in FIG.
- FIG. 24 is a graph showing the rare earth concentration distribution in the thickness direction in the state of FIG. 23A
- FIG. 25 is a graph showing the Hf concentration distribution in the thickness direction in the state of FIG.
- FIG. 26 is a graph showing the rare earth concentration distribution and the Hf concentration distribution in the thickness direction in the state of FIG. That is, the concentration distribution of the rare earth element at the position along the line 16 in FIG. 23A corresponds to FIG. 24, and the concentration distribution of Hf at the position along the line 16 in FIG. 26, the rare earth element concentration distribution and the Hf concentration distribution at the position along the line 16 in FIG. 23B correspond to FIG.
- the position of the line 16 in FIG. 23A is the same as the position of the line 16 in FIG.
- the horizontal axis of the graphs of FIGS. 24 and 25 corresponds to the position along the line 16 in FIG. 23A, and the horizontal axis of the graph of FIG. 26 is the line 16 in FIG.
- the vertical axis of the graph in FIG. 24 corresponds to the rare earth concentration (rare earth element concentration)
- the vertical axis of the graph in FIG. 25 corresponds to the Hf concentration
- the vertical axis of the graph in FIG. The axis corresponds to the rare earth concentration and the Hf concentration.
- the concentration distribution of rare earth elements is indicated by a solid line
- the concentration distribution of Hf is indicated by a dotted line. Note that the rare earth concentration and the Hf concentration on the vertical axis of the graphs of FIGS.
- the thickness direction or the film thickness direction corresponds to a direction perpendicular to the main surface of the semiconductor substrate 1.
- the direction of the line 16 in FIGS. 23A and 23B is the thickness direction (that is, the direction perpendicular to the main surface of the semiconductor substrate 1).
- the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c are formed in this order from the bottom, and react with each other, whereby the high dielectric constant gate insulating film An Hf-containing insulating film 5 is formed.
- the rare earth-containing film 4b contains rare earth elements, but the Hf-containing films 4a and 4c do not contain rare earth elements, and as can also be seen from FIG. 25, the Hf-containing film 4a. , 4c contain Hf (hafnium), but the rare earth-containing film 4b does not contain Hf (hafnium).
- the rare earth concentration in the thickness direction of the rare earth-containing film 4b is substantially constant
- the Hf concentration in the thickness direction of the Hf-containing film 4a is substantially constant
- the Hf concentration in the thickness direction of the Hf-containing film 4c is substantially constant.
- the concentration distribution in the thickness direction of each element in the Hf-containing insulating film 5 is Although it should be uniform, in practice, it is difficult to completely mix the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c. For this reason, the concentration distribution in the thickness direction of each element in the actually formed Hf-containing insulating film 5 is not uniform, and the composition distribution before the reaction of the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c is determined. A non-uniform distribution maintained to some extent.
- the rare earth concentration distribution in the thickness direction of the Hf-containing insulating film 5 (rare earth element concentration distribution) will be described.
- the rare earth concentration distribution in the thickness direction of the Hf-containing insulating film 5 is not uniform (constant), but peaks (maximum) in the central region in the thickness direction of the Hf-containing insulating film 5. the one having a value) P 1.
- the concentration distribution of the rare earth element in the thickness direction of the Hf-containing insulating film (first gate insulating film) 5 is more rare earth elements in the vicinity of the lower surface and the upper surface of the Hf-containing insulating film 5 than in the central region of the Hf-containing insulating film 5.
- the concentration of is low.
- this peak P 1 is a region that was the rare-earth-containing film 4 b before becoming the Hf-containing insulating film 5 (that is, the original rare-earth-containing film). 4b). The reason is as follows.
- the rare-earth-containing film 4b is moved to the Hf-containing film 4a side and the Hf-containing film 4c side.
- Rare earth elements diffuse.
- the heat treatment of about the activation annealing heat treatment in step S14
- the rare earth elements are not uniformly distributed in the thickness direction of the Hf-containing insulating film 5, but after the activation annealing (heat treatment in step S14).
- the heat treatment at a temperature equal to or higher than the temperature of activation annealing (heat treatment in step S14) is not performed on the semiconductor substrate 1.
- the region that originally was the rare earth-containing film 4b (the intermediate layer portion in the thickness direction of the Hf-containing insulating film 5), the region that was originally the Hf-containing films 4a and 4c.
- the rare earth concentration is low.
- the Hf-containing insulating film 5 based on the above peak P 1 in the (middle layer portion of the Hf-containing insulating film 5) A region a rare earth-containing film 4b is formed, more specifically, based on the content rare earth It said peak P 1 is formed near the center in the thickness direction of the film 4b and an area (an intermediate layer portion of the Hf-containing insulating film 5). Then, the semiconductor substrate 1 side and the gate electrode GE1 (metal film 7) than the peak P 1, a state in which the rare earth concentration was decreased gradually.
- the rare earth concentration distribution in the thickness direction of the Hf-containing insulating film 5 becomes one mountain-shaped distribution, has the peak P 1 in the central region in the thickness direction of the Hf-containing insulating film 5 and has the highest rare earth concentration, and the peak P 1 located towards the (central region in the thickness direction) in the semiconductor substrate 1 side decreases monotonically rare earth concentration, rare earth concentration decreases monotonically toward the metal film 7 side from the position of the peak P 1 (central region in the thickness direction) .
- the concentration distribution of the rare earth element in the thickness direction of the Hf-containing insulating film 5 has a peak P 1 in the central region in the thickness direction of the Hf-containing insulating film 5, the lower surface of the Hf-containing insulating film 5 (i.e. Hf-containing insulating The central region in the thickness direction of the Hf-containing insulating film 5 at and near the interface between the film 5 and the interface layer 3 and the upper surface of the Hf-containing insulating film 5 (that is, the interface between the Hf-containing insulating film 5 and the metal film 7) and its vicinity.
- the concentration of the rare earth element is lower than (the above peak P 1 ).
- the Hf concentration distribution in the thickness direction of the Hf-containing insulating film 5 will be described.
- the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c the Hf-containing film 4a and the rare earth-containing film 4b contain Hf, but the rare earth-containing film that is an intermediate layer.
- the film 4b does not contain Hf.
- the Hf concentration distribution in the thickness direction of the Hf-containing insulating film 5 is not uniform (constant), but a double peak (peak P 2) in the thickness direction of the Hf-containing insulating film 5. And peak P 3 ).
- the concentration distribution has a double peak means that the concentration distribution has two peaks with maximum values (here, peak P 2 and peak P 3 ), and peaks other than these two peaks (maximum). Corresponds to not having (value).
- peak P 2 and peak P 3 maximum values
- peak P 3 peak P 3 of the double peak in the Hf-containing insulating film 5
- the other peak P 3 of the double peak in the Hf-containing insulating film 5 is a region (Hf-containing insulating film 5 ). The reason is as follows.
- the region that was originally the rare-earth-containing film 4 b (the lower layer portion and the upper layer portion of the Hf-containing insulating film 5)
- the Hf concentration is low. Accordingly, in the Hf-containing insulating film 5, based on the above peak P 2 is formed in the region was Hf-containing film 4a (lower layer portion of the Hf-containing insulating film 5), and the original was Hf-containing film 4c region the peak P 3 are formed in the (upper layer portion of the Hf-containing insulating film 5).
- Hf concentration decreases gradually or rapidly. Further, the Hf concentration takes the minimum value MIN at a position between the peak P 2 and the peak P 3 (position in the thickness direction), and from the peak P 2 to the minimum value MIN, the peak P 3 starts from the minimum value MIN. Over time, the Hf concentration gradually decreases. That is, the Hf concentration distribution in the thickness direction of the Hf-containing insulating film 5 has two peak-like distributions and has a double peak (P 2 , P 3 ) in the thickness direction of the Hf-containing insulating film 5, and the peak P 2.
- Hf concentration toward the position Hf concentration is monotonously decreased toward the semiconductor substrate 1 side
- Hf concentration is monotonously decreased toward the minimum value MIN from the position of the peak P 2
- the minimum value MIN from the position of the peak P 3 Monotonously decreases
- the Hf concentration monotonously decreases from the position of peak P 3 toward the metal film 7 side.
- the peak P 1 is located between the position of the peak P 2 and the position of the peak P 3 in the thickness direction of the Hf-containing insulating film 5.
- the concentration distribution of the rare earth element in the thickness direction of the Hf-containing insulating film 5 is a position between the double peaks of the Hf (hafnium) concentration distribution in the thickness direction of the Hf-containing insulating film 5 (that is, the position and peak of the peak P 2 ). It has a peak P 1 between the positions of P 3 . Then, in the thickness direction of the Hf-containing insulating film 5, at the location or near the earth concentration distribution has the peak P 1, Hf concentration distribution will have the minimum value MIN.
- FIG. 27 is an explanatory diagram of the semiconductor device according to the present embodiment. Like FIG. 23, FIG. 27 shows a partially enlarged cross-sectional view of the region in the vicinity of the gate insulating film. FIG. 27 corresponds to the case where the heat treatment of step S21 is performed (in the case of the process flow in FIG. 17).
- FIG. 27A shows a state before the Hf-containing film 4a and the rare earth-containing film 4b react (the state shown in FIG. 6).
- FIG. 27B shows the Hf-containing film 4a and the rare-earth-containing film 4b. The state in which the rare earth-containing film 4b reacts to form the Hf-containing film 4d (the state shown in FIG. 18) is shown.
- FIG. 18 shows a state before the Hf-containing film 4a and the rare earth-containing film 4b react.
- FIG. 27D the Hf-containing film 4d and the Hf-containing film 4c react.
- a state where the Hf-containing insulating film 5 is obtained (the state after FIG. 22) is shown.
- the manufactured semiconductor device corresponds to the state of FIG. 27D, and FIG. 23B and FIG. 27D are the same.
- the Hf-containing film 4a and the rare earth-containing film 4b are formed in order from the bottom, and these react to form the Hf-containing film 4d.
- the Hf-containing insulating film 5 which is a high dielectric constant gate insulating film is formed by the reaction between the containing film 4d and the Hf-containing film 4c formed thereon.
- the rare earth-containing film 4b contains rare earth elements, but the Hf-containing films 4a and 4c do not contain rare earth elements, and the Hf-containing films 4a and 4c contain Hf (hafnium).
- the rare earth-containing film 4b does not contain Hf (hafnium).
- the concentration distribution in the thickness direction of each element in the Hf-containing insulating film 5 should be uniform. In reality, however, it is difficult to completely mix the Hf-containing film 4d and the Hf-containing film 4c. It is also difficult to completely mix the Hf-containing film 4a and the rare earth-containing film 4b by the heat treatment in step S21.
- the concentration distribution in the thickness direction of each element in the actually formed Hf-containing insulating film 5 is not uniform, and the composition distribution before the reaction of the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c is maintained to some extent. Resulting in a non-uniform distribution.
- the Hf-containing film 4a and the rare earth-containing film 4b are reacted once, and then the reaction layer (Hf-containing film 4d) and the Hf-containing film 4c are reacted to form the Hf-containing insulating film 5.
- the rare earth concentration distribution and the Hf concentration distribution in the thickness direction of the Hf-containing insulating film 5 react with the Hf-containing film 4a, the rare-earth-containing film 4b, and the Hf-containing film 4c as in the process of FIG.
- the concentration distribution is the same as when the Hf-containing insulating film 5 is formed.
- the rare earth element concentration distribution and the Hf concentration distribution in the thickness direction in the formed Hf-containing insulating film 5 are as shown in FIG. 26 regardless of the presence or absence of the heat treatment step of step S21. . Since the specific description of the concentration distribution shown in FIG. 26 has already been described above, the description thereof is omitted here.
- FIG. 28 is an explanatory diagram of the semiconductor device of the first comparative example, showing a partially enlarged cross-sectional view of the region in the vicinity of the gate insulating film, and corresponds to FIG. 23 of the present embodiment.
- an interface layer (silicon oxide film) 103, a hafnium oxide film 104a, and a rare earth oxide film 104b are formed on a semiconductor substrate 101.
- a metal film 107 is formed in order from the bottom and forms a metal gate electrode on the rare earth oxide film 104b.
- the high-temperature heat treatment such as activation annealing causes the hafnium oxide film 104a and the rare earth oxide film 104b to react, and as shown in FIG. 28 (b), hafnium (Hf), oxygen (O), and rare earth.
- a high dielectric constant gate insulating film 105a containing an element as a main component is formed.
- FIG. 29 is an explanatory diagram of the semiconductor device of the second comparative example, showing a partially enlarged cross-sectional view of the vicinity of the gate insulating film, and corresponds to FIG. 23 of the present embodiment.
- the interface layer (silicon oxide film) 103, the rare earth oxide film 104b, and the hafnium oxide film 104c are formed on the semiconductor substrate 101.
- a metal film 107 is formed in order from the bottom, and forms a metal gate electrode on the hafnium oxide film 104c.
- the rare earth oxide film 104b reacts with the hafnium oxide film 104c by a high-temperature heat treatment such as activation annealing, and as shown in FIG. 29B, hafnium (Hf), oxygen (O), and rare earth A high dielectric constant gate insulating film 105b containing an element as a main component is formed.
- the first comparative example of FIG. 28 corresponds to the case where the Hf-containing film 4c is not formed in the present embodiment
- the second comparative example of FIG. 29 is the Hf-containing film 4a in the present embodiment. This corresponds to the case where no is formed.
- an Hf-based gate insulating film containing hafnium (Hf) and oxygen (O) as main components has high heat resistance, high dielectric constant, and high stability. Very good in terms.
- a rare earth element particularly preferably lanthanum
- the threshold value of the n-channel MISFET can be lowered.
- the rare earth element when the rare earth element is introduced into the Hf-based gate insulating film, the rare earth element is likely to diffuse to the metal gate electrode or the semiconductor substrate side, and thus it may cause various problems. I understood.
- the following problems occur in the semiconductor device of the first comparative example in FIG. That is, in the semiconductor device of the first comparative example of FIG. 28, two layers of the hafnium oxide film 104a and the rare earth oxide film 104b formed thereon are used to form the high dielectric constant gate insulating film 105a. These two layers are reacted.
- the metal film 107 for the metal gate is located immediately above the rare earth oxide film 104 b, the rare earth element is easily diffused into the metal film 107. If the rare earth element diffuses into the metal film 107, the effective work function of the metal gate electrode (metal film 107) changes, so that the threshold value of the n-channel MISFET is the design value (target value). This causes deviation in threshold value (variation), leading to a decrease in performance of a semiconductor device having a MISFET.
- the rare earth concentration distribution in the thickness direction in the high dielectric constant gate insulating film 105a is not uniform, and is a non-uniform distribution in which the composition distribution before the reaction between the hafnium oxide film 104a and the rare earth oxide film 104b is maintained to some extent. In the vicinity of the interface between the high dielectric constant gate insulating film 105a and the metal film 107, the rare earth concentration is considerably high.
- the metal gate electrode Oxidizing agent such as oxygen, moisture or OH group easily enters from the side surface through the interface between the high dielectric constant gate insulating film 105a and the metal gate electrode (metal film 107), and the metal gate electrode (metal film 107) is oxidized. Will be invited.
- the metal gate electrode (metal film 107) is oxidized, the effective work function of the metal gate electrode (metal film 107) changes, so that the threshold value of the n-channel MISFET deviates from the design value (target value). As a result, variation (fluctuation) of the threshold value is caused and the performance of the semiconductor device having the MISFET is lowered.
- the following problems occur in the semiconductor device of the second comparative example in FIG. That is, in the semiconductor device of the second comparative example in FIG. 29, two layers of the rare earth oxide film 104b and the hafnium oxide film 104c formed thereon are used to form the high dielectric constant gate insulating film 105b. These two layers are reacted.
- the rare earth oxide film 104 b is formed immediately above the interface layer 103, the rare earth element easily diffuses into the semiconductor substrate 101.
- the characteristics of the MISFET deteriorate due to a decrease in channel mobility, leading to a decrease in performance of the semiconductor device having the MISFET.
- the interface layer 103 is provided for controlling the interface between the high dielectric constant gate insulating film 105 b and the semiconductor substrate 101, it is not preferable to form the rare earth oxide film 104 b directly on the interface layer 103.
- the second comparative example there is a possibility that a defect due to diffusion of rare earth elements occurs. For this reason, in order to further improve the performance of a semiconductor device including a MISFET having a high dielectric constant gate insulating film and a metal gate electrode, it is caused by diffusion of such rare earth elements to the metal gate electrode or the semiconductor substrate side. It is desirable to suppress the malfunctions.
- the Hf-containing insulating film 5 that is a high dielectric constant gate insulating film containing hafnium (Hf), oxygen (O), and a rare earth element as main components is formed.
- Hf hafnium
- O oxygen
- a rare earth element as main components.
- three layers of the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c formed in this order from the bottom are used, and these react to form the Hf-containing insulating film 5.
- the rare earth-containing film 4b is not formed immediately above the interface layer 3, but is formed on the Hf-containing film 4a. Diffusion into the semiconductor substrate 1 (p-type well PW) can be suppressed or prevented. Therefore, it is possible to suppress or prevent a decrease in channel mobility due to diffusion of rare earth elements in the semiconductor substrate 1 (p-type well PW), and to improve the characteristics (performance) of the n-channel type MISFET Qn. . For this reason, the performance of a semiconductor device having an n-channel MISFET can be improved. As described above, in this embodiment, the problem caused in the second comparative example of FIG. 29 can be solved and the performance of the semiconductor device can be improved.
- the metal film 7 for the metal gate electrode is not formed immediately above the rare earth-containing film 4b, but the metal film 7 is formed on the Hf-containing film 4c. Diffusion into the metal film 7 for the metal gate electrode can be suppressed or prevented. If the rare earth element diffuses into the metal film 7, the effective work function of the metal gate electrode (metal film 7) changes and the threshold value deviates from the design value (target value). In this embodiment, since the diffusion of rare earth elements into the metal film 7 can be suppressed or prevented, the threshold value of the n-channel type MISFET Qn can be set to a design value (target value). In addition, variation (variation) in threshold value can be reduced. Therefore, the characteristics (performance) of the n-channel type MISFE can be improved, and the performance of the semiconductor device having the n-channel type MISFET can be improved.
- the rare earth concentration distribution in the thickness direction in the Hf-containing insulating film 5 is not uniform, and is a non-uniform distribution in which the composition distribution before the reaction of the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c is maintained to some extent. ing. Therefore, compared to the first comparative example of FIG. 28, the present embodiment reflects the fact that the metal film 7 is formed on the Hf-containing film 4c that does not contain a rare earth element. The rare earth concentration in the vicinity of the interface between the film (Hf-containing insulating film 5) and the metal film 7 can be considerably reduced.
- the Hf-containing insulating film 5 high dielectric constant gate insulating film
- the metal film 7 metal gate electrode
- the characteristics (performance) of the n-channel MISFET can be improved, and the performance of the semiconductor device having the n-channel MISFET can be improved.
- the problem caused in the first comparative example in FIG. 28 can be solved and the performance of the semiconductor device can be improved.
- the film thickness of the Hf-containing film 4c is preferably larger than the film thickness of the Hf-containing film 4a (formed film thickness in step S5).
- the rare-earth element is a metal while suppressing the increase in the film thickness of the Hf-containing insulating film 5. Diffusion into the film 7 can be accurately prevented, and the performance of the semiconductor device having the n-channel MISFET can be improved efficiently.
- FIG. 30 is a graph showing the narrow channel characteristics of an n channel MISFET.
- FIG. 31 is an explanatory diagram of the gate width.
- the horizontal axis of the graph of FIG. 30 corresponds to the gate width of the n-channel type MISFET, and the vertical axis of the graph of FIG. 30 corresponds to the amount of change in threshold value.
- the amount of change in the threshold value on the vertical axis of the graph of FIG. 30 is the threshold value when the gate width is sufficiently large (the gate width is approximately 1 ⁇ m or more), and the gate width is changed when It corresponds to how much the threshold value deviates from the reference value.
- FIG. 30 is a graph showing the narrow channel characteristics of an n channel MISFET.
- FIG. 31 is an explanatory diagram of the gate width.
- the horizontal axis of the graph of FIG. 30 corresponds to the gate width of the n-channel type MISFET
- the vertical axis of the graph of FIG. 30 corresponds to the amount of change in
- FIG. 31 shows a gate electrode GE (corresponding to the gate electrode GE1 of the present embodiment) and a source / drain region SD (a combination of the n ⁇ type semiconductor region EX1 and the n + type semiconductor region SD1 of the present embodiment).
- the cross-sectional view of FIG. 1 is substantially equivalent to the cross-sectional view taken along the line A1-A1 of FIG.
- the gate width is indicated by a symbol W1 in FIG. 31, and the gate length is indicated by a symbol W2 in FIG.
- a gate width of 100 nm or less may be used.
- the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c are formed in this order from the bottom as in the present embodiment, and these react to form the Hf-containing insulating film 5. Is indicated by a solid line and is indicated as “this embodiment”.
- two layers of a hafnium oxide film 104a and a rare earth oxide film 104b are formed in order from the bottom as in the first comparative example of FIG. 28, and these react to react with each other to form a high dielectric constant gate insulating film 105a. Is formed as a “first comparative example (FIG. 28)”.
- the threshold voltage is lowered by introducing a rare earth element into the high dielectric constant gate insulating film 105a. Can do.
- the threshold voltage rises due to the effect of the oxidation of the metal film 107 for the reasons described above, and the high dielectric constant is increased. The effect of lowering the threshold due to the introduction of rare earth elements into the rate gate insulating film 105a is apparently lost.
- the threshold voltage can be lowered. For this reason, the effect of lowering the threshold by introducing the rare earth element into the high dielectric constant gate insulating film (Hf-containing insulating film 5) can be enjoyed regardless of the gate width W1. Therefore, the performance of a semiconductor device having an n-channel MISFET can be improved.
- Embodiment 2 In the first embodiment, the case where the present invention is applied to a semiconductor device having an n-channel MISFET has been described. In this embodiment, a case where the present invention is applied to a semiconductor device having a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor) will be described.
- CMISFET Complementary Metal Insulator Semiconductor Field Effect Transistor
- FIG. 32 is a fragmentary cross-sectional view of the semiconductor device of the present embodiment, here, a semiconductor device having a CMISFET.
- the semiconductor device of the present embodiment includes an n-channel type MISFET Qn formed in an nMIS formation region (first region) 1A of a semiconductor substrate 1 and a pMIS formation region (second region) of a semiconductor substrate 1. And p channel type MISFET Qp formed in 1B.
- the configuration of the n-channel type MISFET Qn in the present embodiment is basically the same as that of the n-channel type MISFET Qn in the first embodiment.
- the semiconductor substrate 1 made of p-type single crystal silicon or the like has an nMIS formation region 1A and a pMIS formation region 1B which are defined by the element isolation region 2 and are electrically isolated from each other, and the nMIS formation region 1A.
- a p-type well PW is formed in the semiconductor substrate 1 and an n-type well NW is formed in the semiconductor substrate 1 in the pMIS formation region 1B.
- a gate electrode (n-channel MISFET Qn) (Hf-containing insulating film (first gate insulating film) 5) functioning as a gate insulating film of the n-channel MISFET Qn.
- Metal gate electrode) GE1 is formed on the surface of the p-type well PW in the nMIS formation region 1A.
- the gate of the p-channel type MISFET Qp is interposed via the Hf-containing insulating film (second gate insulating film) 6 functioning as the gate insulating film of the p-channel type MISFET Qp.
- An electrode (metal gate electrode) GE2 is formed.
- the Hf-containing insulating film 5 and the Hf-containing insulating film 6 are formed directly on the surface (silicon surface) of the semiconductor substrate 1 (p-type well PW and n-type well NW) (that is, the interface layer 3 is omitted). However, at the interface between the Hf-containing insulating film 5 and the Hf-containing insulating film 6 and the semiconductor substrate 1 (p-type well PW and n-type well NW), the same interface layer (insulating layer as in the first embodiment) Insulating film) 3 is more preferable.
- the Hf-containing insulating film 5 and the Hf-containing insulating film 6 are each an insulating material film having a dielectric constant (relative dielectric constant) higher than that of silicon oxide, that is, a so-called High-k film (high dielectric constant film). Since the Hf-containing insulating film 5 functioning as the gate insulating film (high dielectric constant gate insulating film) of the n-channel type MISFET Qn is the same as that of the first embodiment, the specific description thereof is omitted here and the p-channel is omitted.
- the Hf-containing insulating film 6 that functions as a gate insulating film (high dielectric constant gate insulating film) of the type MISFET Qp will be described.
- the Hf-containing insulating film 6 is made of an insulating material containing Hf (hafnium) and O (oxygen) as main components, and further contains Al (aluminum).
- the Hf-containing insulating film 6 contains Hf (hafnium), O (oxygen), and Al (aluminum) as essential constituent elements, but in addition, one of N (nitrogen) and Si (silicon, silicon). Or it can also contain both.
- the reason why the Hf-containing insulating film 6 contains Al (aluminum) is to reduce the threshold value of the p-channel type MISFET Qp. Therefore, an HfAlO film, an HfAlON film, an HfAlSiON film, or an HfAlSiO film can be suitably used as the Hf-containing insulating film 6.
- the HfAlO film is an insulating material film composed of hafnium (Hf), aluminum (Al), and oxygen (O)
- the HfAlON film is composed of hafnium (Hf), aluminum (Al), and oxygen (O).
- the HfAlSiON film is an insulating material film composed of hafnium (Hf), aluminum (Al), silicon (Si), oxygen (O), and nitrogen (N)
- the HfAlSiO film is composed of hafnium (Hf). It is an insulating material film composed of aluminum (Al), silicon (Si), and oxygen (O).
- Each of the gate electrodes GE1 and GE2 includes a metal film (metal gate film) 7 in contact with a gate insulating film (Hf-containing insulating film 5 in the nMIS forming region 1A and Hf-containing insulating film 6 in the pMIS forming region 1B), and the metal film 7 It is composed of a laminated film (laminated structure) with the upper silicon film 8.
- the gate electrode GE1 has a metal film 7 in contact with the Hf-containing insulating film 5 which is a gate insulating film (high dielectric constant gate insulating film), and the gate electrode GE2 is a gate insulating film (high dielectric constant gate insulating film).
- each gate electrode GE1, GE2 is a so-called metal gate electrode (metal gate electrode). Since the metal film 7 is the same as that of the first embodiment, the description thereof is omitted here.
- the concentration (content ratio) of the rare earth element in the Hf-containing insulating film 5 is not uniform (constant) in the film thickness direction of the Hf-containing insulating film 5, and the semiconductor substrate
- the concentration (content) of the rare earth element is low in the region on one side (ie, the region in contact with the interface layer 3) and the region on the gate electrode GE1 side (ie, in the region in contact with the metal film 7), and the central region (center Part)), the concentration (content ratio) of rare earth elements is high.
- the Hf-containing insulating film 6 contains aluminum (Al), but the Al concentration (content ratio) of the Hf-containing insulating film 6 is in the film thickness direction of the Hf-containing insulating film 6.
- the concentration (content ratio) of Al is low in the region on the semiconductor substrate 1 side (that is, the region in contact with the interface layer 3) and the region on the gate electrode GE2 side (that is, the region in contact with the metal film 7), which is not uniform (constant).
- the Al concentration (content ratio) is high in the central region (central portion) in the film thickness direction. This will be described in more detail later.
- an n ⁇ type semiconductor region (extension region, LDD region) EX1 and an n + type having a higher impurity concentration than that are used as source / drain regions of the LDD structure of the n-channel type MISFET Qn.
- a semiconductor region (source / drain region) SD1 is formed.
- a source / drain region of the LDD structure of the p-channel type MISFET Qp as a source / drain region of the LDD structure of the p-channel type MISFET Qp, a p ⁇ type semiconductor region (extension region, LDD region) EX2 and p having a higher impurity concentration than that are used.
- a + type semiconductor region (source / drain region) SD2 is formed.
- the n + type semiconductor region SD1 has a higher impurity concentration and a deep junction depth than the n ⁇ type semiconductor region EX1
- the p + type semiconductor region SD2 has a higher impurity concentration and a junction depth than the p ⁇ type semiconductor region EX2. The depth is deep.
- nMIS formation region 1A the n ⁇ type semiconductor region EX1 is formed in alignment with the gate electrode GE1
- the n + type semiconductor region SD1 is formed in alignment with the sidewall SW provided on the side wall of the gate electrode GE1.
- the pMIS formation region 1B the p ⁇ type semiconductor region EX2 is formed in alignment with the gate electrode GE2, and the p + type semiconductor region SD2 is formed in alignment with the sidewall SW provided on the side wall of the gate electrode GE2.
- pMIS formation region 1B the p ⁇ type semiconductor region EX2 is formed in alignment with the gate electrode GE2
- the p + type semiconductor region SD2 is formed in alignment with the sidewall SW provided on the side wall of the gate electrode GE2.
- the n ⁇ type semiconductor region EX1 is located below the sidewall SW formed on the side wall of the gate electrode GE1, and is interposed between the channel region of the n channel type MISFET Qn and the n + type semiconductor region SD1.
- P ⁇ type semiconductor region EX2 is located below sidewall SW formed on the sidewall of gate electrode GE2, and is interposed between the channel region of p channel MISFET Qp and p + type semiconductor region SD2. Yes.
- a metal silicide layer (metal silicide film) 10 similar to that of the first embodiment is formed on the surfaces of the n + type semiconductor region SD 1, the p + type semiconductor region SD 2, and the silicon film 8.
- the formation of the metal silicide layer 10 can be omitted. However, if the metal silicide layer 10 is formed on the surfaces of the n + type semiconductor region SD1, the p + type semiconductor region SD2 and the silicon film 8, diffusion resistance and contact The resistance can be reduced.
- the metal silicide layer 10 is formed on the surface of the silicon film 8, the metal is formed on the gate electrodes GE 1 and GE 2 made of a laminated film (laminated structure) of the metal film 7 and the silicon film 8 on the metal film 7.
- the silicide layer 10 is formed. From another viewpoint, the metal silicide layer 10 is also included in the gate electrodes GE1 and GE2, and a laminated film (laminated structure) of the metal film 7, the silicon film 8 on the metal film 7, and the metal silicide layer 10 on the silicon film 8 is used. It can also be considered that the gate electrodes GE1 and GE2 are configured.
- an insulating film (interlayer insulating film) 11 described later, a contact hole CNT, a plug PG, a stopper insulating film 12, an insulating film 13 and a wiring M1 (see FIG. 47 and FIG. 48 described later), and an upper multilayer wiring structure are provided. Although formed, illustration and description thereof are omitted here.
- FIG. 33 is a manufacturing process flow chart showing a part of the manufacturing process of the present embodiment, and corresponds to FIG. 2 of the first embodiment.
- 34 to 48 are fragmentary cross-sectional views of the semiconductor device of the present embodiment during the manufacturing process.
- a semiconductor substrate (semiconductor wafer) 1 similar to that of the first embodiment is prepared (prepared) (step S1 in FIG. 33).
- the semiconductor substrate 1 on which the semiconductor device of the present embodiment is formed includes an nMIS formation region 1A, which is a region where an n-channel type MISFET is formed, and a pMIS formation region 1B, which is a region where a p-channel type MISFET is formed. And have.
- the element isolation region 2 is formed on the main surface of the semiconductor substrate 1 (step S2 in FIG. 33).
- the p-type well PW is formed in the region for forming the n-channel MISFET (nMIS formation region 1A) of the semiconductor substrate 1, and the n-type well NW is formed in the region for forming the p-channel MISFET (pMIS formation region 1B). It forms (step S3a of FIG. 33).
- the p-type well PW is formed, for example, by ion implantation of a p-type impurity such as boron (B), and the n-type well NW is formed of, for example, phosphorus (P) or arsenic (As). It is formed by ion implantation of n-type impurities.
- ion implantation for adjusting a threshold value of a MISFET to be formed later is performed on the upper layer portion of the semiconductor substrate 1. Can also be performed as needed.
- the surface of the semiconductor substrate 1 is cleaned (cleaned) by removing the natural oxide film on the surface of the semiconductor substrate 1 by wet etching using, for example, a hydrofluoric acid (HF) aqueous solution. Thereby, the surface (silicon surface) of the semiconductor substrate 1 (p-type well PW and n-type well NW) is exposed.
- HF hydrofluoric acid
- the same interface layer 3 as in the first embodiment is formed by the same method (step S4 in FIG. 33).
- the step of forming the interface layer 3 in step S4 can be omitted, the step of forming the interface layer 3 in step S4 is more preferably performed, and the reason is the same as in the first embodiment.
- the same Hf-containing film (Hf-containing layer) 4a as in the first embodiment is formed on the main surface of the semiconductor substrate 1, that is, on the interface layer 3 (FIG. 33).
- Step S5 Since the material, film thickness, film forming method, and the like of the Hf-containing film 4a are the same as those in the first embodiment, description thereof is omitted here.
- step S5 since the Hf-containing film 4a is formed over the entire main surface of the semiconductor substrate 1, it is formed in both the nMIS formation region 1A and the pMIS formation region 1B.
- the Hf-containing film 4a is a film for forming the Hf-containing insulating films 5 and 6 which are high dielectric constant gate insulating films of the n-channel type MISFET Qn and the p-channel type MISFET Qp.
- Al-containing film (Al-containing layer) 21 is formed on the main surface of the semiconductor substrate 1, that is, on the Hf-containing film 4a (step S31 in FIG. 33).
- the Al-containing film 21 is a film for forming the Hf-containing insulating film 6 that is a high dielectric constant gate insulating film of the p-channel type MISFET Qp.
- the Al-containing film 21 is a material film containing Al (aluminum).
- the Al-containing film 21 is most preferably an aluminum oxide film (AlO film, typically an Al 2 O 3 film) from the viewpoint of stability, but in addition, an aluminum oxynitride film (aluminum oxynitride film) , AlON film) or aluminum film (Al film) can also be used.
- the Al-containing film 21 can be formed by sputtering or ALD, and the film thickness (formed film thickness) is preferably in the range of 0.2 to 1 nm, for example, about 0.5 nm. .
- a reaction preventing mask layer (mask layer) 22 is formed on the main surface of the semiconductor substrate 1, that is, on the Al-containing film 21 (step 32 in FIG. 33).
- the reaction preventing mask layer 22 is provided to prevent the rare earth-containing film 4b to be formed later from reacting with the Hf-containing film 4a and the Al-containing film 21 in the pMIS formation region 1B.
- the reaction preventing mask layer 22 is preferably a metal nitride film or a metal carbide film, and particularly preferably a titanium nitride (TiN) film.
- the reaction preventing mask layer 22 can be formed by sputtering or the like, and the film thickness can be set to, for example, about 5 to 20 nm.
- step S32 since the reaction preventing mask layer 22 is formed on the entire main surface of the semiconductor substrate 1, it is formed on the Al-containing film 21 in the nMIS formation region 1A and the pMIS formation region 1B.
- the reaction preventing mask layer 22 and the Al-containing film 21 in the nMIS formation region 1A are selectively removed by etching (preferably wet etching or a combination of dry etching and wet etching). Then, the reaction preventing mask layer 22 and the Al-containing film 21 in the pMIS formation region 1B are left (step S33 in FIG. 33). As a result, in the nMIS formation region 1A, the Hf-containing film 4a is exposed, while in the pMIS formation region 1B, the Al-containing film 21 and the reaction preventing mask layer 22 thereon are formed on the Hf-containing film 4a. Maintained.
- step S33 a photoresist pattern (not shown) that covers the pMIS formation region 1B and exposes the nMIS formation region 1A is formed on the reaction preventing mask layer 22, and then the photoresist pattern is formed.
- the reaction preventing mask layer 22 in the nMIS formation region 1A is removed by etching, and then the Al-containing film 21 in the nMIS formation region 1A is removed by etching. Thereafter, the photoresist pattern is removed.
- a rare earth-containing film 4b is formed on the main surface of the semiconductor substrate 1 (step S6a in FIG. 33).
- the rare earth-containing film 4b is a film for forming the Hf-containing insulating film 5 which is a high dielectric constant gate insulating film of the n-channel type MISFET Qn.
- the step In S6a the rare earth-containing film 4b is formed on the Hf-containing film 4a in the nMIS formation region 1A, and is formed on the reaction preventing mask layer 22 in the pMIS formation region 1B.
- the rare earth-containing film 4b and the Hf-containing film 4a are in contact with each other in the nMIS formation region 1A, but the rare earth-containing film 4b and the Al-containing film 21 (and the Hf-containing film 4a) are in the pMIS formation region 1B. Since the reaction preventing mask layer 22 is interposed therebetween, they are not in contact with each other. Since the material, film thickness, film forming method, and the like of the rare earth-containing film 5 are the same as those in the first embodiment, description thereof is omitted here.
- step S34 in FIG. 33 heat treatment is performed on the semiconductor substrate 1 (step S34 in FIG. 33).
- the heat treatment step in step S34 can be performed in an inert gas atmosphere (even in a nitrogen gas atmosphere) with the heat treatment temperature preferably in the range of 600 to 1000 ° C.
- the Hf-containing film 4a and the rare earth-containing film 4b react (mix, mix, interdiffusion) in the nMIS formation region 1A, and as shown in FIG.
- An Hf-containing film (reaction layer) 4d that is a reaction layer (mixed layer, mixing layer) with the containing film 4b is formed.
- the heat treatment in step S34 causes the Hf-containing film 4a and the Al-containing film 21 to react (mixing, mixing, mutual diffusion) in the pMIS formation region 1B, and as shown in FIG. 38, the Hf-containing film 4a.
- An Hf-containing film (reaction layer) 4e which is a reaction layer (mixed layer, mixing layer) between the Al and Al-containing film 21, is formed.
- step S34 Since the Hf-containing film 4d formed in the nMIS formation region 1A by the heat treatment in step S34 is the same as the Hf-containing film 4d formed in step S21 in the first embodiment, description thereof is omitted here. .
- the Hf-containing film 4a contains hafnium (Hf) and oxygen (O) as main components
- the Al-containing film 21 contains Al (aluminum) as main components
- Hf in the pMIS formation region 1B contains Hf in the pMIS formation region 1B.
- the Hf-containing film 4e formed by the reaction between the film 4a and the Al-containing film 21 is an insulating film containing hafnium (Hf), oxygen (O), and aluminum (Al) as main components.
- the Hf-containing film 4e When the Hf-containing film 4a contains not only hafnium (Hf) and oxygen (O) but also nitrogen (N), the Hf-containing film 4e has hafnium (Hf) and oxygen (O). Not only aluminum (Al) but also nitrogen (N) is contained.
- the Hf-containing film 4a contains not only hafnium (Hf) and oxygen (O) but also Si (silicon, silicon)
- the Hf-containing film 4e has hafnium (Hf) and oxygen (O ) And aluminum (Al) as well as Si (silicon, silicon).
- the rare earth-containing film 4b and the Al-containing film 21 (and the Hf-containing film 4a) are not in contact with each other with the reaction preventing mask layer 22 interposed therebetween.
- the Al-containing film 21 and the Hf-containing film 4a do not react with the rare earth-containing film 4b, and the rare earth elements constituting the rare earth-containing film 4b are not introduced (diffused) into the Hf-containing film 4e in the pMIS formation region 1B.
- the Hf-containing film 4e is a film having the following composition depending on the type of the Hf-containing film 4a. That is, when the Hf-containing film 4a is an HfO film, the Hf-containing film 4e is an HfAlO film. When the Hf-containing film 4a is an HfON film, the Hf-containing film 4e is an HfAlON film, and the Hf-containing film 4a. When the HfSiO film is an HfSiO film, the Hf-containing film 4e is an HfAlSiO film.
- the Hf-containing film 4e is an HfAlSiON film.
- the Al-containing film 21 is an aluminum oxynitride film
- the Hf-containing film 4e is a film having the following composition depending on the type of the Hf-containing film 4a. That is, when the Hf-containing film 4a is an HfO film, the Hf-containing film 4e is an HfAlON film.
- the Hf-containing film 4a is an HfON film
- the Hf-containing film 4e is an HfAlON film, and the Hf-containing film 4a.
- the Hf-containing film 4e is an HfAlSiON film.
- the Hf-containing film 4e is an HfAlSiON film.
- the Hf-containing film 4a and the Al-containing film 21 are formed in order from the bottom, and these react to form the Hf-containing film 4e.
- the Hf-containing film 4a contains Hf (hafnium) but contains Al (aluminum).
- the Al-containing film 21 contains Al (aluminum) but does not contain Hf (hafnium).
- the Hf-containing film 4e formed in the pMIS formation region 1B does not have a uniform composition in the film thickness direction, and maintains the composition distribution before the reaction between the Hf-containing film 4a and the Al-containing film 21 to some extent. This will be described in more detail later.
- step S34 of the present embodiment the Hf-containing film 4a and the rare earth-containing film 4b are formed in order from the bottom, and these react to react with each other to form the Hf-containing film 4d. Therefore, the Hf-containing film 4d formed in the nMIS formation region 1A is not uniform in composition in the film thickness direction, like the Hf-containing film 4d of the first embodiment, and the Hf-containing film 4a and the rare earth The composition distribution before the reaction of the containing film 4b is maintained to some extent.
- the rare earth-containing film 4b in the pMIS formation region 1B hardly reacts with the reaction preventing mask layer 22.
- Remain That is, as a material for the reaction preventing mask layer 22, a material that is stable even at the heat treatment temperature of the heat treatment process in step S24 and hardly reacts with any of the Hf-containing film 4a, the Al-containing film 21, and the rare earth-containing film 4b is selected. It is. As such a material, metal nitride or metal carbide is suitable, and titanium nitride (TiN) is particularly suitable.
- step S4 If the interface layer 3 is formed in step S4 before the Hf-containing film 4a is formed in step S5, the reaction between the Hf-containing film 4a and the lower interface layer 3 is suppressed during the heat treatment in step S34.
- the rare earth-containing film 4b (unreacted rare earth-containing film 4b) that has not reacted in the heat treatment process in step S34 is etched (preferably wet etching). Then, the reaction preventing mask layer 22 is removed by etching (preferably wet etching) (step S25 in FIG. 33). As a result, the Hf-containing film 4d is exposed in the nMIS formation region 1A, and the Hf-containing film 4e is exposed in the pMIS formation region 1B.
- step S34 it is preferable to perform the heat treatment step in step S34.
- the heat treatment process in step S34 can be omitted.
- an Hf-containing film 4c is formed on the main surface of the semiconductor substrate 1, that is, on the Hf-containing film 4d in the nMIS formation region 1A and the Hf-containing film 4e in the pMIS formation region 1B.
- Step 7a in FIG. 33 Since the material, film thickness, film forming method, and the like of the Hf-containing film 4c are the same as those in the first embodiment, description thereof is omitted here.
- step S7a in the nMIS formation region 1A, the Hf-containing film 4c is formed on the Hf-containing film 4d, and in the pMIS formation region 1B, the Hf-containing film 4c is formed on the Hf-containing film 4e.
- the Hf-containing film 4c is a film for forming the Hf-containing insulating films 5 and 6 that are high dielectric constant gate insulating films of the n-channel type MISFET Qn and the p-channel type MISFET Qp.
- a metal film 7 for a metal gate is formed on the main surface of the semiconductor substrate 1, that is, on the Hf-containing film 4c (step S8 in FIG. 33). . Since the material, film thickness, film forming method, and the like of the metal film 7 are the same as those in the first embodiment, the description thereof is omitted here.
- a silicon film 8 similar to that of the first embodiment is formed on the main surface of the semiconductor substrate 1, that is, on the metal film 7 (step S9 in FIG. 33). Although it is possible to omit the step of forming the silicon film 8 in step S9, it is more preferable to perform the step of forming the silicon film 8 in step S9 for the same reason as in the first embodiment.
- the interface layer 3, the Hf-containing film 4d, the Hf-containing film 4c, the metal film 7 and the silicon film 8 are stacked in this order from the bottom on the semiconductor substrate 1 (p-type well PW).
- the interface layer 3, the Hf-containing film 4e, the Hf-containing film 4c, the metal film 7, and the silicon film 8 are sequentially stacked from the bottom on the semiconductor substrate 1 (n-type well NW). It is in the state.
- a photoresist pattern PR1a is formed on the silicon film 8 by using a photolithography method. Then, using this photoresist pattern PR1a as an etching mask, the laminated film of the silicon film 8 and the metal film 7 is etched (preferably dry-etched) and patterned to form the metal film 7 as shown in FIG. Then, gate electrodes GE1 and GE2 made of the silicon film 8 on the metal film 7 are formed (step S10a in FIG. 33). Thereafter, the photoresist pattern PR1a is removed.
- FIG. 42 shows a state where the photoresist pattern PR1a is removed.
- the gate electrode GE1 is formed on the Hf-containing film 4c in the nMIS formation region 1A, and the gate electrode GE2 is formed on the Hf-containing film 4c in the pMIS formation region 1B. That is, the gate electrode GE1 composed of the metal film 7 and the silicon film 8 on the metal film 7 is formed by stacking the interface layer 3, the Hf-containing film 4d, and the Hf-containing film 4c on the surface of the p-type well PW in the nMIS formation region 1A.
- a gate electrode GE2 formed through the film and made of the metal film 7 and the silicon film 8 on the metal film 7 is formed on the surface of the n-type well NW in the pMIS formation region 1B, the interface layer 3, the Hf-containing film 4e, and the Hf It is formed through a laminated film of the containing film 4c.
- the Hf-containing film 4c and the Hf-containing film 4d located below the gate electrode GE1 and the Hf-containing film 4c and the Hf-containing film 4e located below the gate electrode GE2 are formed by the dry etching in step S10a and the subsequent wet etching. It remains without being removed.
- the Hf-containing film 4c and Hf-containing film 4d that are not covered with the gate electrode GE1 and the Hf-containing film 4c and Hf-containing film 4e that are not covered with the gate electrode GE2 are the silicon film 8 and the metal in step S10a.
- the film 7 is removed by dry etching at the time of patterning or subsequent wet etching.
- n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into regions on both sides of the gate electrode GE1 of the p-type well PW in the nMIS formation region 1A.
- a ⁇ type semiconductor region EX1 is formed, and a p ⁇ type semiconductor region EX2 is formed by ion-implanting p-type impurities such as boron (B) into regions on both sides of the gate electrode GE2 of the n-type well NW in the pMIS formation region 1B.
- the pMIS formation region 1B is covered with a photoresist film (not shown) as an ion implantation blocking mask, and the semiconductor substrate 1 (p type well PW in the nMIS formation region 1A) is covered. ) Is ion-implanted using the gate electrode GE1 as a mask.
- the nMIS formation region 1A is covered with another photoresist film (not shown) as an ion implantation blocking mask, and the semiconductor substrate 1 (pMIS formation region 1B) Ions are implanted into the n-type well NW) using the gate electrode GE2 as a mask.
- the n ⁇ type semiconductor region EX1 may be formed first, or the p ⁇ type semiconductor region EX2 may be formed first.
- ion implantation for forming the halo region can be performed before or after the formation of the n ⁇ type semiconductor region EX1 and the p ⁇ type semiconductor region EX2.
- a halo region (p-type halo region) is formed so as to wrap around the n ⁇ type semiconductor region EX1
- a p ⁇ type is formed in the nMIS formation region 1A.
- a halo region (n-type halo region) is formed so as to wrap around the semiconductor region EX2.
- a sidewall SW made of an insulator is formed on the sidewalls of the gate electrodes GE1 and GE2 in the same manner as in the first embodiment (step S12 in FIG. 33).
- the n + type semiconductor region SD1 is formed in the p type well PW of the nMIS formation region 1A by ion implantation, and the p + type semiconductor region SD2 is formed in the n type well NW of the pMIS formation region 1B by other ion implantation. (Step S13a in FIG. 33).
- n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into regions on both sides of the gate electrode GE1 and the sidewall SW of the p-type well PW in the nMIS formation region 1A. Can be formed.
- the n + type semiconductor region SD1 has a higher impurity concentration and a deep junction depth than the n ⁇ type semiconductor region EX1.
- the pMIS formation region 1B is covered with a photoresist film (not shown) as an ion implantation blocking mask, and the semiconductor substrate 1 (p-type well) in the nMIS formation region 1A is covered.
- PW is ion-implanted using the gate electrode GE1 and the sidewall SW on the side wall as a mask. Therefore, the n ⁇ type semiconductor region EX1 is formed in alignment with the gate electrode GE1, and the n + type semiconductor region SD1 is formed in alignment with the sidewall SW on the side wall of the gate electrode GE1.
- the p + type semiconductor region SD2 is formed by ion-implanting p-type impurities such as boron (B) into the regions on both sides of the gate electrode GE2 and the sidewall SW of the n-type well NW in the pMIS formation region 1B. Can do.
- the p + type semiconductor region SD2 has a higher impurity concentration and a deep junction depth than the p ⁇ type semiconductor region EX2.
- the nMIS formation region 1A is covered with another photoresist film (not shown) as an ion implantation blocking mask, and the semiconductor substrate 1 (n in the pMIS formation region 1B) Ions are implanted into the mold well NW) using the gate electrode GE2 and the sidewall SW on the side wall as a mask.
- the p ⁇ type semiconductor region EX2 is formed in alignment with the gate electrode GE2
- the p + type semiconductor region SD2 is formed in alignment with the sidewall SW on the side wall of the gate electrode GE2.
- the n + type semiconductor region SD1 may be formed first, or the p + type semiconductor region SD2 may be formed first.
- the silicon film 8 constituting the gate electrode GE1 in the nMIS formation region 1A is doped with n-type impurities in the ion implantation process for forming the n ⁇ type semiconductor region EX1 and the ion implantation process for forming the n + type semiconductor region SD1. And an n-type silicon film.
- the silicon film 8 constituting the gate electrode GE2 in the pMIS formation region 1B is doped with p-type impurities in the ion implantation process for forming the p ⁇ type semiconductor region EX2 and the ion implantation process for forming the p + type semiconductor region SD2.
- it can be a p-type silicon film.
- the n + type semiconductor region SD1 functions as a source / drain region of the n channel MISFET Qn
- the p + type semiconductor region SD2 functions as a source / drain region of the p channel MISFET Qp.
- the n + type semiconductor region SD1 forming step in step S13a can be regarded as a step of performing ion implantation for forming the source / drain regions of the n-channel type MISFET Qn
- the p + type semiconductor region SD2 forming step in step S13a Can be regarded as a step of performing ion implantation for forming the source / drain regions of the p-channel type MISFET Qp.
- Step S14 After performing ion implantation for forming the n + type semiconductor region SD1 and ion implantation for forming the p + type semiconductor region SD2 in step S13a, heat treatment (annealing treatment, activation annealing) for activating the introduced impurity is performed.
- annealing treatment, activation annealing for activating the introduced impurity is performed.
- Step S14 in FIG. 33.
- Impurities introduced into the n ⁇ type semiconductor region EX1, the p ⁇ type semiconductor region EX2, the n + type semiconductor region SD1, the p + type semiconductor region SD2, the silicon film 8 and the like by the ion implantation in steps S11a and S13a are removed in step S14. It can be activated by heat treatment. Since the heat treatment conditions in step S14 are the same as those in the first embodiment, the description thereof is omitted here.
- step S14 Since the heat treatment in step S14 is a high-temperature heat treatment, the Hf-containing film 4d and the Hf-containing film 4c react (mix, mix, interdiffusion) in the nMIS formation region 1A, and the Hf-containing film in the pMIS formation region 1B. 4e reacts with the Hf-containing film 4c (mixing, mixing, mutual diffusion). That is, as shown in FIG.
- the Hf-containing film 4d reacts with the Hf-containing film 4c (mixing, mixing, mutual diffusion) to form the Hf-containing insulating film 5, and the pMIS formation region In 1B, the Hf-containing film 4e and the Hf-containing film 4c react (mix, mix, interdiffusion) to form the Hf-containing insulating film 6.
- the Hf-containing insulating film 5 formed in the nMIS formation region 1A by the heat treatment in step S14 is the same as the Hf-containing insulating film 5 formed in step S14 in the first embodiment. Omitted.
- the Hf-containing film 4a and the Al-containing film react with each other by the heat treatment in step S34 to form an Hf-containing film 4e that is a reaction layer of both, and in the heat treatment in step S14, this Hf-containing film 4e.
- the Hf-containing film 4c react to form the Hf-containing insulating film 6.
- the Hf-containing insulating film 6 becomes an insulating film containing the elements constituting the Hf-containing film 4a, the elements constituting the Al-containing film 4b, and the elements constituting the Hf-containing film 4c. It is the same with or without heat treatment.
- the Hf-containing film 4a and the Hf-containing film 4c contain hafnium (Hf) and oxygen (O) as the main components, and the Al-containing film 21 contains aluminum (Al) as the main components.
- the insulating film 6 is an insulating film containing hafnium (Hf), oxygen (O), and aluminum (Al) as main components.
- the Hf-containing insulating film 6 In addition to hafnium (Hf), oxygen (O), and aluminum (Al), nitrogen (N) is also contained. If one or both of the Hf-containing film 4a and the Hf-containing film 4c contain not only hafnium (Hf) and oxygen (O) but also Si (silicon, silicon), the Hf-containing insulating film 6 These contain not only hafnium (Hf), oxygen (O) and aluminum (Al) but also Si (silicon, silicon).
- the Al-containing film 21 is preferably an aluminum oxide film as described above, but an aluminum oxynitride film or an aluminum film can also be used. Since the Hf-containing films 4a and 4c contain oxygen (O), the Hf-containing insulating film 6 contains oxygen (O) regardless of whether the Al-containing film 21 is an aluminum oxide film, an aluminum oxynitride film, or an aluminum film. ). When the Al-containing film 21 is an aluminum oxynitride film, the Hf-containing insulating film 6 contains nitrogen (N).
- the Hf-containing insulating film 6 is a film having the following composition depending on the type of the Hf-containing films 4a and 4c. That is, when both of the Hf-containing films 4a and 4c are HfO films, the Hf-containing insulating film 6 is an HfAlO film, and when one of the Hf-containing films 4a and 4c is an HfO film and the other is an HfON film, When both the containing films 4a and 4c are HfON films, the Hf-containing insulating film 6 is an HfAlON film.
- the Hf-containing insulating film 6 is an HfAlSiO film.
- the Hf-containing insulating film 6 is an HfLnAlON film.
- the Hf-containing insulating film 6 can be used regardless of whether the other of the Hf-containing films 4a and 4c is an HfO film, an HfON film, an HfSiO film, or an HfSiON film. Becomes an HfAlSiON film.
- the Hf-containing insulating film 6 is a film having the following composition depending on the type of the Hf-containing films 4a and 4c. That is, when both the Hf-containing films 4a and 4c are HfO films, when one of the Hf-containing films 4a and 4c is an HfO film and the other is an HfON film, and when both the Hf-containing films 4a and 4c are HfON films.
- the Hf-containing insulating film 6 becomes an HfAlON film.
- the Hf-containing film 4a or 4c is Hf-containing regardless of whether the other of the Hf-containing films 4a and 4c is an HfO film, an HfON film, an HfSiO film, or an HfSiON film.
- the insulating film 6 is an HfAlSiON film.
- the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c are formed in this order from below, and these react to form the Hf-containing insulating film 6, and the Hf-containing films 4a and 4c are Hf (hafnium).
- the rare earth element nor aluminum (Al) is contained, and the Al-containing film 21 contains Al (aluminum) but does not contain Hf (hafnium).
- the formed Hf-containing insulating film 6 is not uniform in composition in the film thickness direction, and maintains the composition distribution before the reaction of the Hf-containing film 4a, the Al-containing film 21 and the Hf-containing film 4c to some extent. . This will be described in more detail later.
- an n-channel type MISFET Qn is formed as a field effect transistor in the nMIS formation region 1A, and a p-channel type is formed as a field effect transistor in the pMIS formation region 1B.
- a MISFET Qp is formed.
- the gate electrode GE1 functions as the gate electrode (metal gate electrode) of the n-channel type MISFET Qn, and the Hf-containing insulating film 5 (and the interface layer 3 below the gate electrode GE1) is the gate insulating film of the n-channel type MISFET Qn. Function as. Then, an n-type semiconductor region (impurity diffusion layer) that functions as the source or drain of the n-channel type MISFET Qn is formed by the n + -type semiconductor region SD1 and the n ⁇ -type semiconductor region EX1.
- the gate electrode GE2 functions as a gate electrode (metal gate electrode) of the p-channel type MISFET Qp, and the Hf-containing insulating film 6 (and the interface layer 3 therebelow) under the gate electrode GE2 is the gate of the p-channel type MISFET Qp. Functions as an insulating film.
- a p-type semiconductor region (impurity diffusion layer) functioning as a source or drain of the p-channel type MISFET Qp is formed by the p + -type semiconductor region SD2 and the p ⁇ -type semiconductor region EX2.
- the first embodiment is applied on the surfaces of the n + type semiconductor region SD1, the p + type semiconductor region SD2 and the silicon film 8 (the silicon film 8 constituting the gate electrodes GE1 and GE2).
- the metal silicide layer 10 similar to the above is selectively formed by the salicide process similar to that of the first embodiment. Specifically, after the surfaces of the n + type semiconductor region SD1 and the p + type semiconductor region SD2 are cleaned, the semiconductor substrate 1 including the n + type semiconductor region SD1, the p + type semiconductor region SD2, and the silicon film 8 is included. A metal film made of Co (cobalt), Ni (nickel), Pt (platinum), or the like is formed on the main surface.
- the metal film is reacted with the n + type semiconductor region SD1, the p + type semiconductor region SD2 and the upper layer portion of the silicon film 8 by heat treatment to form the metal silicide layer 10, and then the unreacted portion of the metal film is removed. It may be removed by wet etching or the like.
- the metal silicide layer 10 has an effect of reducing diffusion resistance and contact resistance, the formation thereof can be omitted if unnecessary.
- Subsequent steps are substantially the same as those in the first embodiment. That is, as shown in FIG. 47, an insulating film 11 similar to that of the first embodiment is formed on the main surface of the semiconductor substrate 1 so as to cover the gate electrodes GE1 and GE2 and the sidewall SW. Then, after forming a contact hole CNT in the insulating film 11 as in the first embodiment, a plug PG is formed in the contact hole CNT as in the first embodiment. The contact hole CNT and the plug PG filling the contact hole CNT are formed in the n + type semiconductor region SD1 and the p + type semiconductor region SD2 and the upper portions of the gate electrodes GE1 and GE2. Then, as shown in FIG.
- the stopper insulating film 12 and the wiring forming insulating film 13 similar to those of the first embodiment are sequentially formed on the insulating film 11 in which the plug PG is embedded, and then the above-mentioned Similar to the first embodiment, the first layer wiring M1 is formed by a single damascene method.
- the wiring 1 is formed so as to fill the wiring groove 14 formed in the insulating film 13 and the stopper insulating film 12.
- the wiring M1 is electrically connected to the n + type semiconductor region SD1 and p + type semiconductor region SD2 for the source or drain of the n channel MISFET Qn and p channel MISFET Qp through the plug PG.
- the second and subsequent wirings are formed by a dual damascene method or the like, but illustration and description thereof are omitted here.
- the wiring M1 and the upper layer wiring are not limited to damascene wiring, and may be formed by patterning a conductor film for wiring. For example, tungsten wiring or aluminum wiring can be used.
- the structure in the nMIS formation region 1A of the semiconductor device of the present embodiment is the same as the structure of the region in which the n-channel type MISFET Qn of the semiconductor device of the first embodiment is formed.
- the manufacturing process of the nMIS formation region 1A of the semiconductor device of the present embodiment is basically the same as the manufacturing process according to the process flow of FIG. That is, the process flow of FIG. 17 plus steps S31, S32, S33, and S35 corresponds to the manufacturing process of the nMIS formation region 1A of the semiconductor device of the present embodiment.
- the heat treatment process in step S34 corresponds to the heat treatment process in step S21 of the first embodiment.
- Steps S31, S32, S33, and S35 are steps performed to form the p-channel type MISFET Qp in the pMIS formation region 1B, and in order to form the n-channel type MISFET Qn in the nMIS formation region 1A, Does not contribute. For this reason, the manufacturing process (n-channel MISFET Qn forming process) of the nMIS forming region 1A in the present embodiment can be regarded as substantially the same as in the first embodiment.
- the same effect as that of the first embodiment can be obtained for the n-channel type MISFET Qn in the nMIS formation region 1A. For this reason, repeated description of the effects that are the same as those in the first embodiment is omitted, and here, the specific effects of the present embodiment will be described.
- the threshold value of the n-channel type MISFET Qn can be lowered, and the p-channel type
- Al (aluminum) into the Hf-containing insulating film 6 that is the Hf-based gate insulating film of the MISFET Qp
- the threshold value of the p-channel MISFET Qp can be lowered.
- both the n-channel type MISFET Qn and the p-channel type MISFET Qp can be lowered in threshold value.
- the rare earth element when a rare earth element is introduced into the Hf-based gate insulating film, the rare earth element easily diffuses to the metal gate electrode or the semiconductor substrate side, causing the above-described various problems. This phenomenon is peculiar when a rare earth element is introduced into the Hf-based gate insulating film.
- Al aluminum
- the same problem does not occur. This is thought to be because Al rarely diffuses to the metal gate electrode or the semiconductor substrate side compared to the rare earth element easily diffusing to the metal gate electrode or the semiconductor substrate side.
- the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c are used to form the Hf-containing insulating film 5 that is the high dielectric constant gate insulating film of the n-channel type MISFET Qn.
- the above-mentioned three layers are used, and these are formed in the order of the Hf-containing film 4a, the rare-earth-containing film 4b, and the Hf-containing film 4c. ) Can be prevented, and characteristics (performance) can be improved.
- the p-channel type MISFET Qp such a problem does not occur.
- the Hf-containing insulating film 4a, the Al-containing film 21 and the Hf-containing film 4c are used. Even if the film 6 is formed, the Hf-containing insulating film 6 may be formed using two layers of the Hf-containing film 4 a and the Al-containing film 21.
- the Hf-containing film 4a and the Al are formed in the p-channel type MISFETQp as in the present embodiment to form the Hf-containing insulating film 6. It is preferable to use three layers of the containing film 21 and the Hf-containing film 4c and to form these in the order of the Hf-containing film 4a, the Al-containing film 21 and the Hf-containing film 4c. That is, in order to form the Hf-containing insulating film 5 of the n-channel type MISFET Qn, the three layers of the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c are used.
- the containing insulating film 6 In order to form the containing insulating film 6, three layers of the Hf-containing film 4a, the Al-containing film 21 and the Hf-containing film 4c are used, and these layers are in order of the Hf-containing film 4a, the Al-containing film 21 and the Hf-containing film 4c. It forms.
- the Hf-containing gate insulating film in step 7a Since the step of selectively removing the Hf-containing film 4c in the pMIS formation region 1B after forming the containing film 4c is required, the number of manufacturing steps of the semiconductor device is increased.
- the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c used for forming the Hf-containing insulating film 5 of the channel MISFET Qn are used among the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c used for forming the Hf-containing insulating film 5 of the channel MISFET Qn. Since it is also used to form the Hf-containing insulating film 6 without being removed in the pMIS formation region 1B, the number of CMISFET manufacturing steps can be reduced.
- the characteristics (performance) of the n-channel MISFET can be improved as described in the first embodiment.
- the Hf-containing insulating film 6 is formed by using three layers of the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c.
- the Al-containing film 21 and the Hf-containing film 4c are used to reduce the threshold value of both the n-channel MISFET and the n-channel MISFET and to produce a CMISFET. Can be reduced.
- the Hf-containing film 4a, the rare earth-containing film 4b, and the Hf-containing film 4c are sequentially formed from the bottom in the nMIS formation region 1A, and these react to form the Hf-containing insulating film 5.
- the Hf-containing film 4a, the Al-containing film 21, and the Hf-containing film 4c are formed in order from the bottom, and these react to form the Hf-containing insulating film 6. Therefore, inevitably, the concentration distribution of rare earth elements and Hf in the thickness direction of the Hf-containing insulating film 5 is as shown in FIG. 26, and the concentration distribution of Al and Hf in the thickness direction of the Hf-containing insulating film 6 is As shown in FIG. This will be described below.
- FIG. 49 is an explanatory diagram of the p-channel type MISFET Qp in the pMIS formation region 1B in the semiconductor device of the present embodiment, and shows a partial enlarged cross-sectional view of the region near the gate insulating film.
- 50 is a graph showing the Al concentration distribution and the Hf concentration distribution in the thickness direction, and the Al concentration distribution and the Hf concentration distribution at positions along the line 16a in FIG. 49 correspond to FIG. Therefore, the horizontal axis of the graph of FIG. 50 corresponds to the position along the line 16a in FIG. 49, the vertical axis of the graph of FIG. 50 corresponds to the Al concentration and the Hf concentration, and in FIG.
- the distribution is indicated by a solid line, and the concentration distribution of Hf is indicated by a dotted line.
- the Al concentration and the Hf concentration on the vertical axis of the graph of FIG. 50 are shown in arbitrary units.
- the direction of the line 16a in FIG. 50 is the thickness direction (that is, the direction perpendicular to the main surface of the semiconductor substrate 1).
- the Al-containing film 21 contains Al (aluminum), but the Hf-containing films 4a and 4c contain neither rare earth elements nor Al (aluminum), and the Hf-containing films 4a and 4c have Hf (hafnium).
- the Al-containing film 21 does not contain Hf (hafnium).
- the concentration distribution in the thickness direction of each element in the actually formed Hf-containing insulating film 6 is not uniform, and the composition distribution before the reaction of the Hf-containing film 4a, the Al-containing film 21, and the Hf-containing film 4c. A non-uniform distribution maintained to some extent.
- the n-channel type MISFET Qn in the nMIS formation region 1A in the semiconductor device of the present embodiment are basically the same as those in the first embodiment, the n-channel type MISFET Qn in the MIS formation region 1A.
- the graph is the same as the graph in FIG.
- the layer structure from the interface layer 3 to the metal film 7 can be obtained by replacing the rare earth-containing film 4b and the Al-containing film 21.
- the manufacturing method is basically the same as that of the n-channel type MISFET Qn in the nMIS formation region 1A. Therefore, the Al concentration distribution in the thickness direction of the insulating film 6 shown in FIG. 50 is the same distribution as the rare earth concentration distribution in the thickness direction of the insulating film 5 as shown in FIG. 26, and the insulation shown in FIG.
- the Hf concentration distribution in the thickness direction of the film 6 is the same distribution as the Hf concentration distribution in the thickness direction of the insulating film 5 as shown in FIG.
- the Al concentration distribution in the thickness direction of the Hf-containing insulating film 6 does not become uniform (constant), but peaks in the central region in the thickness direction of the Hf-containing insulating film 6 (maximum). the one having a value) P 4. That is, the concentration distribution of Al (aluminum) in the thickness direction of the Hf-containing insulating film (second gate insulating film) 6 is closer to the lower surface and the upper surface of the Hf-containing insulating film 6 than in the central region of the Hf-containing insulating film 6. The concentration of Al (aluminum) is low.
- the reason for this Al concentration distribution is that, as described in the first embodiment, the rare earth concentration distribution in the thickness direction of the Hf-containing insulating film 5 has a peak P 1 in the central region in the thickness direction of the Hf-containing insulating film 5.
- the reason is basically the same if the rare earth element (rare earth-containing film 4b) and Al (Al-containing film 21) are interchanged.
- the region that was originally the Al-containing film 21 compared to the region that was originally the Al-containing film 21 (intermediate layer portion in the thickness direction of the Hf-containing insulating film 6), the region that was originally the Hf-containing films 4 a and 4 c ( In the lower layer portion and the upper layer portion of the Hf-containing insulating film 6, the Al concentration is low.
- the source is the peak P 4 is formed in the region and the Al-containing film 21 (intermediate layer portion of the Hf-containing insulating film 6), more specifically, based on the Al
- the peak P 4 is formed in the vicinity of the central portion in the thickness direction of the region (the intermediate layer portion of the Hf-containing insulating film 6) that was the containing film 21.
- the semiconductor substrate 1 side and the gate electrode GE2 side of the peak P 4 a state in which Al concentration is reduced gradually.
- the Al concentration distribution in the thickness direction of the Hf-containing insulating film 6 becomes one mountain-shaped distribution, has a peak P 4 in the center region in the thickness direction of the Hf-containing insulating film 6 and has the maximum Al concentration, and the peak P 4 position Al concentration monotonously decreases from (central region in the thickness direction) in the semiconductor substrate 1 side, Al concentration decreases monotonically toward the metal film 7 side from the position (center region in the thickness direction) of the peak P 4 .
- the concentration distribution of Al in the thickness direction of the Hf-containing insulating film 6 has a peak P 4 in the central region in the thickness direction of the Hf-containing insulating film 6, the lower surface of the Hf-containing insulating film 6 (i.e. Hf-containing insulating film 6 And the vicinity thereof and the upper surface of the Hf-containing insulating film 6 (that is, the interface between the Hf-containing insulating film 6 and the metal film 7) and the vicinity thereof, the central region in the thickness direction of the Hf-containing insulating film 6 (above)
- the concentration of Al (aluminum) is lower than the peak P 4 ).
- the Hf concentration distribution in the thickness direction of the Hf-containing insulating film 6 is not uniform (constant), but double peaks (peaks P 5 and P5 in the thickness direction of the Hf-containing insulating film 6). It has a peak P 6 ).
- the source is formed in the region was Hf-containing film 4a (lower layer portion of the Hf-containing insulating film 6)
- the other peak P 6 of the double peak in the Hf-containing insulating film 6 the source is formed in the region was Hf-containing film 4c (upper layer portion of the Hf-containing insulating film 6).
- the reason why the Hf concentration distribution in the thickness direction of the Hf-containing insulating film 6 has a double peak is basically the same as the Hf concentration distribution in the thickness direction of the Hf-containing insulating film 5 has a double peak. And, in this semiconductor substrate 1 side than the peak P 5 and the gate electrode GE2 side than the peak P 6, Hf concentration decreases gradually or rapidly. Further, the Hf concentration takes the minimum value MINa at a position between the peak P 5 and the peak P 6 (position in the thickness direction), and from the peak P 5 to the minimum value MINa, and from the peak P 6 to the minimum value MINa. Over time, the Hf concentration gradually decreases.
- the Hf concentration distribution in the thickness direction of the Hf-containing insulating film 6 becomes two mountain-shaped distributions and has a double peak (P 5 , P 6 ), and moves from the position of the peak P 5 toward the semiconductor substrate 1 side.
- Hf concentration Te decreasing monotonously Hf concentration is monotonously decreased toward the minimum value MINa from the position of the peak P 5
- Hf concentration is monotonously decreased toward the minimum value MINa from the position of the peak P 6
- the Hf concentration monotonously decreases from the position toward the metal film 7 side.
- the source is the peak P 4 is formed in the region and the Al-containing film 21 (intermediate layer portion of the Hf-containing insulating film 6), originally was Hf-containing film 4a region It said peak P 5 in the (lower layer portion of the Hf-containing insulating film 6) is formed, based on the above peak P 6 is formed in the region was Hf-containing film 4c (upper layer portion of the Hf-containing insulating film 6) . Therefore, as shown in FIG. 50, in the thickness direction of the Hf-containing insulating film 6, between the position of the position and the peak P 6 of the peak P 5, the peak P 4 will be located.
- a manufacturing process in the case where the reaction preventing mask layer 22 is provided in the pMIS formation region 1B to prevent the reaction between the Hf-containing film 4a and the rare earth-containing film 4b in the pMIS formation region 1B.
- the manufacturing process described with reference to FIG. 48 has been described.
- a reaction preventing mask layer 22 may be provided in the nMIS formation region 1A to prevent the reaction between the Hf-containing film 4a and the Al-containing film 21 in the nMIS formation region 1A.
- the manufacturing process will be described with reference to FIGS. Note that differences from the manufacturing process described with reference to FIGS. 34 to 48 will be mainly described.
- 51 to 52 are main-portion cross-sectional views during another manufacturing process of the semiconductor device of the present embodiment.
- the rare earth-containing film 4b is formed on the Hf-containing film 4a instead of the Al-containing film 21 in step S31 (see FIG. 51).
- the reaction preventing mask layer 22 is formed on the rare earth-containing film 4b (see FIG. 51).
- the reaction preventing mask layer 22 and the rare earth-containing film 4b in the pMIS formation region 1B are removed and the reaction preventing mask layer 22 and the rare earth-containing film 4b in the nMIS formation region 1A are left (see FIG. 52). .
- step S6a the Al-containing film 21 is formed instead of the rare earth-containing film 4b, that is, the Al-containing film on the reaction preventing mask layer 22 in the nMIS formation region 1A and the Hf-containing film 4a in the pMIS formation region 1B. 21 is formed (see FIG. 53).
- the interface layer 3, the Hf-containing film 4a, the rare earth-containing film 4b, the reaction preventing mask layer 22, and the Al-containing film 21 are sequentially stacked from the bottom on the p-type well PW.
- the interface layer 3, the Hf-containing film 4a, and the Al-containing film 21 are sequentially stacked from the bottom on the n-type well NW.
- the Hf-containing film 4a and the rare earth-containing film 4b in the nMIS formation region 1A are reacted (mixed, mixed, and interdiffusion) in the heat treatment of step S34 to form an Hf-containing film 4d that is a reaction layer of both, and pMIS
- the Hf-containing film 4a in the formation region 1B and the Al-containing film 21 are reacted (mixed, mixed, and mutually diffused) to form a Hf-containing film 4e that is a reaction layer of both (see FIG. 54).
- the reaction preventing mask layer 22 is interposed between the Al-containing film 21 in the nMIS formation region 1A and the rare earth-containing film 4b (and the Hf-containing film 4a), and the Al-containing film 21 in the nMIS formation region 1A is a rare earth. It functions to prevent reaction with the containing film 4b and the Hf-containing film 4a.
- step S35 the unreacted Al-containing film 21 on the reaction preventing mask layer 22 is removed, and the reaction preventing mask layer 22 is further removed (see FIG. 55).
- the present invention is effective when applied to a semiconductor device and its manufacturing technology.
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Abstract
Description
本実施の形態の半導体装置を図面を参照して説明する。
上記実施の形態1では、nチャネル型のMISFETを有する半導体装置に本発明を適用した場合について説明した。本実施の形態では、CMISFET(Complementary Metal Insulator Semiconductor Field Effect Transistor)を有する半導体装置に本発明を適用した場合について説明する。
1A nMIS形成領域
1B pMIS形成領域
2 素子分離領域
3 界面層
4a,4c Hf含有膜
4b 希土類含有膜
5,6 Hf含有絶縁膜(高誘電率ゲート絶縁膜)
7 金属膜
8 シリコン膜
10 金属シリサイド層
11 絶縁膜
12 ストッパ絶縁膜
13 絶縁膜
14 配線溝
21 Al含有膜
22 反応防止用マスク層
CNT コンタクトホール
EX1 n-型半導体領域
EX2 p-型半導体領域
GE1,GE2 ゲート電極(メタルゲート電極)
M1 配線
MIN,MINa 極小値
NW n型ウエル
P1,P2,P3,P4,P5,P6 ピーク
PG プラグ
PR1,PR1a フォトレジストパターン
PW p型ウエル
Qn nチャネル型MISFET
Qp pチャネル型MISFET
SD1 n+型半導体領域
SD2 p+型半導体領域
SW サイドウォール
Claims (24)
- nチャネル型の第1MISFETを備える半導体装置であって、
半導体基板と、
前記半導体基板上に形成された、前記第1MISFETの第1ゲート絶縁膜と、
前記第1ゲート絶縁膜上に形成された、前記第1MISFETの第1メタルゲート電極と、
を有し、
前記第1ゲート絶縁膜は、ハフニウムと希土類元素と酸素とを主成分として含有し、
前記第1ゲート絶縁膜の厚み方向における希土類元素の濃度分布は、前記第1ゲート絶縁膜の下面近傍および上面近傍では、前記第1ゲート絶縁膜の中央領域よりも希土類元素の濃度が低いことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1ゲート絶縁膜の厚み方向における希土類元素の濃度分布は、前記第1ゲート絶縁膜の厚み方向の前記中央領域にピークを有していることを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記第1ゲート絶縁膜の厚み方向におけるハフニウムの濃度分布は、ダブルピークを有し、
前記第1ゲート絶縁膜の厚み方向における希土類元素の濃度分布は、前記第1ゲート絶縁膜の厚み方向におけるハフニウムの濃度分布のダブルピークの間にピークを有していることを特徴とする半導体装置。 - 請求項3記載の半導体装置において、
前記半導体基板に形成された、前記第1MISFETのソース・ドレイン用の半導体領域を更に有することを特徴とする半導体装置。 - 請求項4記載の半導体装置において、
前記第1ゲート絶縁膜が含有する希土類元素はランタンであることを特徴とする半導体装置。 - 請求項5記載の半導体装置において、
前記第1ゲート絶縁膜と前記半導体基板との界面に形成された、酸化シリコンまたは酸窒化シリコンからなる界面層を更に有することを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
pチャネル型の第2MISFETを更に備え、
前記半導体基板上に形成された、前記第2MISFETの第2ゲート絶縁膜と、
前記第2ゲート絶縁膜上に形成された、前記第2MISFETの第2メタルゲート電極と、
を更に有し、
前記第2ゲート絶縁膜は、ハフニウムとアルミニウムと酸素とを主成分として含有し、
前記第2ゲート絶縁膜の厚み方向におけるアルミニウムの濃度分布は、前記第2ゲート絶縁膜の下面近傍および上面近傍では、前記第2ゲート絶縁膜の中央領域よりもアルミニウムの濃度が低いことを特徴とする半導体装置。 - 請求項7記載の半導体装置において、
前記第2ゲート絶縁膜の厚み方向におけるハフニウムの濃度分布は、ダブルピークを有し、
前記第2ゲート絶縁膜の厚み方向における希土類元素の濃度分布は、前記第2ゲート絶縁膜の厚み方向におけるハフニウムの濃度分布のダブルピークの間にピークを有していることを特徴とする半導体装置。 - ハフニウムと希土類元素と酸素とを主成分として含有するゲート絶縁膜およびメタルゲート電極を有するnチャネル型MISFETを備えた半導体装置の製造方法であって、
(a)半導体基板を用意する工程、
(b)前記半導体基板上に、前記ゲート絶縁膜形成用でかつハフニウムおよび酸素を主成分として含有する第1Hf含有膜を形成する工程、
(c)前記第1Hf含有膜上に、前記ゲート絶縁膜形成用でかつ希土類元素を主成分として含有する希土類含有膜を形成する工程、
(d)前記希土類含有膜上に、前記ゲート絶縁膜形成用でかつハフニウムおよび酸素を主成分として含有する第2Hf含有膜を形成する工程、
(e)前記第2Hf含有膜上に、金属膜を形成する工程、
(f)前記(e)工程後、前記金属膜をパターニングして前記メタルゲート電極を形成する工程、
を有することを特徴とする半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記(e)工程後で、前記(f)工程前に、
(e1)前記金属膜上にシリコン膜を形成する工程、
を更に有し、
前記(f)工程では、前記シリコン膜および前記金属膜をパターニングして前記メタルゲート電極を形成することを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記(f)工程後に、
(g)前記半導体基板に前記MISFETのソース・ドレイン領域形成用のイオン注入を行なう工程、
(h)前記(g)工程後に、前記(g)工程の前記イオン注入で導入された不純物を活性化させるための第1熱処理を行う工程、
を更に有することを特徴とする半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
前記(c)工程で形成される前記希土類含有膜は酸化希土類膜であることを特徴とする半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記(c)工程で形成される前記希土類含有膜は酸化ランタン膜であることを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(b)工程で形成される前記第1Hf含有膜は、HfO膜、HfON膜、HfSiO膜またはHfSiON膜であり、
前記(d)工程で形成される前記第2Hf含有膜は、HfO膜、HfON膜、HfSiO膜またはHfSiON膜であることを特徴とする半導体装置の製造方法。 - 請求項14記載の半導体装置の製造方法において、
前記(b)工程前に、
(b1)前記半導体基板上に、酸化シリコンまたは酸窒化シリコンからなる第3絶縁膜を形成する工程、
を更に有し、
前記(b)工程では、前記第3絶縁膜上に前記第1Hf含有膜を形成することを特徴とする半導体装置の製造方法。 - 請求項15記載の半導体装置の製造方法において、
前記(h)工程の前記第1熱処理により、前記第1Hf含有膜、前記希土類含有膜および前記第2Hf含有膜が反応して、前記ゲート絶縁膜が形成されることを特徴とする半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法において、
前記(b)工程で形成される前記第1Hf含有膜よりも、前記(d)工程で形成される前記第2Hf含有膜が厚いことを特徴とする半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記(c)工程後で、前記(d)工程前に、
(c1)第2熱処理を行って、前記第1Hf含有膜を前記希土類含有膜と反応させる工程、
を更に有し、
前記(d)工程では、前記第1Hf含有膜と前記希土類含有膜との反応層上に前記第2Hf含有膜が形成され、
前記(h)工程の前記第1熱処理により、前記反応層と前記第2Hf含有膜が反応して前記ゲート絶縁膜が形成されることを特徴とする半導体装置の製造方法。 - ハフニウムと希土類元素と酸素とを主成分として含有する第1ゲート絶縁膜および第1メタルゲート電極を有するnチャネル型MISFETを半導体基板の第1領域に有し、ハフニウムとアルミニウムと酸素とを主成分として含有する第2ゲート絶縁膜および第2メタルゲート電極を有するpチャネル型MISFETを半導体基板の第2領域に有する半導体装置の製造方法であって、
(a)前記半導体基板を用意する工程、
(b)前記半導体基板上の前記第1領域および前記第2領域に、前記第1および第2ゲート絶縁膜形成用でかつハフニウムおよび酸素を主成分として含有する第1Hf含有膜を形成する工程、
(c)前記第1領域および前記第2領域に形成された前記第1Hf含有膜上に、前記第2ゲート絶縁膜形成用でかつアルミニウムを主成分として含有するAl含有膜を形成する工程、
(d)前記第1領域および前記第2領域に形成された前記Al含有膜上にマスク層を形成する工程、
(e)前記(d)工程後、前記第1領域の前記マスク層および前記Al含有膜を除去し、前記第2領域の前記マスク層および前記Al含有膜を残す工程、
(f)前記(e)工程後、前記第1ゲート絶縁膜形成用でかつ希土類元素を主成分として含有する希土類含有膜を、前記第1領域の前記第1Hf含有膜上および前記第2領域の前記マスク層上に形成する工程、
(g)前記(f)工程後、前記第2領域の前記マスク層上の前記希土類含有膜と前記マスク層とを除去する工程、
(h)前記(g)工程後、前記第1領域の前記希土類含有膜および前記第2領域の前記Al含有膜上に、前記第1および第2ゲート絶縁膜形成用でかつハフニウムおよび酸素を主成分として含有する第2Hf含有膜を形成する工程、
(i)前記(h)工程後、前記第1領域および前記第2領域の前記第2Hf含有膜上に、金属膜を形成する工程、
(j)前記(i)工程後、前記金属膜をパターニングして、前記第1領域に前記第1メタルゲート電極を、前記第2領域に前記第2メタルゲート電極を形成する工程、
を有することを特徴とする半導体装置の製造方法。 - 請求項19記載の半導体装置の製造方法において、
前記(f)工程後、前記(g)工程前に、
(f1)熱処理を行って、前記第1領域の前記第1Hf含有膜と前記希土類含有膜とを反応させ、前記第2領域の前記第1Hf含有膜と前記Al含有膜とを反応させる工程、
を更に有し、
前記(h)工程では、前記第1Hf含有膜は、前記第1領域においては前記第1Hf含有膜と前記希土類含有膜との反応層上に形成され、前記第2領域においては前記第1Hf含有膜と前記Al含有膜との反応層上に形成されることを特徴とする半導体装置の製造方法。 - 請求項20記載の半導体装置の製造方法において、
前記(j)工程の後に、
(k)前記第1領域の前記半導体基板に前記nチャネル型MISFETのソース・ドレイン領域形成用のイオン注入を行ない、前記第2領域の前記半導体基板に前記pチャネル型MISFETのソース・ドレイン領域形成用のイオン注入を行なう工程、
(l)前記(k)工程後に、前記(k)工程の前記イオン注入で導入された不純物を活性化させるための熱処理を行う工程、
を更に有することを特徴とする半導体装置の製造方法。 - 請求項21記載の半導体装置の製造方法において、
前記(b)工程で形成される前記第1Hf含有膜は、HfO膜、HfON膜、HfSiO膜またはHfSiON膜であり、
前記(c)工程で形成された前記Al含有膜は、酸化アルミニウム膜、酸窒化アルミニウム膜またはアルミニウム膜であり、
前記(f)工程で形成された前記希土類含有膜は、希土類酸化物膜であり、
前記(h)工程で形成される前記第2Hf含有膜は、HfO膜、HfON膜、HfSiO膜またはHfSiON膜であることを特徴とする半導体装置の製造方法。 - 請求項22記載の半導体装置の製造方法において、
前記(f)工程で形成された前記希土類含有膜は、酸化ランタン膜であることを特徴とする半導体装置の製造方法。 - 請求項23記載の半導体装置の製造方法において、
前記(c)工程で形成された前記マスク層は、窒化金属膜または炭化金属膜であることを特徴とする半導体装置の製造方法。
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PCT/JP2009/067421 WO2011042955A1 (ja) | 2009-10-06 | 2009-10-06 | 半導体装置およびその製造方法 |
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KR20200049505A (ko) * | 2018-10-26 | 2020-05-08 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 계면 층을 갖는 게이트 구조물 |
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US9190409B2 (en) | 2013-02-25 | 2015-11-17 | Renesas Electronics Corporation | Replacement metal gate transistor with controlled threshold voltage |
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