JP2005536053A - 金属酸化物を用いてデュアルゲートオキサイドデバイスを形成するための方法および形成されるデバイス - Google Patents

金属酸化物を用いてデュアルゲートオキサイドデバイスを形成するための方法および形成されるデバイス Download PDF

Info

Publication number
JP2005536053A
JP2005536053A JP2004529077A JP2004529077A JP2005536053A JP 2005536053 A JP2005536053 A JP 2005536053A JP 2004529077 A JP2004529077 A JP 2004529077A JP 2004529077 A JP2004529077 A JP 2004529077A JP 2005536053 A JP2005536053 A JP 2005536053A
Authority
JP
Japan
Prior art keywords
gate
metal oxide
dielectric
dielectric layer
gate dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004529077A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005536053A5 (zh
Inventor
シー. ギルマー、デイビッド
シー. ホッブス、クリストファー
ツェン、シン−ホワン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2005536053A publication Critical patent/JP2005536053A/ja
Publication of JP2005536053A5 publication Critical patent/JP2005536053A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31616Deposition of Al2O3
    • H01L21/3162Deposition of Al2O3 on a silicon body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/55Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/981Utilizing varying dielectric thickness

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2004529077A 2002-08-15 2003-06-16 金属酸化物を用いてデュアルゲートオキサイドデバイスを形成するための方法および形成されるデバイス Pending JP2005536053A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/219,522 US6787421B2 (en) 2002-08-15 2002-08-15 Method for forming a dual gate oxide device using a metal oxide and resulting device
PCT/US2003/018939 WO2004017403A1 (en) 2002-08-15 2003-06-16 Method for forming a dual gate oxide device using a metal oxide and resulting device

Publications (2)

Publication Number Publication Date
JP2005536053A true JP2005536053A (ja) 2005-11-24
JP2005536053A5 JP2005536053A5 (zh) 2006-07-20

Family

ID=31714754

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004529077A Pending JP2005536053A (ja) 2002-08-15 2003-06-16 金属酸化物を用いてデュアルゲートオキサイドデバイスを形成するための方法および形成されるデバイス

Country Status (7)

Country Link
US (1) US6787421B2 (zh)
JP (1) JP2005536053A (zh)
KR (1) KR20050054920A (zh)
CN (1) CN1675759A (zh)
AU (1) AU2003285819A1 (zh)
TW (1) TW200414529A (zh)
WO (1) WO2004017403A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010150332A1 (ja) * 2009-06-24 2010-12-29 パナソニック株式会社 半導体装置及びその製造方法
CN102332398A (zh) * 2011-10-28 2012-01-25 上海华力微电子有限公司 一种双高k栅介质/金属栅结构的制作方法
WO2012035684A1 (ja) * 2010-09-14 2012-03-22 パナソニック株式会社 半導体装置及びその製造方法

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7041562B2 (en) * 2003-10-29 2006-05-09 Freescale Semiconductor, Inc. Method for forming multiple gate oxide thickness utilizing ashing and cleaning
US6979623B2 (en) * 2003-12-17 2005-12-27 Texas Instruments Incorporated Method for fabricating split gate transistor device having high-k dielectrics
KR20050070837A (ko) * 2003-12-31 2005-07-07 동부아남반도체 주식회사 금속 옥사이드 반도체 소자의 플라즈마 손상방지를 위한식각방법
US7115947B2 (en) * 2004-03-18 2006-10-03 International Business Machines Corporation Multiple dielectric finfet structure and method
US20050250258A1 (en) * 2004-05-04 2005-11-10 Metz Matthew V Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US7227205B2 (en) * 2004-06-24 2007-06-05 International Business Machines Corporation Strained-silicon CMOS device and method
TWI463526B (zh) * 2004-06-24 2014-12-01 Ibm 改良具應力矽之cmos元件的方法及以該方法製備而成的元件
US7144784B2 (en) * 2004-07-29 2006-12-05 Freescale Semiconductor, Inc. Method of forming a semiconductor device and structure thereof
US6946349B1 (en) * 2004-08-09 2005-09-20 Chartered Semiconductor Manufacturing Ltd. Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses
DE102004040943B4 (de) * 2004-08-24 2008-07-31 Qimonda Ag Verfahren zur selektiven Abscheidung einer Schicht mittels eines ALD-Verfahrens
US7494939B2 (en) 2004-08-31 2009-02-24 Micron Technology, Inc. Methods for forming a lanthanum-metal oxide dielectric layer
US7588988B2 (en) 2004-08-31 2009-09-15 Micron Technology, Inc. Method of forming apparatus having oxide films formed using atomic layer deposition
US7071038B2 (en) * 2004-09-22 2006-07-04 Freescale Semiconductor, Inc Method of forming a semiconductor device having a dielectric layer with high dielectric constant
US20060088962A1 (en) * 2004-10-22 2006-04-27 Herman Gregory S Method of forming a solution processed transistor having a multilayer dielectric
US7235501B2 (en) 2004-12-13 2007-06-26 Micron Technology, Inc. Lanthanum hafnium oxide dielectrics
DE102004063532A1 (de) * 2004-12-30 2006-07-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung von Gateisolationsschichten mit unterschiedlichen Eigenschaften
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7214590B2 (en) * 2005-04-05 2007-05-08 Freescale Semiconductor, Inc. Method of forming an electronic device
US8405165B2 (en) * 2005-06-07 2013-03-26 International Business Machines Corporation Field effect transistor having multiple conduction states
US7544596B2 (en) * 2005-08-30 2009-06-09 Micron Technology, Inc. Atomic layer deposition of GdScO3 films as gate dielectrics
US7592251B2 (en) 2005-12-08 2009-09-22 Micron Technology, Inc. Hafnium tantalum titanium oxide films
US7972974B2 (en) 2006-01-10 2011-07-05 Micron Technology, Inc. Gallium lanthanide oxide films
KR100762239B1 (ko) * 2006-05-03 2007-10-01 주식회사 하이닉스반도체 반도체 소자의 pmos 트랜지스터, 이를 포함하는 반도체소자와 그의 제조 방법
US7759747B2 (en) 2006-08-31 2010-07-20 Micron Technology, Inc. Tantalum aluminum oxynitride high-κ dielectric
US7518145B2 (en) * 2007-01-25 2009-04-14 International Business Machines Corporation Integrated multiple gate dielectric composition and thickness semiconductor chip and method of manufacturing the same
US7768080B2 (en) * 2007-07-30 2010-08-03 Hewlett-Packard Development Company, L.P. Multilayer dielectric
US7709331B2 (en) * 2007-09-07 2010-05-04 Freescale Semiconductor, Inc. Dual gate oxide device integration
US8460996B2 (en) * 2007-10-31 2013-06-11 Freescale Semiconductor, Inc. Semiconductor devices with different dielectric thicknesses
US8017469B2 (en) 2009-01-21 2011-09-13 Freescale Semiconductor, Inc. Dual high-k oxides with sige channel
US7944004B2 (en) * 2009-03-26 2011-05-17 Kabushiki Kaisha Toshiba Multiple thickness and/or composition high-K gate dielectrics and methods of making thereof
US7943460B2 (en) * 2009-04-20 2011-05-17 International Business Machines Corporation High-K metal gate CMOS
JP5268792B2 (ja) * 2009-06-12 2013-08-21 パナソニック株式会社 半導体装置
US8377807B2 (en) * 2010-09-30 2013-02-19 Suvolta, Inc. Method for minimizing defects in a semiconductor substrate due to ion implantation
US11931740B2 (en) 2012-02-13 2024-03-19 Neumodx Molecular, Inc. System and method for processing and detecting nucleic acids
CN114134029A (zh) 2012-02-13 2022-03-04 纽莫德克斯莫勒库拉尔公司 用于处理和检测核酸的微流体盒
US11485968B2 (en) 2012-02-13 2022-11-01 Neumodx Molecular, Inc. Microfluidic cartridge for processing and detecting nucleic acids
US9637775B2 (en) 2012-02-13 2017-05-02 Neumodx Molecular, Inc. System and method for processing biological samples
KR101850409B1 (ko) 2012-03-15 2018-06-01 삼성전자주식회사 듀얼 게이트 절연막을 갖는 반도체 장치의 제조 방법
CN103824771A (zh) * 2012-11-16 2014-05-28 中芯国际集成电路制造(上海)有限公司 栅氧化层的形成方法
US9059022B2 (en) 2012-12-28 2015-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods of forming the same
US9048335B2 (en) * 2013-03-01 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating multiple gate stack compositions
US9373501B2 (en) * 2013-04-16 2016-06-21 International Business Machines Corporation Hydroxyl group termination for nucleation of a dielectric metallic oxide
US8987793B2 (en) * 2013-04-23 2015-03-24 Broadcom Corporation Fin-based field-effect transistor with split-gate structure
CN104183470B (zh) * 2013-05-21 2017-09-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
TW201528486A (zh) * 2014-01-15 2015-07-16 Silicon Optronics Inc 影像感測裝置及其製造方法
CN104952734B (zh) * 2015-07-16 2020-01-24 矽力杰半导体技术(杭州)有限公司 半导体结构及其制造方法
CN108122750B (zh) * 2016-11-29 2020-06-09 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
US10002939B1 (en) 2017-02-16 2018-06-19 International Business Machines Corporation Nanosheet transistors having thin and thick gate dielectric material
CN108630605B (zh) 2017-03-22 2020-12-18 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6320238B1 (en) 1996-12-23 2001-11-20 Agere Systems Guardian Corp. Gate structure for integrated circuit fabrication
US6358819B1 (en) 1998-12-15 2002-03-19 Lsi Logic Corporation Dual gate oxide process for deep submicron ICS
US6297539B1 (en) 1999-07-19 2001-10-02 Sharp Laboratories Of America, Inc. Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same
JP2001060630A (ja) * 1999-08-23 2001-03-06 Nec Corp 半導体装置の製造方法
US6448127B1 (en) * 2000-01-14 2002-09-10 Advanced Micro Devices, Inc. Process for formation of ultra-thin base oxide in high k/oxide stack gate dielectrics of mosfets
JP2001284463A (ja) 2000-03-30 2001-10-12 Nec Corp 半導体装置およびその製造方法
JP2001298095A (ja) * 2000-04-13 2001-10-26 Nec Corp Mos型半導体装置の製造方法
TW466606B (en) * 2000-04-20 2001-12-01 United Microelectronics Corp Manufacturing method for dual metal gate electrode
JP2002009168A (ja) * 2000-06-19 2002-01-11 Nec Corp 半導体装置及びその製造方法
JP2002009169A (ja) * 2000-06-20 2002-01-11 Nec Corp 半導体装置とその製造方法
US6268251B1 (en) 2000-07-12 2001-07-31 Chartered Semiconductor Manufacturing Inc. Method of forming MOS/CMOS devices with dual or triple gate oxide
JP2002134739A (ja) * 2000-10-19 2002-05-10 Mitsubishi Electric Corp 半導体装置及びその製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010150332A1 (ja) * 2009-06-24 2010-12-29 パナソニック株式会社 半導体装置及びその製造方法
JP2011009313A (ja) * 2009-06-24 2011-01-13 Panasonic Corp 半導体装置及びその製造方法
WO2012035684A1 (ja) * 2010-09-14 2012-03-22 パナソニック株式会社 半導体装置及びその製造方法
JP2012064648A (ja) * 2010-09-14 2012-03-29 Panasonic Corp 半導体装置及びその製造方法
CN102332398A (zh) * 2011-10-28 2012-01-25 上海华力微电子有限公司 一种双高k栅介质/金属栅结构的制作方法

Also Published As

Publication number Publication date
TW200414529A (en) 2004-08-01
US20040032001A1 (en) 2004-02-19
AU2003285819A1 (en) 2004-03-03
US6787421B2 (en) 2004-09-07
CN1675759A (zh) 2005-09-28
WO2004017403A1 (en) 2004-02-26
KR20050054920A (ko) 2005-06-10

Similar Documents

Publication Publication Date Title
US6787421B2 (en) Method for forming a dual gate oxide device using a metal oxide and resulting device
TWI382449B (zh) 半導體製程及包含具有單金屬閘極之雙金屬氧化物閘極介電質之積體電路
US7323420B2 (en) Method for manufacturing multi-thickness gate dielectric layer of semiconductor device
JP3730962B2 (ja) 半導体装置の製造方法
TWI292589B (en) Structure and fabrication method of multiple gate dielectric layers
US6821854B2 (en) Method of manufacturing a semiconductor integrated circuit device
JP2004253767A (ja) デュアルゲート構造およびデュアルゲート構造を有する集積回路の製造方法
JP2008508718A (ja) 半導体デバイスの形成方法およびその構造
EP1388892A2 (en) A triple gate oxide process with high-gate dielectric
US6586293B1 (en) Semiconductor device and method of manufacturing the same
US5970345A (en) Method of forming an integrated circuit having both low voltage and high voltage MOS transistors
US6531368B1 (en) Method of fabricating a semiconductor device having a metal oxide high-k gate insulator by localized laser irradiation and a device thereby formed
US20070218598A1 (en) Method for forming ultra thin low leakage multi gate devices
US6495422B1 (en) Methods of forming high-k gate dielectrics and I/O gate oxides for advanced logic application
JP3539491B2 (ja) 半導体装置の製造方法
JP3544622B2 (ja) 二重酸化膜の形成方法
US7393787B2 (en) Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment
US7670913B2 (en) Method for forming ultra-thin low leakage multiple gate devices using a masking layer over the semiconductor substrate
US6579766B1 (en) Dual gate oxide process without critical resist and without N2 implant
JP4588483B2 (ja) 半導体装置
JP3770250B2 (ja) 半導体装置の製造方法
JP2004079606A (ja) 高誘電率膜を有する半導体装置及びその製造方法
JP2005064052A (ja) 半導体装置の製造方法
JP5177980B2 (ja) 半導体装置およびその製造方法
JP2000332125A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060531

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060531

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090318

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090401

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090908