CN1993824A - 对互补金属氧化物半导体集成电路的nmos和pmos晶体管使用不同栅电介质 - Google Patents
对互补金属氧化物半导体集成电路的nmos和pmos晶体管使用不同栅电介质 Download PDFInfo
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- 230000000295 complement effect Effects 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 6
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 21
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- 238000005516 engineering process Methods 0.000 claims description 11
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- 230000000873 masking effect Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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Abstract
可以利用具有不同栅电介质的NMOS和PMOS晶体管形成互补金属氧化物半导体集成电路。例如,可通过减法工艺形成不同的栅电介质。作为几个实例,这些栅电介质可以在材料、厚度、或者形成技术方面是不同的。
Description
技术领域
本发明总体上涉及半导体技术、半导体处理和互补金属氧化物半导体集成电路的形成。
背景技术
互补金属氧化物半导体(CMOS)集成电路包括NMOS晶体管和PMOS晶体管。通常,这些晶体管可以通过形成栅电介质和之后在该电介质的顶部上形成NMOS和PMOS栅极结构制成。这些栅电极结构可由多晶硅、硅化物或者金属制成。
具有由二氧化硅制成的非常薄的栅电介质的MOS场效应晶体管可能会经历不可接受的栅极漏电流。代替二氧化硅由特定高k介电材料形成栅电介质能够降低栅极泄漏。然而,由于这种电介质不能与多晶硅相兼容,因此希望在包括高k栅电介质的器件中使用金属栅电极。
当制造包括金属栅电极的CMOS器件时,可将取代栅极工艺用于利用不同金属形成栅电极。在该工艺中,去除被一对隔离物托架的第一多晶硅层以在这些隔离物之间产生沟槽。用第一金属填充该沟槽。然后去除第二多晶硅层,并用与第一金属不同的第二金属取代第二多晶硅层。由于该工艺需要多次蚀刻、沉积和抛光步骤,因此高产量的半导体器件制造商可能不愿使用该工艺。
更确切地,应用取代栅极工艺以在高k栅介电层上形成金属栅电极,可使用减法方法(subtractive approach)。在这种工艺中,通过在介电层上沉积金属层、掩蔽该金属层并然后去除该金属层的未被覆盖的部分以及介电层的下面的部分,在高k栅介电层上形成金属栅电极。不幸的是,获得的高k栅介电层的暴露的侧壁使得该层易受横向氧化的影响,其不利地影响了其物理和电特性。
由此,需要互补金属氧化物半导体制造技术。
附图说明
图1是根据本发明的一个实施例在早期制造阶段本发明的另一实施例的局部、放大、截面图;
图2是根据本发明的一个实施例在随后制造阶段图1中所示实施例的局部、放大、截面图;
图3是根据本发明的一个实施例在随后制造阶段图2中所示实施例的局部、放大、截面图;
图4是根据本发明的一个实施例在随后制造阶段图3中所示实施例的局部、放大、截面图;
图5是根据本发明的一个实施例在随后制造阶段图4中所示实施例的局部、放大、截面图;
图6是根据本发明的一个实施例在随后制造阶段图5中所示实施例的局部、放大、截面图;
图7是根据本发明的一个实施例在随后制造阶段图6中所示实施例的局部、放大、截面图;
图8是根据本发明的一个实施例在随后制造阶段图7中所示实施例的局部、放大、截面图;
图9是在随后的处理之后根据本发明的一个实施例在随后制造阶段图8中所示实施例的局部、放大、截面图;和
图10是根据本发明的一个实施例在随后制造阶段图9中所示实施例的局部、放大、截面图。
具体实施方式
可利用具有不同栅电介质的NMOS和PMOS晶体管制造互补金属氧化物半导体(CMOS)集成电路。该电介质在所使用的材料、其厚度或者用于形成栅电介质的技术方面可以是不同的,以提及几个实例。结果,栅电介质可适合于特定类型的晶体管,其可以是NMOS或者PMOS晶体管,这视情况而定。
参考图1,最初,可由掩蔽材料34例如抗蚀剂覆盖衬底32。然后,如图2中所示,可暴露掩蔽材料34,以在右边产生暴露区34a和在左边产生未暴露区34。在多种情况下,区域34和34a在半导体结构32上方可以间隔很大,且可以对应于最终将形成NMOS与PMOS晶体管的有源区。
参考图3,然后可以图案化图2中示出的暴露的晶片,以去除暴露的材料34a。替换地,可选择性地去除未暴露的材料。然后,如图3中所示,可以形成开口36。
在图4中,然后可以在获得的结构上方沉积或者生长栅电介质38。在衬底32的顶部上且还在掩蔽层34的顶部上形成栅电介质38。
当去除掩蔽层34时,如图5中所示,还剥离了栅电介质38的覆盖部分。由此,在本发明的一个实施例中,仅在于衬底32上直接沉积栅电介质38的位置处留下该栅电介质38。
参考图6,可以用另一掩蔽层40覆盖该晶片,在本发明的一个实施例中,其也可以是抗蚀剂。然后,如图7中所示,掩蔽层40可以被有差别地暴露。在所示出的实施例中,层40a已经通过曝光而改性,从而,如图8中所示,在左边可以选择性地将其去除,以形成间隙42。
然后,如图9中所示,在衬底32上方沉积或生长栅电介质44。层44在左边积累在衬底32上并且在右边积累在掩蔽层40上方。
最终,在图10中,可剥离在掩蔽层40上方的电介质44,仅留下在衬底32上方的介电层44。结果,在不同区域中形成不同的介电材料44和38,以用作NMOS和PMOS晶体管或者用于不同应用的相同类型的晶体管的栅电介质。之后,可以使用适当的制造技术构建这些PMOS和NMOS晶体管。例如,栅电极可由多晶硅、硅化物、金属或者任何其它合适的材料形成。
在一个实施例中,可选择电介质38,以具有优化将在区域36中形成的NMOS或PMOS晶体管的性能的特性。例如,栅电介质38的材料、厚度或者形成技术可适合于其特定应用。
例如,NMOS晶体管可使用较大导带偏移材料,例如二氧化硅,且PMOS晶体管可使用具有较高介电常数的材料,例如二氧化铪,其还正好具有良好的空穴带偏移。在一个实施例中,较高介电常数可以大于十。作为另一实例,在一些情况下,可将比PMOS晶体管厚的材料用于NMOS。例如,二氧化铪泄漏比空穴多的电子,因此可将较厚的二氧化铪层用在NMOS晶体管上,并且可将较薄的二氧化铪层用在PMOS晶体管上。例如,在一个实施例中,对于NMOS晶体管,二氧化铪栅电介质可以为30埃,且对于PMOS晶体管的栅电介质为15埃。
作为再一实例,对于两种栅电介质,沉积技术可以是不同的。例如,可以使用扩散技术沉积用于NMOS晶体管的材料,例如二氧化硅,同时可使用原子层沉积、溅射、或金属有机化学汽相沉积(MOCVD)来沉积高介电常数材料,例如二氧化铪。
在一些实施例中,单栅极介电材料可能没有为NMOS和PMOS结构提供最高的性能。这可能例如是由于导带或价带的差的带偏移、与栅电极材料的不兼容性、与栅电极处理或者厚度要求的不兼容性导致的。在一些实施例中,通过为每个结构选择较好的候选电介质膜并且沉积具有最佳厚度的最佳膜,可形成较高性能的互补金属氧化物半导体器件。在一些实施例中,通过对于每个电极堆叠使用最佳厚度的较好栅极介电材料,可形成较高性能的结构,其可以显示出较高的迁移率、较高的饱和电流或者较好的阈值电压。
虽然已经关于有限数目的实施例描述了本发明,但是本领域技术人员将理解由其得到的多种修改和变形。所附权利要求旨在覆盖落入本发明的真实精神和范围内的所有这些修改和变形。
Claims (20)
1.一种方法,包括:
在衬底上限定NMOS和PMOS晶体管区域;
在NMOS或PMOS区域中的一个上方形成掩模;
在衬底上和掩模上方形成第一栅电介质,以形成第一导电类型的晶体管;
掩蔽所述第一栅电介质;以及
形成第二栅电介质,以形成第二导电类型的晶体管。
2.如权利要求1的方法,包括形成不同厚度的所述第一和第二栅电介质。
3.如权利要求1的方法,包括形成不同材料的所述第一和第二栅电介质。
4.如权利要求1的方法,包括形成通过不同技术沉积的第一和第二栅电介质。
5.如权利要求1的方法,包括剥离在掩模上方形成的电介质。
6.如权利要求1的方法,包括形成具有金属栅极的NMOS和PMOS晶体管。
7.如权利要求1的方法,包括对于NMOS栅电介质使用具有较大导带偏移的材料。
8.如权利要求1的方法,包括对于PMOS晶体管使用具有较高介电常数的材料作为栅电介质。
9.如权利要求1的方法,包括对于所述NMOS晶体管使用比对于所述PMOS晶体管更厚的电介质。
10.如权利要求9的方法,包括使用具有大于10的介电常数的第一和第二电介质。
11.一种半导体结构,包括:
衬底;
在所述衬底上的NMOS和PMOS晶体管区域;
仅在所述区域中的一个上方的掩模;和
在两个所述区域上方的栅电介质。
12.如权利要求11的结构,其中所述栅电介质具有大于10的介电常数。
13.如权利要求11的结构,其中所述掩模是抗蚀剂。
14.如权利要求11的结构,其中所述电介质是金属氧化物。
15.一种方法,包括:
通过掩蔽PMOS区域并在PMOS和NMOS区域上形成第一栅电介质,形成在NMOS区域中的互补金属氧化物半导体集成电路的NMOS晶体管和在PMOS区域中的PMOS晶体管;以及
形成具有与所述第一栅电介质不同的第二栅电介质的所述互补金属氧化物半导体集成电路的PMOS晶体管。
16.如权利要求15的方法,包括形成具有不同电介质厚度的所述电介质。
17.如权利要求15的方法,包括形成不同材料的所述电介质。
18.如权利要求15的方法,包括使用不同的沉积技术沉积所述电介质。
19.如权利要求15的方法,包括对于第一栅电介质使用具有较大导带偏移的材料。
20.如权利要求15的方法,包括使用具有较高介电常数的材料作为所述第二栅电介质。
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US10/900,585 US7087476B2 (en) | 2004-07-28 | 2004-07-28 | Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit |
US10/900,585 | 2004-07-28 |
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JP (1) | JP2008507141A (zh) |
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DE (1) | DE112005001787T5 (zh) |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114388349A (zh) * | 2022-03-22 | 2022-04-22 | 广州粤芯半导体技术有限公司 | 半导体器件的制备方法 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8399934B2 (en) * | 2004-12-20 | 2013-03-19 | Infineon Technologies Ag | Transistor device |
KR100702307B1 (ko) * | 2004-07-29 | 2007-03-30 | 주식회사 하이닉스반도체 | 반도체 소자의 디램 및 그 제조 방법 |
EP1914800A1 (en) * | 2006-10-20 | 2008-04-23 | Interuniversitair Microelektronica Centrum | Method of manufacturing a semiconductor device with multiple dielectrics |
US7635634B2 (en) * | 2007-04-16 | 2009-12-22 | Infineon Technologies Ag | Dielectric apparatus and associated methods |
TWI492367B (zh) | 2007-12-03 | 2015-07-11 | Renesas Electronics Corp | Cmos半導體裝置之製造方法 |
US20090191468A1 (en) * | 2008-01-29 | 2009-07-30 | International Business Machines Corporation | Contact Level Mask Layouts By Introducing Anisotropic Sub-Resolution Assist Features |
US20090250760A1 (en) * | 2008-04-02 | 2009-10-08 | International Business Machines Corporation | Methods of forming high-k/metal gates for nfets and pfets |
JP5314964B2 (ja) * | 2008-08-13 | 2013-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7975246B2 (en) * | 2008-08-14 | 2011-07-05 | International Business Machines Corporation | MEEF reduction by elongation of square shapes |
JP2010129926A (ja) * | 2008-11-28 | 2010-06-10 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
KR101634748B1 (ko) | 2009-12-08 | 2016-07-11 | 삼성전자주식회사 | 트랜지스터의 제조방법 및 그를 이용한 집적 회로의 형성방법 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US667024A (en) * | 1899-12-26 | 1901-01-29 | Karl W Leaf | Garment placket-closure. |
US4411058A (en) * | 1981-08-31 | 1983-10-25 | Hughes Aircraft Company | Process for fabricating CMOS devices with self-aligned channel stops |
JPH01157553A (ja) * | 1987-09-29 | 1989-06-20 | Matsushita Electric Ind Co Ltd | 薄膜回路の製造方法 |
JPH01307245A (ja) * | 1988-06-03 | 1989-12-12 | Matsushita Graphic Commun Syst Inc | 薄膜トランジスタ集積回路の製造方法 |
US5672521A (en) * | 1995-11-21 | 1997-09-30 | Advanced Micro Devices, Inc. | Method of forming multiple gate oxide thicknesses on a wafer substrate |
US5763922A (en) * | 1997-02-28 | 1998-06-09 | Intel Corporation | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers |
US6048769A (en) * | 1997-02-28 | 2000-04-11 | Intel Corporation | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers |
TW421962B (en) * | 1997-09-29 | 2001-02-11 | Canon Kk | Image sensing device using mos type image sensing elements |
JP2000188338A (ja) * | 1998-12-21 | 2000-07-04 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP3023355B1 (ja) | 1998-12-25 | 2000-03-21 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
US6335262B1 (en) * | 1999-01-14 | 2002-01-01 | International Business Machines Corporation | Method for fabricating different gate oxide thicknesses within the same chip |
US6133164A (en) * | 1999-02-23 | 2000-10-17 | Vantis Corporation | Fabrication of oxide regions having multiple thicknesses using minimized number of thermal cycles |
JP2001060630A (ja) | 1999-08-23 | 2001-03-06 | Nec Corp | 半導体装置の製造方法 |
US6800512B1 (en) * | 1999-09-16 | 2004-10-05 | Matsushita Electric Industrial Co., Ltd. | Method of forming insulating film and method of fabricating semiconductor device |
JP2001284466A (ja) * | 2000-03-29 | 2001-10-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP3749837B2 (ja) * | 2001-07-10 | 2006-03-01 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
US6872627B2 (en) * | 2001-07-16 | 2005-03-29 | Taiwan Semiconductor Manufacturing Company | Selective formation of metal gate for dual gate oxide application |
US6670248B1 (en) | 2002-08-07 | 2003-12-30 | Chartered Semiconductor Manufacturing Ltd. | Triple gate oxide process with high-k gate dielectric |
JP4004040B2 (ja) * | 2002-09-05 | 2007-11-07 | 株式会社東芝 | 半導体装置 |
US6706581B1 (en) * | 2002-10-29 | 2004-03-16 | Taiwan Semiconductor Manufacturing Company | Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices |
US6933235B2 (en) * | 2002-11-21 | 2005-08-23 | The Regents Of The University Of North Texas | Method for removing contaminants on a substrate |
JP4485754B2 (ja) * | 2003-04-08 | 2010-06-23 | パナソニック株式会社 | 半導体装置の製造方法 |
US6908822B2 (en) * | 2003-09-15 | 2005-06-21 | Freescale Semiconductor, Inc. | Semiconductor device having an insulating layer and method for forming |
-
2004
- 2004-07-28 US US10/900,585 patent/US7087476B2/en not_active Expired - Fee Related
-
2005
- 2005-07-15 JP JP2007521707A patent/JP2008507141A/ja active Pending
- 2005-07-15 TW TW094124133A patent/TWI301666B/zh not_active IP Right Cessation
- 2005-07-15 GB GB0700529A patent/GB2431289B/en not_active Expired - Fee Related
- 2005-07-15 WO PCT/US2005/025337 patent/WO2006028577A2/en active Application Filing
- 2005-07-15 DE DE112005001787T patent/DE112005001787T5/de not_active Ceased
- 2005-07-15 CN CNA200580025620XA patent/CN1993824A/zh active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114388349A (zh) * | 2022-03-22 | 2022-04-22 | 广州粤芯半导体技术有限公司 | 半导体器件的制备方法 |
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GB2431289B (en) | 2009-03-11 |
GB2431289A (en) | 2007-04-18 |
WO2006028577A3 (en) | 2006-06-22 |
TW200618256A (en) | 2006-06-01 |
US7087476B2 (en) | 2006-08-08 |
GB0700529D0 (en) | 2007-02-21 |
TWI301666B (en) | 2008-10-01 |
JP2008507141A (ja) | 2008-03-06 |
US20060022271A1 (en) | 2006-02-02 |
WO2006028577A2 (en) | 2006-03-16 |
DE112005001787T5 (de) | 2007-05-10 |
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