CN1667794A - 应变finFET及其制造方法 - Google Patents

应变finFET及其制造方法 Download PDF

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CN1667794A
CN1667794A CNA2004100950072A CN200410095007A CN1667794A CN 1667794 A CN1667794 A CN 1667794A CN A2004100950072 A CNA2004100950072 A CN A2004100950072A CN 200410095007 A CN200410095007 A CN 200410095007A CN 1667794 A CN1667794 A CN 1667794A
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杜雷斯蒂·奇达姆巴拉奥
奥马尔·H·多库马西
奥列格·G·格鲁钦科夫
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

提供了一种半导体结构及其制造方法。此制造方法包括在衬底中形成浅沟槽隔离(浅沟槽隔离)以及在衬底上提供第一材料和第二材料。第一材料和第二材料分别在pFET区域和nFET区域处形成第一小岛和第二小岛。在形成finFET之前，受拉伸的硬掩模被形成在第一和第二小岛层上。在具有硬掩模的finFET的侧壁上生长硅外延层，处于拉伸状态的帽层于是防止了nFET鳍的横向翘曲。

Description

应变finFET及其制造方法
技术领域
本发明一般涉及到半导体器件及其制造方法，更确切地说是涉及到具有张应力和压应力的半导体器件finFET的制造。
背景技术
半导体器件衬底中的机械应力能够改变器件的性能。亦即，半导体器件中的应力能够提高半导体器件的特性。于是，为了改善半导体器件的特性，就在n型器件(例如nFET)和/或p型器件(例如pFET)的沟道中产生张应力和/或压应力。但相同的应力分量，无论是张应力或压应力，对n型器件和p型器件的特性有不同的作用。
为了最大限度地提高集成电路(IC)芯片中的nFET和pFET二者的性能，应该对nFET和pFET不同地设计和施加各个应力分量。这是由于有利于nFET性能的应力类型通常对pFET的性能是不利的。更确切地说，当器件处于拉伸(例如沿平面器件电流流动的方向)时，nFET的性能特性被提高，而pFET的性能特性被降低。为了选择性地在nFET中产生张应力而在pFET中产生压应力，采用了不同的工艺和不同的材料组合。
例如，为了在nFET和pFET中形成适当的应力，已经分别提出了沟槽隔离结构。当采用此方法时，nFET器件的隔离区包含沿纵向(例如平行于电流流动的方向)以及沿横向(例如垂直于电流流动的方向)将第一类型机械应力施加在nFET上的第一隔离材料。而且，为pFET提供了第一隔离区和第二隔离区，且pFET器件的各个隔离区沿横向和纵向将唯一的机械应力施加在pFET器件上。
作为变通，为了选择性地在FET器件的沟道中诱发适当的应力，已经提出了栅侧壁上的衬里(见例如Ootsuka et sl.，IEDM 2000，p.575)。借助于提供衬里，与由于沟道隔离填充技术而施加的应力相比，适当的应力被施加得更靠近器件。
还已经分别提出了许多用张应力和压应力来改善nFET和pFET二者性能的建议，包括调制间隔的本征应力以及用掩模分别改变二种MOSFET的浅沟槽隔离(浅沟槽隔离)材料。弛豫SiGe上的张应变Si也已经被提议作为一种施加应力的方法。不幸的是，弛豫SiGe上的张应变Si仅仅能够将双轴张应力施加在用于叠层形式的Si帽上。这就由于pFET对应力灵敏的本性而限制了可使用的Ge百分比范围。nFET的性能随双轴张力而单调地改善；但pFET随双轴张力变坏，直至大约3Gpa才开始改善。
为了同时改善pFET和nFET二者，Ge的百分比要高，大约大于25-30％(或等效于应力大约大于3-4Gpa)。Ge百分比的这一水平难以在工艺中实现，因而不很容易制造，主要问题包括表面粗糙性、工艺复杂性、缺陷和成品率的控制等。假定高的Ge百分比难以用于pFET(因为张力水平比较低而可能不利)，则必须发明其它的方法来改善器件性能。
此外，已知Si:C外延生长在Si上固有地具有张应力。Si:C/Si材料叠层中的1％的C含量能够在Si:C中引起大约500Mpa的张应力水平。相比之下，在SiGe/Si系统中，需要大约6％来引起500Mpa的压力。如论文Ernst et al.，VLSI Symp.，2002，p.92所示，在外延生长过程中，这一1％的C水平能够被组合到Si中。在Ernst的论文中，Si/Si:C/Si位于nFET的层状沟道中。但此结构的Si:C部分不弛豫。作为替代，在Ernst的论文中，不弛豫的Si:C本身与非常薄的Si帽一起被用作部分沟道。此方法的问题在于，依赖于C含量，迁移率由于散射而未被提高，而是被抑制了。
虽然这些方法确实提供了张应力被施加到nFET器件和压应力沿pFET器件纵向被施加的结构，但它们要求额外的材料和/或更复杂的加工，因而导致更高的成本。而且，这些情况下能够施加的应力的水平典型地是中等的(亦即大约几百Mpa)。于是希望提供更节约成本且简化的方法来分别在nFET和pFET的沟道中产生大的张应力和压应力。
发明内容
在本发明的第一情况下，制造结构的方法包括形成具有第一晶格常数的材料的第一小岛以及具有第二晶格常数的材料的第二小岛。掩模被提供在第一小岛和第二小岛上，以便防止将来在侧壁被生长在鳍上时发生翘曲。此掩模处于张应力下。由第一小岛和第二小岛以及掩模来形成第一finFET和第二finFET。
在另一情况下，制造结构的方法包括在具有形成与pFET区域相关的第一小岛的第一材料以及形成与nFET区域相关的第二小岛的第二材料的衬底中形成浅沟槽隔离(浅沟槽隔离)。处于拉伸状态的硬掩模被形成在pFET区域和nFET区域上，分别被用来在pFET区域和nFET区域中形成具有硬掩模帽层的pFET鳍和nFET鳍。外延硅侧壁被生长在pFET鳍和nFET鳍上，其中，帽层防止了nFET鳍在侧壁形成过程中发生翘曲。
在本发明的另一情况下，半导体结构包括衬底以及衬底中的弛豫浅沟槽隔离(浅沟槽隔离)。第一finFET由具有第一晶格常数的第一材料组成，并提供了受强烈拉伸的材料的帽。第二finFET由具有第二晶格常数的第二材料组成，也提供了受强烈拉伸的材料的帽。外延生长的Si侧壁被提供在第一finFET和第二finFET上。第二finFET上的受强烈拉伸的材料的帽防止了第二finFET在外延侧壁生长时发生横向翘曲。
附图说明
图1-6表示形成根据本发明的中间结构的制造工艺；
图7-10表示形成根据本发明另一情况的中间结构的制造工艺；而
图11-13示出了根据本发明用图6或图10的结构作为基底来形成本发明的中间结构的制造工艺。
具体实施方式
本发明的目的是一种半导体器件以及提供与CMOS器件的nFET和pFET相关的所需应力以便改善器件性能的方法。在一种方法中，在形成finFET之前，在各个nFET和pFET沟道中得到了SiGe和Si:C小岛。然后在小岛上形成受拉伸的膜。此受拉伸的膜例如硬掩模提供了大量的横向刚性并将Si:C鳍夹持在适当的位置。亦即，受拉伸的硬掩模防止了处于强烈压应力下的鳍部分地由于预期在加工过程中形成的鳍的不对称性而发生横向翘曲。然后在弛豫的nFET鳍和pFET鳍二者上形成外延Si层，以便提供nFET和pFET的所希望的应力条件。
finFET是一种双栅结构，其中，硅本体已经被扭开其侧面以形成垂直于晶片平面竖立的硅“鳍”。栅电极被形成在鳍的二侧上，使得能够用单个掩模层和腐蚀同时确定二个栅。如在本发明中实现的那样，此鳍最好对称于双栅，但可以不对称于单个栅。还应该理解的是，此finFET借助于简单地调整鳍的尺度就提供了更高的驱动电流密度，而不要求栅氧化物厚度的减小及其相关的泄漏。在本发明中，在相对受应力状态下得到了各个finFET，这改善了器件的性能。
在本发明之前，利用其中小岛具有比较大的尺寸的晶片键合技术，才有可能安置用来制造具有不同弛豫晶格(原子之间的不同尺度)的nFET和pFET的至少二种小岛；但在本发明中，各种方法产生了一种独特的具有弛豫的但不同晶体结构的小晶体小岛的衬底。在一种方法中，提供了采用高温稳定的非晶材料例如二氧化硅在小岛之间而晶体在绝缘体上的结构。具有不同(晶体)小岛的独特结构使得能够安置可选不同晶体的不同应变层。在第一情况下，这些不同应变层是用来形成本发明finFET的受拉伸的SiGe层或受压缩的Si:C层。
本发明对于在绝缘体上制作具有多种晶格常数的小岛的衬底的工艺来说，具有创新的重要贡献。例如，在本发明中，第一finFET(晶体1)的晶格常数a≥aSi，而第二finFET(晶体2)的晶格常数a≤aSi。在本发明的一种情况下，如下面更详细地讨论的那样，本发明的将分别在SiGe finFET和Si:C finFET上张应变和压应变的Si外延侧壁层能够被选择性地生长。
现在参照图1，示出了一种硅晶片。这种晶片是各种分立和集成电路(IC)半导体器件应用的市售起始衬底。在一种方法中，可以用采用大剂量氧注入和高温退火在本体晶片中形成BOX(埋置的氧化物)的SIMOX(利用注入的氧进行分离)方法，来制造玻璃晶片上的硅(SOI)。作为另一例子，可以借助于将器件质量的硅晶片键合到其表面上具有氧化物层的另一硅晶片(衬底层)，来制造晶片。然后采用在衬底层上的氧化物层(已经成为BOX)的顶部上留下薄的(相对于起始晶片的厚度)器件质量的单晶硅层的工艺，将成对的晶片分离开。也可以用其它的工艺来形成SOI晶片。
仍然参照图1，形成了硅层20，并用标准的衬垫氧化技术、衬垫氮化物淀积技术、以光刻为基础的图形化技术、由氮化物、氧化物、以及硅组成的叠层的直达埋置氧化物的反应离子刻蚀(RIE)技术、边沿氧化技术、衬里淀积技术、填充物淀积技术、以及化学机械抛光技术来进行图形化，以便形成浅沟槽隔离(浅沟槽隔离)25。浅沟槽隔离形成工艺是熟知的技术。在一种方法中，将例如SiO2的高温稳定非晶材料用于浅沟槽隔离。
参照图2，利用诸如化学气相淀积方法之类的常规技术，在结构的表面上淀积外延锗材料(层)30。例如，可以以常规的方式使用超高真空化学气相淀积(UHVCVD)方法来淀积锗层30。其它的常规技术包括快速热化学气相淀积(RTCVD)、限止反应加工CVD(LRPCVD)、以及分子束外延(MBE)。在一个实施方案中，依赖于例如可以是30-100nm的下方硅层的厚度，锗材料的厚度可以是5-50nm或其它的尺寸。
nFET硬掩模35被提供在部分锗层30上(例如在要形成nFET器件的位置处)。此nFET硬掩模35可以是用诸如甩涂、CVD、等离子体辅助CVD、超高真空化学气相淀积(UHVCVD)、快速热化学气相淀积(RTCVD)、限止反应加工CVD(LRPCVD)、以及其它相似的淀积工艺之类的常规淀积工艺所形成的氮化物硬掩模。
在图3中，暴露的锗层30被腐蚀，并用本技术熟知的技术剥离nFET掩模35。例如，可以用RIE、湿法腐蚀、或干法腐蚀方法来选择性地腐蚀锗层30。
如图4所示，Si:C材料40(或可选地C)被淀积在结构上，包括淀积在外延淀积的Ge材料35上。例如，可以以常规的方式采用超高真空化学气相淀积(UHVCVD)方法来淀积Si:C(或可选地C)材料40。其它常规技术包括快速热化学气相淀积(RTCVD)、限止反应加工CVD(LRPCVD)、以及其它相似的工艺。在一个实施方案中，依赖于例如可以是30-100nm的下方硅层的厚度，Si:C或C材料的厚度可以是5-50nm或其它的尺寸。在另一情况下，当采用C时，厚度可以是1-30nm。
pFET硬掩模45被提供在部分Si:C材料40上要形成pFET的位置处。此pFET硬掩模45可以是用诸如甩涂、CVD、等离子体辅助CVD、超高真空化学气相淀积(UHVCVD)、快速热化学气相淀积(RTCVD)、限止反应加工CVD(LRPCVD)、以及其它相似的淀积工艺之类的常规淀积工艺所形成的氮化物硬掩模。
如图5所示，暴露的Si:C层40然后被腐蚀，并用本技术熟知的技术剥离pFET掩模45。例如，可以用诸如RIE、湿法腐蚀、或干法腐蚀之类的标准腐蚀技术来腐蚀Si:C和pFET。
然后，在图6中，此结构经历热退火工艺。在此工艺过程中，对于nFET来说，淀积的Ge材料30被混合到下方的SOI膜中，从而形成基本上是SiGe材料的小岛50。同样，在此工艺中，对于pFET来说，淀积的Si:C或可选的C材料被混合到下方的SOI膜中，形成基本上是Si:C材料的小岛55。热退火工艺在例如大约1200-1350℃下进行1-10小时，一种情况是在1200℃下进行大约5小时。
利用本发明的方法，所要求的锗百分比对于nFET是不大的(例如小于25％，且在一种方法中是10-20％)，因而不引起缺陷问题。而且，由于高温热混合步骤，例如浅沟槽隔离25能够弛豫且使SiGe小岛50和Si:C小岛55容易弛豫。这是由于部分是因为浅沟槽隔离包含氧化物材料，这种氧化物材料在高温下是一种粘滞性材料，例如在高温下成为一种低粘滞性材料。
还应该理解的是，SiGe小岛50和Si:C小岛55具有不同的弛豫晶格(原子之间不同的尺寸)，这产生了具有小晶体小岛的独特衬底。与满铺(SiGe或Si:C)衬底相比，SiGe小岛50和Si:C小岛55的弛豫提供了改进的性能。在一种情况下，根据本发明采用了SiGe小岛50和Si:C小岛55之间的高温稳定非晶材料例如二氧化硅和绝缘体上晶体的结构。
图7-10示出了本发明的另一种情况。在图7中，示出了诸如SOI的硅晶片。如在前述结构中那样，可以用SIMOX工艺或其它熟知的工艺来制造此SOI。利用标准的衬垫氧化技术、衬垫氮化物淀积技术、以光刻为基础的图形化技术、由氮化物、氧化物、以及硅组成的叠层的直达埋置氧化物的反应离子刻蚀(RIE)技术、边沿氧化技术、衬里淀积技术、填充物淀积技术、以及化学机械抛光技术，硅层20被图形化，以便形成浅沟槽隔离(浅沟槽隔离)25。浅沟槽隔离的形成工艺在本技术中是众所周知的。
参照图8，pFET掩模40被提供在部分结构上要形成pFET的位置处。可以用诸如各种化学气相淀积方法之类的常规技术来淀积pFET硬掩模。例如这些技术可以包括甩涂、CVD、等离子体辅助CVD、蒸发、超高真空化学气相淀积(UHVCVD)、快速热化学气相淀积(RTCVD)、限止反应加工CVD(LRPCVD)、以及其它相似的淀积工艺。
利用常规技术，外延锗层30被选择性地生长在要形成nFET的暴露表面上。在一个实施方案中，依赖于例如可以是30-100nm的下方硅层的厚度，锗材料的厚度可以是5-50nm或其它的尺寸。如上所述，用众所周知的工艺来剥离硬掩模45。
在图9中，nFET掩模35被提供在部分结构上要形成nFET的位置处。如各处讨论的以及一般熟练人员应该知道的那样，可以用诸如化学气相淀积方法之类的常规技术来淀积nFET硬掩模。
如上所述，利用诸如化学气相淀积方法之类的常规技术，Si:C层40被选择性地生长在要形成pFET的结构的暴露表面上。在一个实施方案中，依赖于例如可以是30-100nm的下方硅层的厚度，Si:C材料的厚度可以是5-50nm或其它的尺寸。C甚至可以更薄，为1-50nm。
如图10所示，然后用众所周知的工艺来清除FET硬掩模35。此结构然后经历热退火工艺。在此退火工艺过程中，对于nFET来说，Ge材料30被混合到SOI膜中，形成基本上是SiGe材料的小岛50。同样，对于pFET来说，Si:C或可选的C材料被混合到SOI膜中，形成基本上是Si:C材料的小岛55。此工艺还形成BOX层作为衬底。热退火工艺在例如大约1200-1350℃下进行1-10小时，一种情况是在1200℃下进行大约5小时。
如上所述，与前面的情况相似，利用本发明的方法，所要求的锗百分比是不大的(例如小于25％，且在一种情况下是10-20％)，因而不引起缺陷问题。而且，由于高温热混合，例如浅沟槽隔离25能够弛豫且使SiGe小岛50和Si:C小岛55容易弛豫。如上所述，与满铺(SiGe或Si:C)衬底相比，SiGe和Si:C的弛豫提供了改进的性能。在一种情况下，这种结构的要点是在小岛之间使用高温稳定的非晶材料例如和绝缘体上晶体结构。
在本发明的另一情况下，可以在大剂量下将C注入到pFET区域中，这能够在热退火时在Si:C中产生比1-4％的C高得多的浓度。此剂量可以约为每平方厘米1×1016，或大于例如每平方厘米5×1016。
现在利用图6或图10的中间结构，如图11所示，受拉伸的硬掩模被淀积在结构上。在一种情况下，硬掩模是氮化物，并以任何熟知的常规方式被淀积在结构上。例如，此氮化物硬掩模可以是用诸如甩涂、CVD、等离子体辅助CVD、超高真空化学气相淀积(UHVCVD)、快速热化学气相淀积(RTCVD)、限止反应加工CVD(LRPCVD)、以及其它相似的淀积工艺之类的常规淀积工艺所形成的硬掩模。在一种情况下，依赖于下方层的厚度，此硬掩模被淀积成5-50nm或其它尺寸。
然后，如图12所示，以常规方式执行侧壁图象转移和腐蚀，以便形成鳍75和80。例如，用侧壁图象转移光刻术来确定鳍，将鳍置于制作的矩形(芯子)的外围上。随后，修剪掩模被用来清除环的不需要部分，且常规抗蚀剂掩模被用来挡住源区和漏区(未示出)，以便将各个鳍连接到一起。在此工艺过程中，硬掩模70保留作为nFET和pFET区的帽。
在图13中，硅外延层85被选择性地生长在nFET和pFET的侧壁上。如下面所讨论的那样，此硅外延层可能不对称地生长，因而可能由于其强烈压缩状态而诱发翘曲。但强烈拉伸的硬掩模会借助于使硅生长过程中作用在nFET区域上的各种力基本上相等而确保和均匀防止这种翘曲。
应该理解的是，硅外延侧壁层的晶格常数不同于SiGe和Si:C“小岛”或被腐蚀的鳍的晶格常数。例如，SiGe的晶格常数a≥aSi，而Si:C的晶格常数a≤aSi。亦即，单独地说，硅的晶格常数通常比SiGe层更小；亦即硅材料的晶格常数与SiGe的晶格常数不匹配。但在本发明的结构中，硅侧壁层的晶格结构倾向于与SiGe的晶格结构匹配。于是，由于硅与SiGe层的晶格匹配(硅的晶格通常更小)，故硅层被置于张应力下。此区域将用作nFET的应变沟道。在一个实施方案中，在对硅含量的比率中，SiGe层的Ge含量可以小于25％。
而且，单独地说，硅通常也具有比Si:C更大的晶格常数。亦即硅材料的晶格常数与Si:C的晶格常数不匹配。但在本发明的结构中，硅层的晶格结构倾向于与Si:C的晶格结构匹配。由于硅与Si:C小岛的晶格匹配(硅的晶格通常更大)，故硅层被置于压应力下。亦即，相似于SiGe的情况，Si:C小岛的周围区域将试图获得平衡状态，从而导致形成在Si:C上的外延硅侧壁层的压应力。此区域将用作pFET的应变沟道。在一个实施方案中，在淀积时，在对硅含量的比率中，C的含量可以高达大约4％。
如图13所示，形成的结构是一种适合于根据本发明的原理形成诸如pFET和nFET的半导体器件的中间结构。如finFET技术领域众所周知的那样，为了形成最终的器件，可以执行CMOS工艺在此结构上形成n和p finFET器件。例如，这些器件可以包括被应变SiGe和Si:C的半导体沟道分隔开的源区和漏区的离子注入。亦即，nFET将被形成在拉伸应变的沟道上，而pFET将被形成在压应变的硅沟道上。栅介质被提供在应变沟道的顶部，且栅导体被提供在栅介质的顶部上。
虽然根据实施方案已经描述了本发明，但本技术领域的熟练人员可以理解的是，本发明能够以所附权利要求的构思与范围内的修正来加以实施。例如，本发明能够被容易地应用于体衬底。

Claims (20)

1.一种用于制造一种结构的方法，它包含下列步骤：
形成具有第一晶格常数的材料的第一小岛；
形成具有第二晶格常数的材料的第二小岛；
在第一小岛和第二小岛上提供掩模，此掩模被用来形成受拉伸的帽层；以及
由第一小岛和第二小岛形成至少一个第一finFET和第二finFET，
其中，受拉伸的帽层防止了第一和第二finFET之一发生翘曲。
2.权利要求1的方法，其中，第一小岛由SiGe材料组成，而第二小岛由Si:C组成，且掩模是氮化物硬掩模。
3.权利要求1的方法，其中，用侧壁图象转移和腐蚀方法来形成第一和第二finFET。
4.权利要求1的方法，还包含在第一finFET和第二finFET的侧壁上选择性地生长硅外延侧壁层，其中，受拉伸的帽层防止了至少第二finFET在其上生长硅外延侧壁层的过程中发生翘曲。
5.权利要求1的方法，其中：
腐蚀方法从第一和第二finFET上的硬掩模形成了受拉伸的帽层；
第一finFET由SiGe组成，并被置于张应力下；而
第二finFET由Si:C组成，并被置于压应力下。
6.权利要求5的方法，其中，受拉伸的帽层防止了Si:C finFET的皱缩或翘曲。
7.权利要求1的方法，还包含：
在衬底中形成浅沟槽隔离；
将材料混合到衬底中，以便用热退火工艺在pFET区域和nFET区域分别形成第一小岛和第二小岛；且
其中，浅沟槽隔离弛豫且使第一小岛和第二小岛容易弛豫。
8.权利要求1的方法，其中，用淀积和生长Ge材料的方法来形成第一小岛，且用淀积和生长Si:C或C材料的方法来形成第二小岛，第一小岛和第二小岛具有不同的弛豫晶格。
9.权利要求4的方法，其中，硅外延侧壁层的晶格常数不同于第一材料和第二材料的晶格常数，致使选择性生长的硅外延侧壁层将分别在第一小岛和第二小岛上张应变和压应变。
10.权利要求4的方法，其中，第一finFET的晶格常数a≥aSi，而第二finFET的晶格常数a≤aSi。
11.权利要求1的方法，其中，第一小岛基本上由SiGe组成，而第二小岛基本上由Si:C组成，且外延生长的侧壁层被生长在分别由SiGe小岛和Si:C小岛形成的被腐蚀的SiGe finFET以及Si:CfinFET上，由于外延生长的侧壁层与SiGe和Si:C finFET的晶格匹配，故SiGe finFET和Si:C finFET被分别置于张应力和压应力下。
12.一种制造半导体结构的方法，它包含下列步骤：
在具有第一材料的衬底中形成浅沟槽隔离；
形成与pFET区域相关的第一小岛以及与nFET区域相关的第二小岛；
在pFET区域和nFET区域上提供处于张应力下的硬掩模；
分别在pFET区域和nFET区域中形成具有硬掩模帽层的pFET鳍和nFET鳍；以及
在pFET鳍和nFET鳍上生长侧壁，其中，帽层防止了nFET鳍在侧壁生长过程中发生翘曲。
13.权利要求12的方法，其中，pFET鳍由包含SiGe的材料组成，而nFET鳍由包含Si:C或C之一的材料组成。
14.权利要求13的方法，其中，SiGe变成张应变，而Si:C变成压应变，且硬掩模借助于基本上抵消nFET上形成侧壁所形成的压应力而防止了nFET鳍的翘曲。
15.权利要求12的方法，还包含弛豫浅沟槽隔离，这使第一小岛和第二小岛在热退火步骤中容易弛豫。
16.权利要求12的方法，其中，侧壁由晶格常数不同于pFET鳍和nFET鳍的硅组成，致使硅侧壁将分别对pFET鳍和nFET鳍施加张应力和压应力。
17.一种结构，它包含：
衬底；
衬底中弛豫的浅沟槽隔离；
由具有第一晶格常数的第一材料和强烈受拉伸材料的帽组成的第一finFET；
由具有第二晶格常数的第二材料和强烈受拉伸材料的帽组成的第二finFET；以及
第一finFET和第二finFET上的外延生长Si侧壁，
其中，第二finFET上的强烈受拉伸材料的帽防止了第二finFET在硅外延侧壁生长时发生横向翘曲。
18.权利要求17的结构，其中，第一材料是弛豫的SiGe，而第二材料是弛豫的Si:C。
19.权利要求17的结构，其中，帽由氮化物组成。
20.权利要求17的结构，其中，浅沟槽隔离被基本上弛豫，且第一finFET处于张应力下，而第二finFET处于压应力下。
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