CN1639861A - 用于制作mim电容器的方法 - Google Patents
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L28/40—Capacitors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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Abstract
一种制作金属-绝缘体-金属(MIM)电容器结构的方法包括在半导体衬底(10)的介质层(20)中制作凹槽。在凹槽内制作第一电容器电极(30,40),凹槽中具有铜第一金属层(30)和在第一金属层(30)上制作的导电的氧化阻挡层(40)。将第一电容器电极(30,40)相对于介质层(20)进行平整。在第一电容器电极(30,40)上制作绝缘体(50),而且在绝缘体(50)上制作第二电容器电极(65)。在凹槽内制作第一电容器电极(30,40)使铜第一金属层(30)的周边与导电的氧化阻挡层(40)保持对准。
Description
技术领域
本发明通常涉及半导体器件领域,更具体地,涉及如半导体器件中所使用的金属-绝缘体-金属(MIM)电容器。
背景技术
由于半导体器件缩小,所以需要减小部件(比如电容器)占用的面积。为了适应这种需要,与在更靠近主要半导体衬底的晶体管层面上制作电容器相反,将在晶体管外面(也就是在金属层面上)制作电容器。这种电容器的例子就是金属-绝缘体-金属(MIM)电容器。在金属面上,由于多晶硅的沉积是高温过程,与后面(金属之后)的处理不相容,所以多晶硅不能用作电极材料。在半导体制造中,铜正替代铝和铝合金作为金属相互连接的主要材料。因此,为避免增加更多的材料和处理步骤,使用铜作为MIM电容器电极的金属是有利的。然而,在与许多高介电常数材料的连接中,存在与使用铜相关的问题,这些高介电常数材料需要被用于MIM电容器,特别是在需要高容量线性的RF应用中使用的电容器。高线性电容是一种恒定的电容,该电容是使用电压和频率的函数。已知的使用铜作为电极材料的问题包括由于铜表面机械和化学稳定性不良导致的不利影响,以及铜与电容器介质材料的其它相互作用(也就是铜扩散)。
因此,存在对MIM电容器结构的需要,这种MIM电容器结构包括使用铜作为电容器电极,这种电容器电极的制作能够容易与半导体制造的其它次序相结合,结果导致具有高线性和高电容的电容器,而且减轻了与铜作为电容器电极之一相关的许多问题。
发明内容
根据本发明的一方面,提供一种制作金属-绝缘体-金属(MIM)电容器结构的工艺包括:提供半导体衬底;在半导体衬底上制作介质层;在介质层上制作凹槽;在凹槽中制作第一金属层,第一金属层包含铜;对第一金属层制作凹槽,其中通过刻蚀第一金属层的方法制作凹槽;在第一金属层上制作第二金属层,第二金属层是用作第一金属层的导电的氧化阻挡层;在第二金属层上制作绝缘体;以及在绝缘体上制作第三金属层。根据本发明的另一方面,提供一种制作半导体器件结构的工艺包括:
根据本发明的另一方面,提供半导体器件;在半导体衬底上制作第一介质层;在第一介质层内制作凹槽;在凹槽中制作第一金属层,第一金属层包含铜;对第一金属层制作凹槽,其中通过刻蚀第一金属层的方法制作凹槽;以及在第一金属层上制作第二金属层,第二金属层是用作第一金属层的导电的氧化阻挡层。
附图说明
本发明采用举例的方式但不局限于举例进行说明,在这些举例中同样的参考标记表示类似的元件,而且其中:
图1说明在横截面中具有半导体器件和介质层的半导体器件的部分,该介质层可用于根据本发明一个实施方式制作MIM电容器。
图2说明根据本发明一个实施方式制作开口和沉积第一金属层后的图1中的器件。
图3说明根据本发明一个实施方式平整第一金属层后的图2中的器件。
图4说明根据本发明一个实施方式刻蚀第一金属层以制作凹槽后的图3中的器件。
图5说明根据本发明一个实施方式在凹槽内沉积第二金属层后的图4中的器件。
图6说明根据本发明一个实施方式平整第二金属层以制作MIM电容器的底部电极后的图5中的器件。
图7说明根据本发明一个实施方式制作电容器介质层、第三金属层和刻蚀终止层后的图6中的器件。
图8说明根据本发明一个实施方式沉积第一光致抗蚀剂层后的图7中的器件。
图9说明根据本发明一个实施方式对第三金属层和刻蚀终止层制作图案以形成MIM电容器的顶部电极后的图8中的器件。
图10说明根据本发明一个实施方式制作中间层介质层以及用于对中间层介质层形成图案的光致抗蚀剂层后的图9中的器件。
图11说明根据本发明一个实施方式制作用于电接触MIM电容器的导电通路后的图10中的器件。
熟练的技术人员意识到图中的元件是为简单和清楚地说明,没有必要按比例绘出。例如,相对于其它元件将图中一些元件的尺寸可能夸大以帮助改善对本发明具体实施方式的理解。
具体实施方式
由于金属氧化物具有高介电常数,因此为了增加MIM电容器结构的电容,使用金属氧化物作为电容器绝缘体是适当的。一般地,这样的金属氧化物具有大于大约20的介电常数。然而,在铜电极外面制作金属氧化物时,铜的不可预见的氧化在电极和随后沉积的材料之间产生不相容的界面。更具体地,电容器介质与电极之间粘合不良而且铜氧化物薄膜的存在可能不可预见地增加电容器的泄漏。
根据本发明,通过在铜电极30和金属氧化物50之间制作导电的氧化阻挡层40,制作具有高容量密度以及在金属氧化物介质50与铜电极30之间粘合良好的MIM电容器。为了减少工艺的复杂性,在凹槽205内铜开口200的上面制作导电的氧化阻挡层40。MIM电容器的底部电极包括导电的氧化阻挡层40和铜电极30。在优选的实施方式中,导电氧化物阻挡层40是氮化钽。然后可以在不形成铜氧化物层的情况下沉积氧化钽或者氧化铪。因此,最终的电容器结构能够具有高电容、低泄漏以及稳定的界面,并且容易制作。结合附图,对使用导电的氧化阻挡层的本发明的一个具体实施方式进行描述。
图1~11说明根据本发明经过系列加工步骤以制作MIM电容器时半导体器件的一部分。更具体地,图1说明在半导体衬底10上面制作介质层20。在优选的具体实施方式中,半导体衬底10是硅。然而,可以应用其它半导体材料,如砷化镓和绝缘体上硅(SOI)。有代表性地,衬底10将包括许多各种各样的有源半导体器件(如金属-氧化物-半导体(MOS)和/或双极晶体管)。然而,对于理解本发明,没有必要理解这些器件,因此没有对这些器件进行说明。
介质层20是通过化学气相沉积(CVD)、物理气相沉积(PVD)或者上述方法相结合等方法进行沉积的,而且介质层20可以是任何电介质材料,如氧化硅。
为了制作图2的结构,对介质层20制作图案并对其进行刻蚀以制作开口200,有时称为沟槽或者凹槽。优选通过采用PVD、CVD、电镀、上述方法相结合等方法沉积电极材料,在介质层20的上面和在开口内制作第一金属层30。在最好的具体实施方式中,第一金属层30包含铜,例如,第一金属层30可以是铜或者铝铜合金。在一个实施方式中,第一金属层30大部分是铜。金属层材料可以采用PVD、CVD、原子层沉积(ALD)、电镀、上述方法相结合等方法进行沉积。此外,实际上第一金属层30可以由多种材料制成。例如,在铜嵌入金属化设计中,通常沟槽被包含钽或者氮化钽的扩散阻挡层衬在里面。
图3所示为平整第一金属层30以制作第一金属层30后的半导体器件,第一金属层为镶嵌结构。可以通过化学机械抛光(CMP)、内腐蚀,比如湿法或者干法刻蚀工艺等平整第一金属层30。如果对第一金属层30进行抛光,则可以将其开槽以帮助控制抛光过程中铜的凹陷。电容器的面积通常比附近的集成电路互连电路的面积大,而且大面积的铜容易在抛光过程中凹陷。在这样的情况下,将该材料开槽是已知的减轻这个问题的方法。
图4中所示,第一金属层30的部分被去除以在开口200内制作凹槽205,从而制作第一金属层30。换句话说,对第一金属层30制作凹槽。凹槽205在沟槽200的最上面部分以下延伸。根据特定的实施方式,采用反应离子刻蚀(RIF)工艺或者湿法刻蚀工艺制作凹槽205,湿法刻蚀工艺以大于大约3~5倍去除介质层20部分的速度去除部分第一金属层30。有代表性地,凹槽205的深度大约在50到2000埃之间而且大约为开口200深度的1/4到1/3。凹槽205的数量由随后制作的底部电极的厚度要求确定,将在下文中对底部电极进行说明。在一个具体实施方式中,在旋转刻蚀工艺中采用湿的刻蚀剂制作凹槽205。在这种旋转刻蚀工艺中,半导体器件放置在卡盘上,以1000~1200rmp的速度旋转,而且刻蚀剂分配到半导体器件上。有代表性地,刻蚀过程持续10~60秒。有代表性地,实际的刻蚀步骤之后有使用去离子水在与旋转刻蚀的相同处理工具中进行10~30秒旋转冲洗的步骤。刻蚀剂的化学成分取决于第一金属层30的成分。例如,如果第一金属层30是铜,刻蚀剂则可以包含酸,如HNO3、HCl、H2SO4或者它们的组合。
或者,与首先平整第一金属层30然后对其进行刻蚀相反,可以在制作第一金属层30之后采用单一的旋转刻蚀工艺制作凹槽205。在该具体实施方式中,使晶片旋转速度、刻蚀剂的化学成分以及刻蚀剂的分配分布最优化以控制刻蚀工艺的均匀和平整性。
制作凹槽205后,通过PVD、CVD、ALD、电镀、化学镀、上述方法相结合等方法制作导电的氧化阻挡层40,如图5所示。导电的氧化阻挡层40沉积在介质层20和开槽的第一金属层30的表面上。导电的氧化阻挡层40可以是能发生氧化而且还能作为下层第一金属层30的阻挡层的任何材料。较好地发生氧化并且对包括铜在内的材料作为阻挡层的材料有钽、钛、铂、铱、铝、钌、钨、氮化钽、氮化钛等等。通常,导电的氧化阻挡层40是金属或者金属合金并能作为第二金属层40。在优选的实施方式中,为了制作充分平整的表面以在随后制作上层薄膜,使凹槽205充满导电的氧化阻挡层40。因此,导电的氧化阻挡层厚度为50到2000埃。然而,没有必要使开口200完全充满第一金属层30和导电的氧化阻挡层40。导电的氧化阻挡层40应该足够厚以发生氧化并作为第一金属层30的扩散阻挡层。此外,导电的氧化阻挡层40还应该足够薄,以使随后完成的MIM电容器的阻抗以及在半导体衬底上MIM电容器附近制作的互连的阻抗不发生很大地增加。而且,导电的氧化阻挡层40还应该与第一金属层30以及随后制作的电容器介质层具有良好的粘合性。
图6所示为平整导电的氧化阻挡层40后的半导体器件。在一个实施方式中,导电的氧化阻挡层40被去除到凹槽205的外面,以使导电的氧化阻挡层40的周边与第一金属层30的周边自对准。可以使用用于平整第一金属层30的任何方法。经过抛光后,要求导电的氧化阻挡层40的顶部表面与介质层20的顶部基本共面。抛光工艺达到这些结果的能力决定于制作凹槽205后第一金属层30的表面形貌以及工艺的选择性。因此,光滑的第一金属层30表面和导电的氧化阻挡层40的高选择性是必要的。基本共面的导电的氧化阻挡层40防止下面的铜电极中发生的纳米尺度的氧化和铜原子向随后沉积的绝缘材料中进行的纳米尺度的扩散,如果发生,任一情形将使电容器的漏电严重化。
在半导体衬底10上分别沉积电容器介质层50、第三金属层60和刻蚀终止层(ESL)70,如图7中所示。电容器介质层50是在导电的氧化阻挡层40上通过采用CVD、PVD原子层沉积(ALD)、上述方法相结合等方法制作的绝缘体。对于RF应用,电容器介质层50最好包含具有高线性的金属氧化物(也就是,有代表性地,标称电容的变化小于百万分之100电压单位),如氧化钽和氧化铪。然而,对于线性可以不太关键的一般应用,其它的金属氧化物如氧化锆、氧化铝、钡钛酸锶(BST)以及钛酸锶(STO)可以是合适的。最好采用PVD,但也可以应用CVD、ALD或者它们相结合的方法,在电容器介质层50的外面制作第三金属层60。第三金属层60将形成电容器的第二(顶部)电极,因此,第三金属层60可以由任何导电材料如钽、氮化钽、钛、氮化钛、钌、铱、铜、铝、铂、钨和上述金属相结合等制成。
在一个实施方式中,第三金属层60包含氮和钽或钛二者之一(以氮化钽或者氮化钛的形式)。如果第三金属层60是铜,则需要在第三金属层60与电容器介质层50之间制作第二氧化阻挡层,如用于氧化阻挡层40的材料。然而,由于在金属氧化物沉积之后制作铜电极,铜电极没有暴露在氧化性气氛中,因此不存在由铜氧化引起的粘合问题。
ESL层70也是采用PVD、CVD、ALD或者它们相结合的方法沉积的。下文中将显而易见,ESL层70用作刻蚀后沉积的夹层绝缘体(ILD)时的刻蚀终止层。ESL层70还可作为金属层60刻蚀的硬掩模。而且,ESL层70可用作抗反射涂层(ARC)以在随后的光刻工艺中改善光学性质。在优选的实施方式中,ESL层70是氮化硅或者氮化铝,或者选择氧化钽或氧化铪。在下文中参照图10将获得ESL层70的更详细的用途。
可以采用相同或者不同的工艺制作电容器介质层50、第三金属层60和ESL层70。但是,对于电容器介质层50、第三金属层60和ESL层70,希望采用同样的工艺进行制作以提高大空间生产环境中的工艺控制和产量。
转到图8,为了刻蚀ESL层70和第三金属层60,沉积第一光致抗蚀剂层80并使其形成图案。刻蚀ESL层70和第三金属层60后,制作了顶部(电容器)电极65(或者第二电极65),如图9中所示。采用传统的方法形成图案之后,去除第一光致抗蚀剂层80。
转到图10,在半导体衬底10上沉积ILD90。为了刻蚀ILD层90以制作通路开口,沉积第一光致抗蚀剂层100并使其形成图案,通路开口被填充金属以制作导电通路110,如图11中所示。使用第一化学成分刻蚀在ESL层75(呈现的地方)和电容器介质层50上终止且暴露部分的通路开口,ESL层75和电容器介质层50都可作为中间的刻蚀终止层。由于要被刻蚀制作成顶部电极上通路开口的部分ILD的厚度实质上地小于被刻蚀以制作用于导电的氧化阻挡层40的刻蚀工艺开口的部分ILD的厚度,因此,不应该采用第一化学成分对ESL层75进行完全地刻蚀。这使得在刻蚀顶部电极65上的通路开口后,能够连续刻蚀工艺以制作更深的用于导电的氧化阻挡层40的通路开口。因此,对于ESL层材料以及或许甚至是电容器介质层50,需要第一化学成分是选择性的。
接下来,将刻蚀化学成分转换到第二化学成分以刻蚀电容器介质层50和ESL层75从而完全地制作转接头开口并露出下面的导电部分。尽管工艺使用两种不同的刻蚀化学成分,但为了提高产量和生产效率,可以在同样的工具甚至同样的容器中进行转接头开口的刻蚀。
如图11中所示,制作转接头开口后,为了制作导电转接头110,要在转接头开口内制作导电材料。在转接头开口内制作的导体形成顶部电极65和导电的氧化阻挡层40的接触。在一个实施方式中,进行铜电镀并对其背面进行化学机械抛光以制作导电转接头110。
由于使用金属氧化物作为主要的电容器介质,在金属氧化物与铜电极之间不存在不良界面的缺点,因此图11中所示的最终MIM电容器比先前提及的结构具有更高的电容。由于具有相容的界面,所以根据本发明的结构提高了漏电特性。此外,由于本发明使本身具有高线性的金属氧化物电容器介质的应用成为可能,因此MIM结构具有高线性。这样的位于芯片上的电容器广泛适用于需要高频率(>1GHz)的RF电路,以及混合信号模拟和过滤。而且,由于导电的氧化阻挡层40是自对准的,因此不需要采用光刻步骤以使导电的氧化阻挡层40形成图案。
附图所示说明的实施方式是MIM电容器,其中,与一同形成底部(电容器)电极的第一金属层30和导电的氧化阻挡层40相比,顶部电极65尺寸较小。在另外一个具体实施方式中,与第一金属层30和导电的氧化阻挡层40相比,顶部电极65尺寸可以更大。在该实施方式中,由于接触位于第一金属层30的下面,因此在制作第一金属层30和导电的氧化阻挡层40之前制作用于导电的氧化阻挡层40的接触,而不是在导电的氧化阻挡层40上制作接触。而且,在该实施方式中,对ESL层70和第三金属层60进行刻蚀时,能够在不破坏电容器结构关键部分的情况下完全将电容器介质层50去除。这样,在ILD层90的下面存在高介电常数的缺点得到克服。然而,仍然存在当从MIM电容器外部区域去除电容器介质层50时,该层下面的其它结构例如附近的铜衬垫结构可能被破坏的问题。这种相关的结构并没有明确地显示于附图中,但这种结构一般通常以IC互连电路的基本部分呈现在芯片上。
尽管上述的实施方式是关于MIM电容器的,但也可能在其它应用中使用该制作方法以减少铜的氧化以及提高粘合性,例如在半导体衬底上制作的最后金属层。
上面已经结合特殊的具体实施方式对好处、其它优点以及问题的解决办法进行了说明。然而,好处、优点、问题的解决办法以及可能导致任何好处、优点或者解决办法产生或变得更明显的任何要素,都不是解释成任何或者全部权利要求的关键、必需或者基本的特征或要素。这里所使用的,“包含”、“由...组成”或者它们的其它任何变化的术语,意指覆盖非排他性的含义,这样,包含一系列要素的工艺、方法、制品或者设备并不只包括那些要素,而是可以包括其它没有列出或者这种工艺、方法、制品或者设备所固有的要素。
在前述的说明书中,已经参照特定的实施方式对本发明进行了说明。然而,一个普通的该技术的熟练人员意识到在不背离下面权利要求书提出的本发明的范围的情况下,可以进行各种各样的修改和变化。例如,象已经描述和说明的那样,在器件中以单镶嵌方式制作MIN电容器。但是,一个普通的技术熟练人员将认识到类似的结构可以合并成双镶嵌整体。因此,说明书和附图将被认为是说明性的而不是限制性的,而且所有这样的修改意为包含在本发明的范围之内。
权利要求书
(按照条约第19条的修改)
1、一种制作金属-绝缘体-金属电容器结构的方法,包括:
提供半导体衬底(10);
在半导体衬底(10)上制作介质层(20);
在介质层(20)中制作凹槽(205);
在凹槽中制作第一金属层(30),第一金属层包含铜;
对第一金属层(30)制作凹槽,其中通过刻蚀第一金属层的方法制作凹槽;
在第一金属层(30)上制作第二金属层(40),第二金属层(40)是用作第一金属层(30)的导电的氧化阻挡层;
在第二金属层(40)上制作绝缘体(50);以及
在绝缘体(50)上制作第三金属层(60)。
2、权利要求1的方法,其中制作第一金属层(30)还包括:
在所述介质层(20)的表面上沉积所述第一金属层(30);和
平整所述第一金属层(30)以制作镶嵌结构。
3、权利要求1的方法,其中制作第二金属层(40)还包括制作所述第二金属层(40)到具有50到2000埃的厚度。
4、权利要求1的方法,其中制作第二金属层(40)包括:
在所述介质层(20)的表面和所述被制作凹槽的第一金属层(30)上沉积第二金属层(40);
去除所述第一金属层(30)中凹槽(205)外面的所有所述第二金属层(40),以使所述第二金属层(40)的周边与所述第一金属层(30)的周边自对准;以及
平整所述第二金属层(40)使其与所述介质层(20)的表面共面。
5、一种制作半导体器件结构的方法,包括:
提供半导体器件(10);
在半导体衬底(10)上制作第一介质层(20);
在第一介质层(20)中制作凹槽(205);
在凹槽(205)中制作第一金属层(30),第一金属层(30)包含铜;
对第一金属层(30)制作凹槽,其中通过刻蚀第一金属层的方法制作凹槽;以及
在第一金属层(30)上制作第二金属层(40),第二金属层(40)是用作第一金属层(30)的导电的氧化阻挡层。
Claims (5)
1、一种制作金属-绝缘体-金属电容器结构的方法,包括:
提供半导体衬底(10);
在半导体衬底(10)上制作介质层(20);
在介质层(20)上制作凹槽(205);
在凹槽中制作第一金属层(30),第一金属层包含铜;
对第一金属层(30)制作凹槽;
在第一金属层(30)上制作第二金属层(40),第二金属层(40)是用作第一金属层(30)的导电的氧化阻挡层;
在第二金属层(40)上制作绝缘体(50);以及
在绝缘体(50)上制作第三金属层(60)。
2、权利要求1的方法,其中制作第一金属层(30)还包括:
在所述介质层(20)的表面上沉积所述第一金属层(30);和平整所述第一金属层(30)以制作镶嵌结构。
3、权利要求1的方法,其中制作第二金属层(40)还包括制作所述第二金属层(40),使其具有50到2000埃的厚度。
4、权利要求1的方法,其中制作第二金属层(40)包括:
在所述介质层(20)的表面和所述被制作凹槽的第一金属层(30)上沉积所述第二金属层(40);
去除所述第一金属层(30)中所述凹槽(205)外面的所有所述第二金属层(40),以使所述第二金属层(40)的周边与第一金属层(30)的周边自对准;以及
平整所述第二金属层(40)使其与所述介质层(20)的表面共面。
5、一种制作半导体器件结构的方法,包括:
提供半导体衬底(10);
在半导体衬底(10)上制作第一介质层(20);
在第一介质层内(20)制作凹槽(205);
在凹槽(205)中制作第一金属层(30),第一金属层(30)包含铜;
对第一金属层(30)制作凹槽;以及
在第一金属层(30)上制作第二金属层(40),第二金属层(40)是用作第一金属层(30)的导电的氧化阻挡层。
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US09/942,208 | 2001-08-29 | ||
US09/942,208 US6461914B1 (en) | 2001-08-29 | 2001-08-29 | Process for making a MIM capacitor |
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US (1) | US6461914B1 (zh) |
EP (1) | EP1425793A2 (zh) |
JP (1) | JP4414221B2 (zh) |
KR (1) | KR20040029106A (zh) |
CN (1) | CN1639861A (zh) |
AU (1) | AU2002313756A1 (zh) |
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Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101160655B (zh) * | 2005-04-15 | 2010-05-19 | 国际商业机器公司 | Mim电容器及其制造方法 |
CN101989621B (zh) * | 2009-08-06 | 2012-03-07 | 中芯国际集成电路制造(上海)有限公司 | Mim电容器及其制造方法 |
CN102420104A (zh) * | 2011-06-07 | 2012-04-18 | 上海华力微电子有限公司 | 一种mim(金属-绝缘层-金属)电容制作方法 |
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CN112086441A (zh) * | 2020-08-26 | 2020-12-15 | 中国电子科技集团公司第十三研究所 | 无源器件制备方法及无源器件 |
CN114512337A (zh) * | 2020-11-16 | 2022-05-17 | 株式会社村田制作所 | 无源部件 |
Families Citing this family (110)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7192827B2 (en) * | 2001-01-05 | 2007-03-20 | Micron Technology, Inc. | Methods of forming capacitor structures |
KR100359299B1 (en) * | 2001-03-26 | 2002-11-07 | Samsung Electronics Co Ltd | Semiconductor memory device having resist pattern and method for forming metal contact thereof |
KR100400252B1 (ko) * | 2001-06-29 | 2003-10-01 | 주식회사 하이닉스반도체 | 탄탈륨 옥사이드 캐퍼시터의 형성 방법 |
US8026161B2 (en) | 2001-08-30 | 2011-09-27 | Micron Technology, Inc. | Highly reliable amorphous high-K gate oxide ZrO2 |
US6717193B2 (en) * | 2001-10-09 | 2004-04-06 | Koninklijke Philips Electronics N.V. | Metal-insulator-metal (MIM) capacitor structure and methods of fabricating same |
US6900122B2 (en) | 2001-12-20 | 2005-05-31 | Micron Technology, Inc. | Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics |
US6809026B2 (en) * | 2001-12-21 | 2004-10-26 | Applied Materials, Inc. | Selective deposition of a barrier layer on a metal film |
US6770565B2 (en) * | 2002-01-08 | 2004-08-03 | Applied Materials Inc. | System for planarizing metal conductive layers |
US6767795B2 (en) | 2002-01-17 | 2004-07-27 | Micron Technology, Inc. | Highly reliable amorphous high-k gate dielectric ZrOXNY |
US6893984B2 (en) * | 2002-02-20 | 2005-05-17 | Micron Technology Inc. | Evaporated LaA1O3 films for gate dielectrics |
US7160577B2 (en) | 2002-05-02 | 2007-01-09 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
US7335552B2 (en) * | 2002-05-15 | 2008-02-26 | Raytheon Company | Electrode for thin film capacitor devices |
US6720608B2 (en) * | 2002-05-22 | 2004-04-13 | United Microelectronics Corp. | Metal-insulator-metal capacitor structure |
US7135421B2 (en) | 2002-06-05 | 2006-11-14 | Micron Technology, Inc. | Atomic layer-deposited hafnium aluminum oxide |
KR100456829B1 (ko) * | 2002-06-17 | 2004-11-10 | 삼성전자주식회사 | 듀얼다마신공정에 적합한 엠아이엠 캐패시터 및 그의제조방법 |
US7221586B2 (en) | 2002-07-08 | 2007-05-22 | Micron Technology, Inc. | Memory utilizing oxide nanolaminates |
JP2004063807A (ja) * | 2002-07-29 | 2004-02-26 | Elpida Memory Inc | 半導体装置の製造方法 |
KR100456697B1 (ko) * | 2002-07-30 | 2004-11-10 | 삼성전자주식회사 | 반도체 장치의 캐패시터 및 그 제조방법 |
US20040027783A1 (en) * | 2002-08-08 | 2004-02-12 | United Microelectronics Corp. | Structure of metal-metal capacitor |
US6790791B2 (en) | 2002-08-15 | 2004-09-14 | Micron Technology, Inc. | Lanthanide doped TiOx dielectric films |
US6916722B2 (en) * | 2002-12-02 | 2005-07-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to fabricate high reliable metal capacitor within copper back-end process |
US20040063295A1 (en) * | 2002-09-30 | 2004-04-01 | Intel Corporation | One-mask process flow for simultaneously constructing a capacitor and a thin film resistor |
US7279423B2 (en) * | 2002-10-31 | 2007-10-09 | Intel Corporation | Forming a copper diffusion barrier |
US6709918B1 (en) * | 2002-12-02 | 2004-03-23 | Chartered Semiconductor Manufacturing Ltd. | Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology |
US20040120097A1 (en) * | 2002-12-23 | 2004-06-24 | Chambers Stephen T. | Methods of forming metal-insulator-metal capacitors |
KR100500444B1 (ko) * | 2002-12-26 | 2005-07-12 | 삼성전자주식회사 | 금속전극들을 갖는 커패시터 제조방법 |
KR20040067012A (ko) * | 2003-01-21 | 2004-07-30 | 주식회사 하이닉스반도체 | 반도체 소자의 엠아이엠 캐패시터 형성방법 |
US7192892B2 (en) * | 2003-03-04 | 2007-03-20 | Micron Technology, Inc. | Atomic layer deposited dielectric layers |
KR100539198B1 (ko) * | 2003-03-10 | 2005-12-27 | 삼성전자주식회사 | 금속-절연체-금속 캐패시터 및 그 제조 방법 |
US7239000B2 (en) * | 2003-04-15 | 2007-07-03 | Honeywell International Inc. | Semiconductor device and magneto-resistive sensor integration |
US7206693B2 (en) * | 2003-04-15 | 2007-04-17 | Honeywell International Inc. | Method and apparatus for an integrated GPS receiver and electronic compassing sensor device |
US7265543B2 (en) * | 2003-04-15 | 2007-09-04 | Honeywell International Inc. | Integrated set/reset driver and magneto-resistive sensor |
US7183186B2 (en) | 2003-04-22 | 2007-02-27 | Micro Technology, Inc. | Atomic layer deposited ZrTiO4 films |
US6812110B1 (en) * | 2003-05-09 | 2004-11-02 | Micron Technology, Inc. | Methods of forming capacitor constructions, and methods of forming constructions comprising dielectric materials |
KR100471408B1 (ko) * | 2003-06-30 | 2005-03-14 | 주식회사 하이닉스반도체 | 반도체 소자의 금속선 패터닝 방법 |
JP2005093597A (ja) * | 2003-09-16 | 2005-04-07 | Shinko Electric Ind Co Ltd | 薄膜キャパシタ及びその製造方法 |
US6933191B2 (en) * | 2003-09-18 | 2005-08-23 | International Business Machines Corporation | Two-mask process for metal-insulator-metal capacitors and single mask process for thin film resistors |
DE10344389A1 (de) * | 2003-09-25 | 2005-05-19 | Infineon Technologies Ag | Verfahren zur Herstellung einer multifunktionellen Dielektrikumschicht auf einem Substrat |
KR100548998B1 (ko) * | 2003-09-25 | 2006-02-02 | 삼성전자주식회사 | 동일레벨에 퓨즈와 커패시터를 갖는 반도체소자 및 그것을제조하는 방법 |
US6876028B1 (en) | 2003-09-30 | 2005-04-05 | International Business Machines Corporation | Metal-insulator-metal capacitor and method of fabrication |
WO2005055178A1 (en) * | 2003-12-02 | 2005-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Display device, method for manufacturing the same, and television apparatus |
KR100573897B1 (ko) * | 2003-12-30 | 2006-04-26 | 동부일렉트로닉스 주식회사 | 반도체 제조 방법 |
KR100564801B1 (ko) * | 2003-12-30 | 2006-03-28 | 동부아남반도체 주식회사 | 반도체 제조 방법 |
KR100538444B1 (ko) * | 2003-12-31 | 2005-12-22 | 동부아남반도체 주식회사 | 비아 홀 및 트렌치 형성 방법 |
US7301752B2 (en) * | 2004-06-04 | 2007-11-27 | International Business Machines Corporation | Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask |
US7588988B2 (en) | 2004-08-31 | 2009-09-15 | Micron Technology, Inc. | Method of forming apparatus having oxide films formed using atomic layer deposition |
US7091542B1 (en) * | 2005-01-28 | 2006-08-15 | International Business Machines Corporation | Method of forming a MIM capacitor for Cu BEOL application |
KR100809321B1 (ko) | 2005-02-01 | 2008-03-05 | 삼성전자주식회사 | 다중 mim 캐패시터 및 이의 제조 방법 |
US20060197183A1 (en) * | 2005-03-01 | 2006-09-07 | International Business Machines Corporation | Improved mim capacitor structure and process |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
KR100870178B1 (ko) | 2005-08-10 | 2008-11-25 | 삼성전자주식회사 | 엠아이엠 커패시터를 구비하는 반도체 소자들 및 그제조방법들 |
US8110469B2 (en) | 2005-08-30 | 2012-02-07 | Micron Technology, Inc. | Graded dielectric layers |
US20070080426A1 (en) * | 2005-10-11 | 2007-04-12 | Texas Instruments Incorporated | Single lithography-step planar metal-insulator-metal capacitor and resistor |
US7483258B2 (en) * | 2005-12-13 | 2009-01-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | MIM capacitor in a copper damascene interconnect |
US7420365B2 (en) | 2006-03-15 | 2008-09-02 | Honeywell International Inc. | Single chip MR sensor integrated with an RF transceiver |
US7439127B2 (en) * | 2006-04-20 | 2008-10-21 | Advanced Micro Devices, Inc. | Method for fabricating a semiconductor component including a high capacitance per unit area capacitor |
WO2008010028A1 (en) * | 2006-06-15 | 2008-01-24 | Freescale Semiconductor, Inc. | Mim capacitor integration |
US7582549B2 (en) | 2006-08-25 | 2009-09-01 | Micron Technology, Inc. | Atomic layer deposited barium strontium titanium oxide films |
JP2008171886A (ja) * | 2007-01-09 | 2008-07-24 | Rohm Co Ltd | 半導体装置およびその製造方法 |
US20080174015A1 (en) * | 2007-01-23 | 2008-07-24 | Russell Thomas Herrin | Removal of etching process residual in semiconductor fabrication |
JP5334199B2 (ja) | 2008-01-22 | 2013-11-06 | ルネサスエレクトロニクス株式会社 | 容量素子を有する半導体装置 |
TW200947670A (en) * | 2008-05-13 | 2009-11-16 | Nanya Technology Corp | Method for fabricating a semiconductor capacitor device |
KR101090932B1 (ko) | 2008-12-24 | 2011-12-08 | 매그나칩 반도체 유한회사 | 캐패시터 및 그의 제조방법 |
US8298902B2 (en) * | 2009-03-18 | 2012-10-30 | International Business Machines Corporation | Interconnect structures, methods for fabricating interconnect structures, and design structures for a radiofrequency integrated circuit |
US20110012229A1 (en) * | 2009-07-14 | 2011-01-20 | United Microelectronics Corp. | Semiconductor device with capacitor and method of fabricating the same |
DE102009035438B4 (de) * | 2009-07-31 | 2013-02-07 | Globalfoundries Dresden Module One Llc & Co. Kg | Verwendung von Dielektrika mit großem ε als sehr selektive Ätzstoppmaterialien in Halbleiterbauelementen, sowie Halbleiterbauelemente |
US8363379B2 (en) * | 2010-08-18 | 2013-01-29 | International Business Machines Corporation | Altering capacitance of MIM capacitor having reactive layer therein |
US8405135B2 (en) | 2010-10-05 | 2013-03-26 | International Business Machines Corporation | 3D via capacitor with a floating conductive plate for improved reliability |
US8692608B2 (en) | 2011-09-19 | 2014-04-08 | United Microelectronics Corp. | Charge pump system capable of stabilizing an output voltage |
US9030221B2 (en) | 2011-09-20 | 2015-05-12 | United Microelectronics Corporation | Circuit structure of test-key and test method thereof |
US8395455B1 (en) | 2011-10-14 | 2013-03-12 | United Microelectronics Corp. | Ring oscillator |
US8421509B1 (en) | 2011-10-25 | 2013-04-16 | United Microelectronics Corp. | Charge pump circuit with low clock feed-through |
US8588020B2 (en) | 2011-11-16 | 2013-11-19 | United Microelectronics Corporation | Sense amplifier and method for determining values of voltages on bit-line pair |
US8493806B1 (en) | 2012-01-03 | 2013-07-23 | United Microelectronics Corporation | Sense-amplifier circuit of memory and calibrating method thereof |
US9142607B2 (en) | 2012-02-23 | 2015-09-22 | Freescale Semiconductor, Inc. | Metal-insulator-metal capacitor |
US8970197B2 (en) | 2012-08-03 | 2015-03-03 | United Microelectronics Corporation | Voltage regulating circuit configured to have output voltage thereof modulated digitally |
US8724404B2 (en) | 2012-10-15 | 2014-05-13 | United Microelectronics Corp. | Memory, supply voltage generation circuit, and operation method of a supply voltage generation circuit used for a memory array |
US8669897B1 (en) | 2012-11-05 | 2014-03-11 | United Microelectronics Corp. | Asynchronous successive approximation register analog-to-digital converter and operating method thereof |
US8711598B1 (en) | 2012-11-21 | 2014-04-29 | United Microelectronics Corp. | Memory cell and memory cell array using the same |
US8873295B2 (en) | 2012-11-27 | 2014-10-28 | United Microelectronics Corporation | Memory and operation method thereof |
US8643521B1 (en) | 2012-11-28 | 2014-02-04 | United Microelectronics Corp. | Digital-to-analog converter with greater output resistance |
US9030886B2 (en) | 2012-12-07 | 2015-05-12 | United Microelectronics Corp. | Memory device and driving method thereof |
US8953401B2 (en) | 2012-12-07 | 2015-02-10 | United Microelectronics Corp. | Memory device and method for driving memory array thereof |
US8809149B2 (en) | 2012-12-12 | 2014-08-19 | Globalfoundries Inc. | High density serial capacitor device and methods of making such a capacitor device |
US8917109B2 (en) | 2013-04-03 | 2014-12-23 | United Microelectronics Corporation | Method and device for pulse width estimation |
CN103311181B (zh) * | 2013-06-03 | 2016-02-03 | 上海华力微电子有限公司 | 改善金属层-绝缘介质层-金属层失配参数的方法 |
US9105355B2 (en) | 2013-07-04 | 2015-08-11 | United Microelectronics Corporation | Memory cell array operated with multiple operation voltage |
US8901711B1 (en) | 2013-08-07 | 2014-12-02 | International Business Machines Corporation | Horizontal metal-insulator-metal capacitor |
US8947911B1 (en) | 2013-11-07 | 2015-02-03 | United Microelectronics Corp. | Method and circuit for optimizing bit line power consumption |
US8866536B1 (en) | 2013-11-14 | 2014-10-21 | United Microelectronics Corp. | Process monitoring circuit and method |
US9143143B2 (en) | 2014-01-13 | 2015-09-22 | United Microelectronics Corp. | VCO restart up circuit and method thereof |
US9548266B2 (en) | 2014-08-27 | 2017-01-17 | Nxp Usa, Inc. | Semiconductor package with embedded capacitor and methods of manufacturing same |
US9349787B1 (en) | 2014-12-10 | 2016-05-24 | GlobalFoundries, Inc. | Integrated circuits with capacitors and methods of producing the same |
US9373680B1 (en) | 2015-02-02 | 2016-06-21 | Globalfoundries Inc. | Integrated circuits with capacitors and methods of producing the same |
US9640608B1 (en) | 2016-02-25 | 2017-05-02 | Globalfoundries Inc. | Serial capacitor device with middle electrode contact and methods of making same |
US10090240B2 (en) | 2016-06-03 | 2018-10-02 | Globalfoundries Inc. | Interconnect structure with capacitor element and related methods |
US9875959B2 (en) | 2016-06-09 | 2018-01-23 | International Business Machines Corporation | Forming a stacked capacitor |
US10032711B2 (en) | 2016-07-25 | 2018-07-24 | International Business Machines Corporation | Integrating metal-insulator-metal capacitors with air gap process flow |
US9893144B1 (en) | 2016-08-05 | 2018-02-13 | International Business Machines Corporation | Methods for fabricating metal-insulator-metal capacitors |
US9704856B1 (en) | 2016-09-23 | 2017-07-11 | International Business Machines Corporation | On-chip MIM capacitor |
US9698213B1 (en) | 2016-09-28 | 2017-07-04 | International Business Machines Corporation | Vertical MIM capacitor |
US9876068B1 (en) | 2016-10-31 | 2018-01-23 | International Business Machines Corporation | High-K metal-insulator-metal capacitor and method of manufacturing the same |
US20180138263A1 (en) * | 2016-11-14 | 2018-05-17 | United Microelectronics Corp. | Semiconductor structure and method for forming the same |
US10008558B1 (en) | 2017-01-05 | 2018-06-26 | International Business Machines Corporation | Advanced metal insulator metal capacitor |
US10032855B1 (en) | 2017-01-05 | 2018-07-24 | International Business Machines Corporation | Advanced metal insulator metal capacitor |
US10090378B1 (en) | 2017-03-17 | 2018-10-02 | International Business Machines Corporation | Efficient metal-insulator-metal capacitor |
US10658455B2 (en) * | 2017-09-28 | 2020-05-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal insulator metal capacitor structure having high capacitance |
US11031457B2 (en) | 2017-12-15 | 2021-06-08 | International Business Machines Corporation | Low resistance high capacitance density MIM capacitor |
US10497519B1 (en) | 2018-09-27 | 2019-12-03 | International Business Machines Corporation | Back-end-of-the line capacitor |
CN112447663B (zh) * | 2019-09-03 | 2024-06-21 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5561082A (en) * | 1992-07-31 | 1996-10-01 | Kabushiki Kaisha Toshiba | Method for forming an electrode and/or wiring layer by reducing copper oxide or silver oxide |
JP3326698B2 (ja) * | 1993-03-19 | 2002-09-24 | 富士通株式会社 | 集積回路装置の製造方法 |
US5708559A (en) * | 1995-10-27 | 1998-01-13 | International Business Machines Corporation | Precision analog metal-metal capacitor |
JP3304754B2 (ja) * | 1996-04-11 | 2002-07-22 | 三菱電機株式会社 | 集積回路の多段埋め込み配線構造 |
KR19980070914A (ko) | 1997-01-31 | 1998-10-26 | 윌리엄비.켐플러 | 집적 회로 구조의 제조 방법 |
US6130102A (en) * | 1997-11-03 | 2000-10-10 | Motorola Inc. | Method for forming semiconductor device including a dual inlaid structure |
US6025226A (en) * | 1998-01-15 | 2000-02-15 | International Business Machines Corporation | Method of forming a capacitor and a capacitor formed using the method |
US6090661A (en) * | 1998-03-19 | 2000-07-18 | Lsi Logic Corporation | Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls |
US6107136A (en) * | 1998-08-17 | 2000-08-22 | Motorola Inc. | Method for forming a capacitor structure |
US6255217B1 (en) * | 1999-01-04 | 2001-07-03 | International Business Machines Corporation | Plasma treatment to enhance inorganic dielectric adhesion to copper |
JP2000260963A (ja) * | 1999-03-12 | 2000-09-22 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2000349255A (ja) * | 1999-06-03 | 2000-12-15 | Oki Electric Ind Co Ltd | 半導体記憶装置およびその製造方法 |
EP1081746A2 (en) * | 1999-08-31 | 2001-03-07 | Lucent Technologies Inc. | Metal-oxide-metal structure having a Cu/TaN/Ta2O5 stacked structure incorporated therein |
TW432689B (en) | 1999-10-18 | 2001-05-01 | Taiwan Semiconductor Mfg | Fabricating method of stacked capacitor |
US6114243A (en) * | 1999-11-15 | 2000-09-05 | Chartered Semiconductor Manufacturing Ltd | Method to avoid copper contamination on the sidewall of a via or a dual damascene structure |
US6498364B1 (en) * | 2000-01-21 | 2002-12-24 | Agere Systems Inc. | Capacitor for integration with copper damascene processes |
US6368953B1 (en) * | 2000-05-09 | 2002-04-09 | International Business Machines Corporation | Encapsulated metal structures for semiconductor devices and MIM capacitors including the same |
US6329234B1 (en) * | 2000-07-24 | 2001-12-11 | Taiwan Semiconductor Manufactuirng Company | Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow |
US6313003B1 (en) * | 2000-08-17 | 2001-11-06 | Taiwan Semiconductor Manufacturing Company | Fabrication process for metal-insulator-metal capacitor with low gate resistance |
US6537912B1 (en) * | 2000-08-25 | 2003-03-25 | Micron Technology Inc. | Method of forming an encapsulated conductive pillar |
JP3895126B2 (ja) * | 2001-04-23 | 2007-03-22 | 株式会社東芝 | 半導体装置の製造方法 |
-
2001
- 2001-08-29 US US09/942,208 patent/US6461914B1/en not_active Expired - Fee Related
-
2002
- 2002-08-13 WO PCT/US2002/025909 patent/WO2003021661A2/en active Application Filing
- 2002-08-13 KR KR10-2004-7003000A patent/KR20040029106A/ko not_active Application Discontinuation
- 2002-08-13 JP JP2003525900A patent/JP4414221B2/ja not_active Expired - Fee Related
- 2002-08-13 CN CNA028169336A patent/CN1639861A/zh active Pending
- 2002-08-13 AU AU2002313756A patent/AU2002313756A1/en not_active Abandoned
- 2002-08-13 EP EP02753470A patent/EP1425793A2/en not_active Withdrawn
- 2002-08-27 TW TW091119392A patent/TW558822B/zh not_active IP Right Cessation
Cited By (15)
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CN101160655B (zh) * | 2005-04-15 | 2010-05-19 | 国际商业机器公司 | Mim电容器及其制造方法 |
CN101989621B (zh) * | 2009-08-06 | 2012-03-07 | 中芯国际集成电路制造(上海)有限公司 | Mim电容器及其制造方法 |
CN102420104A (zh) * | 2011-06-07 | 2012-04-18 | 上海华力微电子有限公司 | 一种mim(金属-绝缘层-金属)电容制作方法 |
CN102420104B (zh) * | 2011-06-07 | 2013-12-04 | 上海华力微电子有限公司 | 一种mim(金属-绝缘层-金属)电容制作方法 |
CN102637660A (zh) * | 2012-04-24 | 2012-08-15 | 上海宏力半导体制造有限公司 | 集成无源器件、mim电容、极板及极板的形成方法 |
CN103872009B (zh) * | 2012-12-12 | 2018-10-12 | 恩智浦美国有限公司 | 包括集成无源器件的集成电路及其制造方法 |
CN103872009A (zh) * | 2012-12-12 | 2014-06-18 | 飞思卡尔半导体公司 | 包括集成无源器件的集成电路及其制造方法 |
CN109585425A (zh) * | 2017-09-28 | 2019-04-05 | 台湾积体电路制造股份有限公司 | 半导体结构及其制造方法 |
CN109585425B (zh) * | 2017-09-28 | 2022-01-07 | 台湾积体电路制造股份有限公司 | 半导体结构及其制造方法 |
US12068364B2 (en) | 2017-09-28 | 2024-08-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal insulator metal capacitor structure having high capacitance |
CN109817607A (zh) * | 2017-11-21 | 2019-05-28 | 台湾积体电路制造股份有限公司 | 具有电容器的半导体器件的结构和形成方法 |
CN109037445A (zh) * | 2018-08-01 | 2018-12-18 | 德淮半导体有限公司 | Mim电容器及其制造方法 |
CN112086441A (zh) * | 2020-08-26 | 2020-12-15 | 中国电子科技集团公司第十三研究所 | 无源器件制备方法及无源器件 |
CN114512337A (zh) * | 2020-11-16 | 2022-05-17 | 株式会社村田制作所 | 无源部件 |
CN114512337B (zh) * | 2020-11-16 | 2024-08-27 | 株式会社村田制作所 | 无源部件 |
Also Published As
Publication number | Publication date |
---|---|
WO2003021661A3 (en) | 2003-07-24 |
JP4414221B2 (ja) | 2010-02-10 |
WO2003021661A2 (en) | 2003-03-13 |
TW558822B (en) | 2003-10-21 |
WO2003021661B1 (en) | 2003-09-12 |
US6461914B1 (en) | 2002-10-08 |
EP1425793A2 (en) | 2004-06-09 |
JP2005526378A (ja) | 2005-09-02 |
AU2002313756A1 (en) | 2003-03-18 |
KR20040029106A (ko) | 2004-04-03 |
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