CN1555573A - 具有集成的散热片和增加层的微电子封装件 - Google Patents

具有集成的散热片和增加层的微电子封装件 Download PDF

Info

Publication number
CN1555573A
CN1555573A CNA018202551A CN01820255A CN1555573A CN 1555573 A CN1555573 A CN 1555573A CN A018202551 A CNA018202551 A CN A018202551A CN 01820255 A CN01820255 A CN 01820255A CN 1555573 A CN1555573 A CN 1555573A
Authority
CN
China
Prior art keywords
core
microelectronic
encapsulating material
conductive traces
microelectronics packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA018202551A
Other languages
English (en)
Inventor
M��V����
M·V·赫瑙
X·C·穆
Q·马
Q·T·吴
S·N·托勒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1555573A publication Critical patent/CN1555573A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种微电子封装件制造方法，包括将至少一个微电子管芯连附到一散热器并将所述微电子管芯/多个管芯封装于其上，还可以包括使微电子封装芯靠接该散热器，其中微电子管芯/多个管芯处于所述微电子封装芯内的至少一个开口中。在封装后，可以制造多个增加层以形成与所述微电子管芯/多个管芯相连的电连接。

Description

具有集成的散热片和增加层的微电子封装件
发明背景
发明领域
本发明涉及用于制造微电子封装件的设备和方法。更具体说，本发明涉及将至少一个微电子管芯连接到散热器以及将微电子管芯封装到其上的制造方法。
背景技术
集成电路元件的高性能、低成本和不断小型化以及集成电路的较大集成密度是计算机产业的发展目标。随着这些目标的实现，微电子管芯变得更小。当然，更大封装密度的目标需要整个微电子管芯封装件等于或略微大于(约10％至30％)微电子管芯本身的尺寸。这样的微电子管芯封装被称为“芯片尺寸封装”或“CSP”。
如图27所示，实际的CSP涉及直接在微电子管芯202的有效表面204上制造增加层。增加层可以包括设于微电子管芯有效表面204上的介电层206。可以在所述介电层206上形成导电轨迹208，其中每个导电轨迹208的一部分与所述有效表面上的至少一个触点212接触。用于与外部元件(未示出)接触的外部触点例如焊料球或导电引线可以制造成与至少一个导电轨迹208电接触。图27示出了被介电层上的焊料掩模材料216包围的外部触点例如焊料球214。但在这种实际的CSP中，由微电子管芯有效表面204提供的表面积一般不能给某些类型的微电子管芯(如逻辑类型的)提供足够的用于与外部元件(未示出)接触所需的全部外部触点的表面。
另外的表面可以通过使用内插器例如衬底(基本是刚性的材料)或挠性元件(基本是挠性的材料)。图28示出了具有通过小焊料球228连接到衬底内插器222的第一表面226并与之电接触的微电子管芯224的衬底内插器222。小焊料球228在微电子管芯224上的触点232与衬底内插器第一表面226上的导电轨迹234之间延伸。导电轨迹234与衬底内插器222的第二表面238上的焊盘236通过通路242分立地电连接，所述通路242延伸通过衬底内插器222。外部触点244(以焊料球示出)形成于焊盘236上。外部触点244用于实现微电子管芯224与外部电系统(未示出)之间的电连通。
衬底内插器222需要数个加工步骤。这些加工步骤使封装件的成本增加。另外，即使采用小焊料球228仍然存在拥挤问题，该问题会导致小焊料球228之间的短路并会使为防止沾污和提供机械稳定性而在微电子管芯224和衬底内插器222之间嵌入底层填料存在困难。此外，电路封装件也许不能满足由衬底内插器222的厚度带来的对未来的微电子管芯224的功率传输需要，因为衬底内插器引起焊接区侧(land side)电容器具有过高的电感。
图29示出了挠性元件内插器252，其中微电子管芯256的有效表面254被连接到带有一层粘接剂262的挠性元件内插器252的第一表面258。微电子管芯256被封装在封装材料264中。在挠性元件内插器252中通过激光烧蚀形成有穿过挠性元件内插器252到达微电子管芯有效表面254上的触点266以及到达处于挠性元件内插器252内的选定金属衬垫的多个开口。导电材料层形成于挠性元件内插器252的第二表面272上和所述开口内。导电材料层被通过标准的光掩模/蚀刻工艺图形化成以形成导电通路274和导电轨迹276。外部触点形成于导电轨迹276上(图中以被导电轨迹276附近的焊料掩模材料282包围的焊料球248表示)。
使用挠性元件内插器252需要粘接形成挠性元件内插器252的材料层，并需要将挠性元件内插器252粘接到微电子管芯256上。这些粘接处理比较困难且会增加封装成本。另外，还发现所得到的封装的可靠性差。
因此，开发能够克服上述问题的用来提供额外的表面积的新设备和技术是有利的，所述表面积用于形成CSP应用中使用的轨迹。
附图简要说明
尽管权利要求书对本说明书进行总结，特别指出并清除地要求了有关本发明的有关内容，但本发明的优点可以从下面结合附图对本发明进行的描述中更清除地了解，其中：
图1-4是侧剖面图，示出了根据本发明形成微电子结构的方法中的步骤；
图5-11是侧剖面图，示出了根据本发明制造另一微电子结构的实施例；
图12-19是侧剖面图，示出了根据本发明在微电子结构上制造增加层的方法；
图20和21是侧剖面图，示出了根据本发明制造另一微电子结构的实施例；
图22和23是侧剖面图，示出了根据本发明具有微电子封装芯的微电子封装件；
图24是侧剖面图，示出了根据本发明的多芯片模块；
图25和26是侧剖面图，示出了根据本发明不具有微电子封装芯的微电子封装件；
图27是侧剖面图，示出了现有技术的微电子器件的实际CSP；
图28是侧剖面图，示出了现有技术的利用衬底内插器的微电子器件的CSP；
图29是侧剖面图，示出了现有技术的利用挠性元件内插器的微电子器件的CSP。
具体实施例的详细说明
在下面的详细说明中，将参照以示例方式示出本发明的具体实施例的附图。这些实施例描述的足够详细，以使本领域技术人员可以实施本发明。应知道，本发明的各实施例虽然不同，但不一定是相互排斥的。例如，结合一个实施例说明的具体特征、结构、或特性可以在其它实施例中实施，而不脱离本发明的精神和范围。另外，应理解的是，每个公开的实施例中的单独元件的位置和布置可以被改变，而不脱离本发明的精神和范围。因而下面的详细说明不是限制性的，本发明的范围仅由所附的权利要求书限定，权利要求书应解释为包括与权利要求书所要求的内容等效的全部范围。所有附图中，相似的标号表示相同或相似的功能。
本发明包括将至少一个微电子管芯连附到散热器上并将微电子管芯/多个管芯封装到其上的微电子封装制造技术。本发明还可以包括靠接着散热器的微电子封装芯，其中微电子管芯/多个管芯处于微电子封装芯内的至少一个开口内，并且封装材料将微电子管芯/多个管芯固定到所述开口内。在封装之后，可以制造增加层以形成与微电子管芯/多个管芯相连的电连接。
图1-4示出了用于制造微电子结构的方法中的步骤。如图1所示，提供大致平的散热片102。该散热片102最好包括高导热性材料，其可以包括但不限于金属，如铜、铜合金、钼、钼合金、铝、铝合金等。用于制造散热器102的材料可以包括但不限于导热性陶瓷材料，如AlSiC、AlN等。还应理解的是，散热器102可以是更复杂的器件，例如热管或散热片内的多个小热管。
如图2所示，一层粘接层104(最好是导热性的)被图形化在散热片102上。粘接层104可以包括填充有导热颗粒材料(例如银或氮化率)的树脂或环氧树脂材料。粘接层104也可以包括具有低熔化温度的金属或金属合金(如焊料材料等)。
至少一个微电子管芯106的背面110被设于粘接层104上以将其连附到散热片102上，如图3所示。最好，粘接层104被图形化成与微电子管芯106的尺寸大致相同。微电子管芯106可以是任何已知的有源或无源微电子器件，包括但不限于逻辑电路(CPU)、存储器(DRAM、SRAM、SDRAM等)、控制器(芯片组)、电容器、电阻器、电感器等。所述微电子管芯106最好被以电方式或其它方式测试过，以在使用前淘汰不能工作的管芯。
如图4所示，在微电子管芯106和散热器102上淀积介电封装材料108，例如塑料、树脂、环氧树脂、弹性的(如橡胶)等材料)。介电封装材料108应选择为具有足够粘性的，以进行填充和形成大致平的上表面120。
图5-11示出了至少另一微电子结构的实施例。如图5所示，提供大致平的散热片102。如图6所示，一层粘接层104(最好是导热性的)被图形化在散热片102上。至少一个微电子管芯106的背面110被放置在粘接层104上以将其连附到散热片102上，如图7所示。
图8-9示出了用于制造本实施例的微电子器件的微电子封装芯112。在微电子封装芯112最好包括大致平的材料。用于制造微电子封装芯112的材料包括但不限于基于双马来酰亚胺三嗪树脂(BT)的层压材料、FR4(阻燃玻璃/环氧树脂)层压材料、各种聚酰亚胺材料、陶瓷材料等，以及金属材料(例如铜)等。微电子封装芯112具有至少一个从微电子封装芯112的第一表面116延伸到微电子封装芯112的相对的第二表面118的开口114。如图9所示，开口114可以具有任何形状和尺寸，包括但不限于矩形/方形114a、具有圆角的矩形/方形114b、圆形114c。对开口114的尺寸和形状唯一限制是它们必须具有用于将微电子管芯或多个管芯容纳于其中的适当的尺寸和形状，下面将会对此进行说明。
如图10所示，微电子封装芯的第二表面118被设置在散热器102上。开口114定位成使微电子管芯处于其中。然后将介电封装材料108淀积到微电子管芯106上(覆盖其有效表面124)、微电子封装芯112上(覆盖其第一表面116)以及开口114内未被微电子管芯106占据的部分中，如图11所示。介电封装材料108将微电子管芯106固定到微电子封装芯112内并提供用于后来形成增加层的有效表面。
图12示出了用介电封装材料108封装在微电子封装芯112内的单个微电子管芯106的视图。微电子管芯106当然包括多个设于其有效表面124上的电触点122。电触点122电连接至微电子管芯106内的电路(未示出)。为了简洁和清除，图中只示出了4个电触点122。
如图13所示，然后穿过覆盖微电子管芯有效表面124的介电封装材料108形成多个通路126。多个通路126最好是通过激光穿孔形成的，但也可以通过现有技术中任何已知的方法形成，包括但不限于光刻。
在介电封装材料上表面120上形成多个导电轨迹128，如图14所示，其中多个导电轨迹128中每个的一部分延伸到所述多个通路126(见图13)中的至少一个内，以与所述电触点电接触。所述多个导电轨迹可以由任何可以使用的导电材料(例如铜、铝及其合金等)制成。
多个导电轨迹128可以利用任何已知技术制成，包括但不限于半附加镀覆和光刻技术。半附加镀覆技术可以包括淀积一籽层，例如在介电封装材料108上溅射淀积或化学镀覆金属。然后将一抗蚀剂层图形化在所述籽层上，之后在由已图形化的抗蚀剂层内的开口区域所暴露的籽层上电解镀覆一层金属(例如铜)。被图形化的抗蚀剂层被剥离，并将其上没有镀覆金属层的籽层部分蚀刻掉。形成多个导电轨迹128的其它方法对于本领域技术人员来说也是显而易见的。
如图15所示，在多个导电轨迹128和介电封装材料108上淀积一介电层132，例如环氧树脂、聚酰亚胺、二苯并环丁烯等。介电层132的形成可以通过任何已知方法实现，包括但不限于薄膜层压、旋涂、辊涂和喷涂淀积等。本发明的介电层最好是有可从Ibiden U.S.A.Corp.，Santa Clara，California，U.S.A.和AjinomotoU.S.A.，Inc.，Paramus，New Jersey，U.S.A.获得的环氧树脂填充。
如图16所示，然后穿过介电层132形成多个第二通路134。所述多个通路134最好是利用激光钻孔形成，但是可由本领域已知的任何方法形成。
如果所述多个导电轨迹128不能将多个第二通路134设置在适当的位置，或者如果布线受到限制，使得关键的电性能要求(例如功率输送、阻抗控制和串扰最小化等)不能得到满足，就需要在所述多个第二通路134内和介电层132上形成其它部分的导电轨迹，然后如图14-16所示那样在其上形成另外一个介电层，再在该另外一个介电层内形成另外的多个通路。介电层的设置和导电轨迹的形成可以重复进行，直到通路处于适当的位置并满足了电性能要求。因而，单个导电轨迹的各部分是由多个部分形成的并可处于不同的介电层上。
可以形成第二多个导电轨迹136，其中第二多个导电轨迹136中每个的一部分延伸到所述第二多个通路132中的至少一个内。第二多个导电轨迹136中每个包括一接合垫138(由虚线140划分出的轨迹上的加大的区域)，如图17所示。
一旦形成了所述第二多个导电轨迹136和接合垫138，它们就可用于形成导电互连件，例如焊料块、焊料球、引线等，用于与外部元件(未示出)连通。例如，焊料掩模材料142可设于第二介电层132、第二多个导电轨迹136以及接合垫138上，如图18所示。然后在焊料掩模材料142中形成多个通路，以暴露出每个接合垫138的至少一部分。通过丝网印刷焊料糊然后进行回流工艺或通过已知的镀覆技术等在每个接合垫138的暴露部分上可以形成多个导电块144(例如，焊料块)，如图19所示。当然应该知道，图12-19所示的增加层制造技术可以用于图4所示的微电子结构。
图20和21示出了本发明的另一实施例。如图20所示，微电子封装芯112比微电子管芯106略厚，并使介电封装材料108设于微电子管芯106、微电子封装芯112上以及开口114(见图10)内未被微电子管芯106占据的部分中。例如，封装芯112可以是约800μm厚，而微电子管芯可以是725μm到775μm厚(300mm晶片的厚度)·介电封装材料108的上部被利用例如蚀刻、研磨或化学机械平整等工艺除去，这些工艺停止于微电子封装芯112上。这样提供了在整个微电子管芯表面124上提供大致均匀厚度的介电封装材料108。之后的制造步骤与结合图13-18示出和描述的方式相同。
图22示出了利用介电封装材料108封装在微电子封装芯112内的多个微电子管芯106。然后可以沿着线146(切割)通过任何介电层和轨迹(共同表示为增加层148)和微电子封装芯112可将单个微电子管芯106分开以形成至少一个分成单个的微电子管芯封装件150，如图23所示。当然，应当知道，多个微电子管芯106不需分成被单个的，而是可以作为多芯片模块。而且，微电子管芯106不需具有相同的功能或尺寸相同。另外，应知道，尺寸和功能不同的多个微电子管芯106可以用介电封装材料108封装在微电子封装芯112的一个开口内，以形成多芯片模块152，如图24所示。
当然，如图1-4所示，微电子封装芯112是任选的。因而，微电子管芯106可以简单地被封装在介电封装材料108内，如图25所示。然后沿着线154(切割)通过增加层148和介电封装材料108来将分开单个的微电子管芯106，以形成至少一个分成单个的微电子管芯封装件156，如图26所示。
已经对本发明的实施例进行了详细说明，但应知道，本发明是由所附权利要求书限定的，不限于上述说明中列出的具体细节，不脱离本发明的精神和范围可以对本发明最出很多显而易见的改变。

Claims (28)

1.一种微电子封装件，包括：
一散热片；
至少一个微电子管芯，其具有一有效表面和一背面，所述至少一个微电子管芯背面邻接所述散热片；
设于所述散热片和所述微电子管芯有效表面上的封装材料。
2.如权利要求1所述的微电子封装件，还包括设于所述封装材料的上表面上的增加层。
3.如权利要求2所述的微电子封装件，其中所述增加层包括设于所述封装材料上表面上的至少一个导电轨迹，所述至少一个导电轨迹的一部分延伸穿过所述封装材料从而与所述至少一个微电子管芯有效表面接触。
4.如权利要求3所述的微电子封装件，其中所述增加层还包括设于封装材料上表面的至少一部分和所述至少一个导电轨迹上的至少一个介电层，和延伸穿过所述至少一个介电层从而与所述至少一个导电轨迹接触的至少一个第二导电轨迹。
5.如权利要求1所述的微电子封装件，还包括设于所述至少一个微电子管芯和所述散热片之间的导热粘接层。
6.一种制造微电子封装件的方法，包括：
提供一散热片；
将至少一个微电子管芯的背面邻接所述散热片设置；
将封装材料设于所述至少一个微电子管芯和所述散热片上。
7.如权利要求6所述的方法，还包括在所述封装材料的上表面上形成一增加层。
8.如权利要求7所述的方法，其中形成所述增加层包括形成至少一个从所述封装材料上表面到所述至少一个微电子管芯有效表面的至少一个通路，并在所述封装材料上表面上设置至少一个导电轨迹，其中所述至少一个导电轨迹的一部分延伸穿过所述至少一个通路从而与所述至少一个微电子管芯有效表面接触。
9.如权利要求8所述的方法，还包括在封装材料上表面的至少一部分和所述至少一个导电轨迹上设置至少一个介电层，形成穿过所述介电层的通路，以及在所述介电层上形成至少一个第二导电轨迹，其中所述第二导电轨迹的一部分延伸穿过所述至少一个介电层从而与所述至少一个导电轨迹接触。
10.一种微电子封装件，包括：
一散热片；
一微电子封装芯，其具有一第一表面和相反的第二表面，所述微电子管芯具有至少一个设于其中的从所述微电子封装芯第一表面延伸到所述微电子封装芯第二表面的开口，其中所述微电子封装芯第二表面靠接所述散热片；
在所述至少一个微电子封装芯开口内并邻接所述散热片设置的至少一个微电子管芯，所述至少一个微电子管芯具有一有效表面；
在所述微电子管芯上和至少一个微电子封装芯开口的一部分内设置的封装材料。
11.如权利要求10所述的微电子封装件，还包括设于所述封装材料的上表面上的增加层。
12.如权利要求11所述的微电子封装件，其中所述增加层包括设于所述封装材料上表面上的至少一个导电轨迹，其中所述至少一个导电轨迹的一部分延伸穿过所述封装材料从而与所述至少一个微电子管芯有效表面接触。
13.如权利要求12所述的微电子封装件，其中所述增加层还包括设于封装材料上表面的至少一部分和所述至少一个导电轨迹上的至少一个介电层。
14.如权利要求11所述的微电子封装件，其中所述封装材料覆盖所述微电子封装芯第一表面。
15.如权利要求10所述的微电子封装件，其中所述微电子封装芯的厚度大于所述至少一个微电子管芯的厚度。
16.如权利要求10所述的微电子封装件，其中所述微电子封装芯是从这样的组中选择的材料，该组包括：基于双马来酰亚胺三嗪树脂的材料、阻燃玻璃/环氧树脂材料、聚酰亚胺、陶瓷和金属。
17.如权利要求10所述的微电子封装件，还包括设于所述至少一个微电子管芯和所述散热片上的导热粘接层。
18.一种制造微电子封装件的方法，包括：
提供一散热片；
将至少一个微电子管芯的背面邻接所述散热片设置；
将一微电子封装芯靠接所述散热片，所述微电子封装芯具有至少一个设于其中的从所述微电子封装芯第一表面延伸到所述微电子封装芯第二表面的开口，所述至少一个微电子管芯处于所述至少一个微电子封装芯开口内；
在所述至少一个微电子管芯上和所述至少一个微电子封装芯开口的一部分内封装材料。
19.如权利要求18所述的方法，还包括在所述封装材料的上表面上形成一增加层。
20.如权利要求19所述的方法，其中形成所述增加层包括形成至少一个从所述封装材料上表面到所述至少一个微电子管芯有效表面的通路，并在所述封装材料上设置至少一个导电轨迹，其中所述至少一个导电轨迹的一部分延伸穿过所述至少一个通路从而与所述微电子管芯有效表面接触。
21.如权利要求20所述的方法，还包括在封装材料上表面的至少一部分和所述至少一个导电轨迹上设置至少一个介电层，形成穿过所述介电层的通路，以及在所述介电层上形成至少一个第二导电轨迹，其中所述第二导电轨迹的一部分延伸穿过所述至少一个介电层从而与所述至少一个导电轨迹接触。
22.如权利要求18所述的方法，其中在所述至少一个微电子管芯上和至少一个微电子封装芯开口的一部分内设置所述封装材料包括：将所述封装材料设于所述至少一个微电子管芯上，至少一个微电子封装芯开口的一部分内，以及所述微电子封装芯第一表面上。
23.如权利要求22所述的方法，其中将微电子封装芯靠接所述散热片包括：将比所述至少一个微电子管芯厚的微电子封装芯靠接所述散热片。
24.如权利要求23所述的方法，其中将所述封装材料设置在所述至少一个微电子管芯上和至少一个微电子封装芯开口的一部分内包括：将所述封装材料设置在所述至少一个微电子管芯上，至少一个微电子封装芯开口的一部分内，以及所述微电子封装芯第一表面上。
25.如权利要求24所述的方法，还包括去除所述微电子封装芯上的所述封装材料的一部分，从而在所述至少一个微电子管芯上形成均匀厚度的封装材料。
26.如权利要求25所述的方法，还包括在所述封装材料的上表面上形成一增加层。
27.如权利要求26所述的方法，其中形成所述增加层包括形成至少一个从所述封装材料上表面到所述至少一个微电子管芯有效表面的通路，并且在所述封装材料上表面上设置至少一个导电轨迹，其中所述至少一个导电轨迹的一部分延伸穿过所述至少一个通路从而与所述微电子管芯有效表面接触。
28.如权利要求27所述的方法，还包括在封装材料上表面的至少一部分和所述至少一个导电轨迹上设置至少一个介电层，形成穿过所述介电层的通路，以及在所述介电层上形成至少一个第二导电轨迹，其中所述第二导电轨迹的一部分延伸穿过所述至少一个介电层从而与所述至少一个导电轨迹接触。
CNA018202551A 2000-12-08 2001-11-09 具有集成的散热片和增加层的微电子封装件 Pending CN1555573A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/733,289 2000-12-08
US09/733,289 US20020070443A1 (en) 2000-12-08 2000-12-08 Microelectronic package having an integrated heat sink and build-up layers

Publications (1)

Publication Number Publication Date
CN1555573A true CN1555573A (zh) 2004-12-15

Family

ID=24946996

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA018202551A Pending CN1555573A (zh) 2000-12-08 2001-11-09 具有集成的散热片和增加层的微电子封装件

Country Status (7)

Country Link
US (1) US20020070443A1 (zh)
EP (1) EP1354354A2 (zh)
JP (1) JP2005506678A (zh)
KR (1) KR20040014432A (zh)
CN (1) CN1555573A (zh)
AU (1) AU2002232747A1 (zh)
WO (1) WO2002047162A2 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102687255A (zh) * 2010-02-03 2012-09-19 马维尔国际贸易有限公司 凹陷半导体衬底
CN102738073A (zh) * 2012-05-24 2012-10-17 日月光半导体制造股份有限公司 间隔件及其制造方法
CN103201833A (zh) * 2010-11-05 2013-07-10 英特尔公司 密封管芯、包含该密封管芯的微电子封装以及制造所述微电子封装的方法
CN105164798A (zh) * 2013-03-13 2015-12-16 施韦策电子公司 电子组件和制造电子组件的方法
CN109637934A (zh) * 2014-10-11 2019-04-16 意法半导体有限公司 电子器件及制造电子器件的方法

Families Citing this family (149)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6890829B2 (en) * 2000-10-24 2005-05-10 Intel Corporation Fabrication of on-package and on-chip structure using build-up layer process
US6706553B2 (en) * 2001-03-26 2004-03-16 Intel Corporation Dispensing process for fabrication of microelectronic packages
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US6888240B2 (en) * 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US7183658B2 (en) * 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TW517361B (en) * 2001-12-31 2003-01-11 Megic Corp Chip package structure and its manufacture process
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
US6964881B2 (en) * 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP3813945B2 (ja) * 2003-05-07 2006-08-23 任天堂株式会社 ゲーム装置およびゲームプログラム
TWI286372B (en) * 2003-08-13 2007-09-01 Phoenix Prec Technology Corp Semiconductor package substrate with protective metal layer on pads formed thereon and method for fabricating the same
CN100418211C (zh) * 2003-12-25 2008-09-10 卡西欧计算机株式会社 半导体器件及其制造方法
US7489032B2 (en) * 2003-12-25 2009-02-10 Casio Computer Co., Ltd. Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same
CN1316611C (zh) * 2004-03-19 2007-05-16 矽品精密工业股份有限公司 具有增层结构的晶圆级半导体封装件及其制法
TWI245350B (en) * 2004-03-25 2005-12-11 Siliconware Precision Industries Co Ltd Wafer level semiconductor package with build-up layer
CN1316604C (zh) * 2004-03-31 2007-05-16 矽品精密工业股份有限公司 具有增层结构的半导体封装件及其制法
US20060051912A1 (en) * 2004-09-09 2006-03-09 Ati Technologies Inc. Method and apparatus for a stacked die configuration
US7468545B2 (en) * 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
JP4533248B2 (ja) * 2005-06-03 2010-09-01 新光電気工業株式会社 電子装置
US7582556B2 (en) * 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
TWI293202B (en) * 2005-11-23 2008-02-01 Phoenix Prec Technology Corp Carrier board structure with semiconductor component embedded therein
US20080099910A1 (en) * 2006-08-31 2008-05-01 Ati Technologies Inc. Flip-Chip Semiconductor Package with Encapsulant Retaining Structure and Strip
US20080054490A1 (en) 2006-08-31 2008-03-06 Ati Technologies Inc. Flip-Chip Ball Grid Array Strip and Package
US7911044B2 (en) * 2006-12-29 2011-03-22 Advanced Chip Engineering Technology Inc. RF module package for releasing stress
US8106496B2 (en) * 2007-06-04 2012-01-31 Stats Chippac, Inc. Semiconductor packaging system with stacking and method of manufacturing thereof
TW200900628A (en) * 2007-06-28 2009-01-01 Wen-Chin Shiau Manufacturing method of heat-dissipating structure of high-power LED lamp seat and product thereof
US8217511B2 (en) * 2007-07-31 2012-07-10 Freescale Semiconductor, Inc. Redistributed chip packaging with thermal contact to device backside
JP2010535427A (ja) * 2007-07-31 2010-11-18 テッセラ，インコーポレイテッド 貫通シリコンビアを使用する半導体実装プロセス
US20090051019A1 (en) * 2007-08-20 2009-02-26 Chih-Feng Huang Multi-chip module package
US20090072382A1 (en) * 2007-09-18 2009-03-19 Guzek John S Microelectronic package and method of forming same
US9941245B2 (en) * 2007-09-25 2018-04-10 Intel Corporation Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
US9123614B2 (en) 2008-10-07 2015-09-01 Mc10, Inc. Methods and applications of non-planar imaging arrays
US8389862B2 (en) 2008-10-07 2013-03-05 Mc10, Inc. Extremely stretchable electronics
US8097926B2 (en) 2008-10-07 2012-01-17 Mc10, Inc. Systems, methods, and devices having stretchable integrated circuitry for sensing and delivering therapy
JP4833307B2 (ja) * 2009-02-24 2011-12-07 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体モジュール、端子板、端子板の製造方法および半導体モジュールの製造方法
KR101170878B1 (ko) * 2009-06-29 2012-08-02 삼성전기주식회사 반도체 칩 패키지 및 그의 제조방법
KR101058621B1 (ko) * 2009-07-23 2011-08-22 삼성전기주식회사 반도체 패키지 및 이의 제조 방법
US8003496B2 (en) 2009-08-14 2011-08-23 Stats Chippac, Ltd. Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die
US20110156240A1 (en) * 2009-12-31 2011-06-30 Stmicroelectronics Asia Pacific Pte. Ltd. Reliable large die fan-out wafer level package and method of manufacture
US8502394B2 (en) * 2009-12-31 2013-08-06 Stmicroelectronics Pte Ltd. Multi-stacked semiconductor dice scale package structure and method of manufacturing same
US8884422B2 (en) 2009-12-31 2014-11-11 Stmicroelectronics Pte Ltd. Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture
US8436255B2 (en) * 2009-12-31 2013-05-07 Stmicroelectronics Pte Ltd. Fan-out wafer level package with polymeric layer for high reliability
US8466997B2 (en) * 2009-12-31 2013-06-18 Stmicroelectronics Pte Ltd. Fan-out wafer level package for an optical sensor and method of manufacture thereof
JP5610422B2 (ja) * 2010-02-04 2014-10-22 富士通株式会社 半導体装置及び半導体装置の製造方法
KR101110345B1 (ko) * 2010-03-31 2012-02-15 한상일 조명기구용 착탈식 커버부재
US8455300B2 (en) 2010-05-25 2013-06-04 Stats Chippac Ltd. Integrated circuit package system with embedded die superstructure and method of manufacture thereof
JP5636265B2 (ja) * 2010-11-15 2014-12-03 新光電気工業株式会社 半導体パッケージ及びその製造方法
US9013037B2 (en) 2011-09-14 2015-04-21 Stmicroelectronics Pte Ltd. Semiconductor package with improved pillar bump process and structure
US9679863B2 (en) * 2011-09-23 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect substrate for FO-WLCSP
US8779601B2 (en) 2011-11-02 2014-07-15 Stmicroelectronics Pte Ltd Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US8916481B2 (en) 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US9136236B2 (en) 2012-09-28 2015-09-15 Intel Corporation Localized high density substrate routing
US8912670B2 (en) 2012-09-28 2014-12-16 Intel Corporation Bumpless build-up layer package including an integrated heat spreader
US9171794B2 (en) * 2012-10-09 2015-10-27 Mc10, Inc. Embedding thin chips in polymer
US9082025B2 (en) 2012-10-09 2015-07-14 Mc10, Inc. Conformal electronics integrated with apparel
US9190380B2 (en) 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US9583414B2 (en) 2013-10-31 2017-02-28 Qorvo Us, Inc. Silicon-on-plastic semiconductor device and method of making the same
US9706647B2 (en) 2013-05-14 2017-07-11 Mc10, Inc. Conformal electronics including nested serpentine interconnects
WO2015026344A1 (en) * 2013-08-21 2015-02-26 Intel Corporation Bumpless die-package interface for bumpless build-up layer (bbul)
US9159690B2 (en) 2013-09-25 2015-10-13 Intel Corporation Tall solders for through-mold interconnect
US9349703B2 (en) 2013-09-25 2016-05-24 Intel Corporation Method for making high density substrate interconnect using inkjet printing
CA2930740A1 (en) 2013-11-22 2015-05-28 Mc10, Inc. Conformal sensor systems for sensing and analysis of cardiac activity
US9627352B2 (en) * 2014-05-12 2017-04-18 Skyworks Solutions, Inc. Devices and methods for processing singulated radio-frequency units
TWI543320B (zh) * 2014-08-29 2016-07-21 矽品精密工業股份有限公司 半導體封裝件及其製法
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
USD781270S1 (en) 2014-10-15 2017-03-14 Mc10, Inc. Electronic device having antenna
US10121718B2 (en) 2014-11-03 2018-11-06 Qorvo Us, Inc. Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
KR101647559B1 (ko) * 2014-11-07 2016-08-10 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 제조 방법 및 반도체 패키지
US20160172313A1 (en) * 2014-12-16 2016-06-16 Nantong Fujitsu Microelectronics Co., Ltd. Substrate with a supporting plate and fabrication method thereof
WO2016134306A1 (en) 2015-02-20 2016-08-25 Mc10, Inc. Automated detection and configuration of wearable devices based on on-body status, location, and/or orientation
US9613831B2 (en) 2015-03-25 2017-04-04 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
US9819144B2 (en) 2015-05-14 2017-11-14 Apple Inc. High-efficiency vertical emitters with improved heat sinking
US10034375B2 (en) 2015-05-21 2018-07-24 Apple Inc. Circuit substrate with embedded heat sink
US20160343604A1 (en) 2015-05-22 2016-11-24 Rf Micro Devices, Inc. Substrate structure with embedded layer for post-processing silicon handle elimination
US9553036B1 (en) * 2015-07-09 2017-01-24 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
US9735539B2 (en) 2015-07-20 2017-08-15 Apple Inc. VCSEL structure with embedded heat sink
CN105023900A (zh) * 2015-08-11 2015-11-04 华天科技（昆山）电子有限公司 埋入硅基板扇出型封装结构及其制造方法
US10620300B2 (en) 2015-08-20 2020-04-14 Apple Inc. SPAD array with gated histogram construction
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
US9997551B2 (en) 2015-12-20 2018-06-12 Apple Inc. Spad array with pixel-level bias control
US10324171B2 (en) 2015-12-20 2019-06-18 Apple Inc. Light detection and ranging sensor
US10020405B2 (en) 2016-01-19 2018-07-10 Qorvo Us, Inc. Microelectronics package with integrated sensors
EP3206229B1 (en) 2016-02-09 2020-10-07 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Methods of manufacturing flexible electronic devices
CN115175014A (zh) 2016-02-22 2022-10-11 美谛达解决方案公司 贴身传感器系统
EP3420733A4 (en) 2016-02-22 2019-06-26 Mc10, Inc. SYSTEM, DEVICE AND METHOD FOR ACQUIRING ON THE BODY OF SENSOR AND CONCENTRATOR NODE COUPLED WITH SENSOR INFORMATION
WO2017184705A1 (en) 2016-04-19 2017-10-26 Mc10, Inc. Method and system for measuring perspiration
US10062583B2 (en) 2016-05-09 2018-08-28 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10468329B2 (en) 2016-07-18 2019-11-05 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US10447347B2 (en) 2016-08-12 2019-10-15 Mc10, Inc. Wireless charger and high speed data off-loader
CN109716511A (zh) * 2016-08-12 2019-05-03 Qorvo美国公司 具有增强性能的晶片级封装
EP3497717A1 (en) 2016-08-12 2019-06-19 Qorvo Us, Inc. Wafer-level package with enhanced performance
JP7035014B2 (ja) 2016-08-12 2022-03-14 コーボ ユーエス，インコーポレイティド 性能が強化されたウェハレベルパッケージ
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10090339B2 (en) 2016-10-21 2018-10-02 Qorvo Us, Inc. Radio frequency (RF) switch
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10755992B2 (en) 2017-07-06 2020-08-25 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
CN109300794B (zh) * 2017-07-25 2021-02-02 中芯国际集成电路制造(上海)有限公司 封装结构及其形成方法
US10366972B2 (en) 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US12062700B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
EP3818558A1 (en) 2018-07-02 2021-05-12 Qorvo US, Inc. Rf semiconductor device and manufacturing method thereof
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
KR102595864B1 (ko) * 2018-12-07 2023-10-30 삼성전자주식회사 반도체 패키지
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
CN113632209A (zh) 2019-01-23 2021-11-09 Qorvo美国公司 Rf半导体装置和其制造方法
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12125825B2 (en) 2019-01-23 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
IT201900006740A1 (it) * 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
IT201900006736A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
US11721657B2 (en) 2019-06-14 2023-08-08 Stmicroelectronics Pte Ltd Wafer level chip scale package having varying thicknesses
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US10881028B1 (en) 2019-07-03 2020-12-29 Apple Inc. Efficient heat removal from electronic modules
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12129168B2 (en) 2019-12-23 2024-10-29 Qorvo Us, Inc. Microelectronics package with vertically stacked MEMS device and controller device
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11710945B2 (en) 2020-05-25 2023-07-25 Apple Inc. Projection of patterned and flood illumination
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US12087659B2 (en) * 2020-08-28 2024-09-10 Delphi Technologies Ip Limited Electronic power package and heat sink/cold rail arrangement
US11699715B1 (en) 2020-09-06 2023-07-11 Apple Inc. Flip-chip mounting of optoelectronic chips
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US12062571B2 (en) 2021-03-05 2024-08-13 Qorvo Us, Inc. Selective etching process for SiGe and doped epitaxial silicon
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
EP4199072A3 (en) * 2021-12-15 2023-08-09 IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik Fan-out wafer-level package
EP4199071A1 (en) * 2021-12-15 2023-06-21 IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik Fan-out wafer-level package
US12123589B1 (en) 2023-05-22 2024-10-22 Apple Inc. Flood projector with microlens array

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3343255A (en) * 1965-06-14 1967-09-26 Westinghouse Electric Corp Structures for semiconductor integrated circuits and methods of forming them
US3457123A (en) * 1965-06-28 1969-07-22 Motorola Inc Methods for making semiconductor structures having glass insulated islands
US3745984A (en) * 1971-12-27 1973-07-17 Gen Motors Corp Purge control valve and system
US4400870A (en) * 1980-10-06 1983-08-30 Texas Instruments Incorporated Method of hermetically encapsulating a semiconductor device by laser irradiation
JPS624351A (ja) * 1985-06-29 1987-01-10 Toshiba Corp 半導体キヤリアの製造方法
FR2599893B1 (fr) * 1986-05-23 1996-08-02 Ricoh Kk Procede de montage d'un module electronique sur un substrat et carte a circuit integre
US4882614A (en) * 1986-07-14 1989-11-21 Matsushita Electric Industrial Co., Ltd. Multiplex signal processing apparatus
JP2579937B2 (ja) * 1987-04-15 1997-02-12 株式会社東芝 電子回路装置およびその製造方法
JPH03155144A (ja) * 1989-11-13 1991-07-03 Sharp Corp ベアー半導体ｉｃチップ実装方法
US5111278A (en) * 1991-03-27 1992-05-05 Eichelberger Charles W Three-dimensional multichip module systems
US5291066A (en) * 1991-11-14 1994-03-01 General Electric Company Moisture-proof electrical circuit high density interconnect module and method for making same
US5422513A (en) * 1992-10-16 1995-06-06 Martin Marietta Corporation Integrated circuit chip placement in a high density interconnect structure
US5324687A (en) * 1992-10-16 1994-06-28 General Electric Company Method for thinning of integrated circuit chips for lightweight packaged electronic systems
US6274391B1 (en) * 1992-10-26 2001-08-14 Texas Instruments Incorporated HDI land grid array packaged device having electrical and optical interconnects
EP0604005A1 (en) * 1992-10-26 1994-06-29 Texas Instruments Incorporated Device packaged in a high interconnect density land grid array package having electrical and optical interconnects
US5300461A (en) * 1993-01-25 1994-04-05 Intel Corporation Process for fabricating sealed semiconductor chip using silicon nitride passivation film
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5306670A (en) * 1993-02-09 1994-04-26 Texas Instruments Incorporated Multi-chip integrated circuit module and method for fabrication thereof
US5422514A (en) * 1993-05-11 1995-06-06 Micromodule Systems, Inc. Packaging and interconnect system for integrated circuits
US5353195A (en) * 1993-07-09 1994-10-04 General Electric Company Integral power and ground structure for multi-chip modules
US5397921A (en) * 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
US5563664A (en) * 1994-01-05 1996-10-08 Samsung Electronics Co., Ltd. Pre-frame-comb as well as pre-line-comb partial-response filtering of BPSK buried in a TV signal
US5527741A (en) * 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
US5745984A (en) * 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
US5821608A (en) * 1995-09-08 1998-10-13 Tessera, Inc. Laterally situated stress/strain relieving lead for a semiconductor chip package
US5696666A (en) * 1995-10-11 1997-12-09 Motorola, Inc. Low profile exposed die chip carrier package
AU7096696A (en) * 1995-11-28 1997-06-19 Hitachi Limited Semiconductor device, process for producing the same, and packaged substrate
US5567657A (en) * 1995-12-04 1996-10-22 General Electric Company Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
JPH1084014A (ja) * 1996-07-19 1998-03-31 Shinko Electric Ind Co Ltd 半導体装置の製造方法
JP2982729B2 (ja) * 1997-01-16 1999-11-29 日本電気株式会社 半導体装置
US5894108A (en) * 1997-02-11 1999-04-13 National Semiconductor Corporation Plastic package with exposed die
KR100237328B1 (ko) * 1997-02-26 2000-01-15 김규현 반도체 패키지의 구조 및 제조방법
US5889654A (en) * 1997-04-09 1999-03-30 International Business Machines Corporation Advanced chip packaging structure for memory card applications
US5977639A (en) * 1997-09-30 1999-11-02 Intel Corporation Metal staples to prevent interlayer delamination
US6025995A (en) * 1997-11-05 2000-02-15 Ericsson Inc. Integrated circuit module and method
JPH11233678A (ja) * 1998-02-16 1999-08-27 Sumitomo Metal Electronics Devices Inc Ｉｃパッケージの製造方法
US6180881B1 (en) * 1998-05-05 2001-01-30 Harlan Ruben Isaak Chip stack and method of making same
US6130472A (en) * 1998-07-24 2000-10-10 International Business Machines Corporation Moisture and ion barrier for protection of devices and interconnect structures
US6396136B2 (en) * 1998-12-31 2002-05-28 Texas Instruments Incorporated Ball grid package with multiple power/ground planes
US6127833A (en) * 1999-01-04 2000-10-03 Taiwan Semiconductor Manufacturing Co. Test carrier for attaching a semiconductor device
US6306680B1 (en) * 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6117704A (en) * 1999-03-31 2000-09-12 Irvine Sensors Corporation Stackable layers containing encapsulated chips
US6288905B1 (en) * 1999-04-15 2001-09-11 Amerasia International Technology Inc. Contact module, as for a smart card, and method for making same
US6239482B1 (en) * 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
KR100333388B1 (ko) * 1999-06-29 2002-04-18 박종섭 칩 사이즈 스택 패키지 및 그의 제조 방법
US6221694B1 (en) * 1999-06-29 2001-04-24 International Business Machines Corporation Method of making a circuitized substrate with an aperture
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) * 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
JP3813402B2 (ja) * 2000-01-31 2006-08-23 新光電気工業株式会社 半導体装置の製造方法
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6423570B1 (en) * 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102687255A (zh) * 2010-02-03 2012-09-19 马维尔国际贸易有限公司 凹陷半导体衬底
CN102687255B (zh) * 2010-02-03 2015-03-04 马维尔国际贸易有限公司 凹陷半导体衬底
CN103201833A (zh) * 2010-11-05 2013-07-10 英特尔公司 密封管芯、包含该密封管芯的微电子封装以及制造所述微电子封装的方法
CN106340497A (zh) * 2010-11-05 2017-01-18 英特尔公司 密封管芯、包含该密封管芯的微电子封装以及制造所述微电子封装的方法
CN106340497B (zh) * 2010-11-05 2020-08-04 英特尔公司 密封管芯、包含该密封管芯的微电子封装以及制造所述微电子封装的方法
CN102738073A (zh) * 2012-05-24 2012-10-17 日月光半导体制造股份有限公司 间隔件及其制造方法
CN102738073B (zh) * 2012-05-24 2015-07-29 日月光半导体制造股份有限公司 间隔件及其制造方法
CN105164798A (zh) * 2013-03-13 2015-12-16 施韦策电子公司 电子组件和制造电子组件的方法
CN109637934A (zh) * 2014-10-11 2019-04-16 意法半导体有限公司 电子器件及制造电子器件的方法
CN109637934B (zh) * 2014-10-11 2023-12-22 意法半导体有限公司 电子器件及制造电子器件的方法

Also Published As

Publication number Publication date
JP2005506678A (ja) 2005-03-03
WO2002047162A3 (en) 2003-08-07
KR20040014432A (ko) 2004-02-14
AU2002232747A1 (en) 2002-06-18
EP1354354A2 (en) 2003-10-22
WO2002047162A2 (en) 2002-06-13
US20020070443A1 (en) 2002-06-13

Similar Documents

Publication Publication Date Title
CN1555573A (zh) 具有集成的散热片和增加层的微电子封装件
US20220051973A1 (en) Semiconductor package and manufacturing method thereof
CN100336220C (zh) 微电子封装及其制造方法
KR101277429B1 (ko) 스택 다이 ｂｇａ 또는 ｌｇａ 컴포넌트 어셈블리
US6818998B2 (en) Stacked chip package having upper chip provided with trenches and method of manufacturing the same
TWI809309B (zh) 半導體裝置以及其製造方法
US20060087037A1 (en) Substrate structure with embedded chip of semiconductor package and method for fabricating the same
US20080119029A1 (en) Wafer scale thin film package
JP2005517287A (ja) 構成要素をベースに埋め込み接触を形成する方法
US11476204B2 (en) Flip-chip packaging substrate and method for fabricating the same
CN1476631A (zh) 具有防湿结构的密封管芯封装上的直接组合层
KR20080093909A (ko) 히트 싱크 및 그라운드 차폐의 기능들을 개선하기 위한반도체 디바이스 패키지
JP2005327984A (ja) 電子部品及び電子部品実装構造の製造方法
US11139230B2 (en) Flip-chip package substrate and method for preparing the same
JP2008085089A (ja) 樹脂配線基板および半導体装置
TW201110309A (en) Stacking package structure with chip embedded inside and die having through silicon via and method of the same
JP2005150748A (ja) デカップリングコンデンサを有する半導体チップパッケージ及びその製造方法
JP2000323516A (ja) 配線基板の製造方法及び配線基板及び半導体装置
US10770444B2 (en) Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US6855573B2 (en) Integrated circuit package and manufacturing method therefor with unique interconnector
WO2019099195A1 (en) Semiconductor logic device and system and method of embedded packaging of same
US20050258536A1 (en) Chip heat sink device and method
CN102190279A (zh) 半导体装置
JP4084737B2 (ja) 半導体装置
TWI233672B (en) High density substrate for flip chip

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication