TWI233672B - High density substrate for flip chip - Google Patents

Abstract

A high-density substrate for flip chip is provided with a substrate 200, a thin film interconnect layer 202, a built-up structure layer 208 and a solder mask layer 220. A chip placement opening 250 formed with a placement region, a dispensing region, and a vacuum region is arranged in the substrate 200. The thin film interconnect layer 202 including a first dielectric layer 204 is formed over the surface of the substrate 200. The chip placement opening 250 exposes partial of the first dielectric layer 204. The built-up structure layer 208 is formed over the thin film interconnect layer 202. The thermal coefficient of expansion of the first dielectric layer 202 is larger than that of the substrate 200. The thermal coefficient of expansion of the built-up layer 208 is larger than that of the 200.

Description

1233672 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a flip chip package substrate, and in particular, to a high-density flip-chip package substrate and a high-density using the same Flip-chip ball grid array package. [Previous Technology] The development trend of chip packaging technology is toward reduction in size and increase in input / output contacts, so flip-chip (f 1 i p c h i p) technology has become one of the mainstream. The flip-chip technology mainly forms long bumps on external contacts (usually metal pads) on the wafer, and is electrically connected to the substrate through the bumps. With flip-chip technology, I / O contacts can be connected at high density, and low-inductance connections can be established. The structure of the conventional package substrate is made by a lamination method (1 ami n a t d) or a build-up method (build up). Therefore, the flatness (u n i f 0 r m i t y) of the outer layer is gradually deteriorated, so accuracy control is difficult. Therefore, when the package substrate is applied to the requirements of high density and fine pitch of a flip-chip package, the manufacturing difficulty is high and the yield is affected. In addition, when the conventional high-density substrate is applied to the flip-chip technology, in order to achieve the stability of the inter-layer alignment, a thicker inner substrate must be used, so the total thickness of the substrate is high, resulting in poor telecommunication performance. Because of the known hardness of the South Density substrate, after the implantation of the flip-chip wafer, the stress and strain caused by the difference in thermal expansion coefficient between the substrate and the wafer during operation will cause damage to the insulating layer on the wafer. [Summary of the Invention] In order to solve the conventional problems, one object of the present invention is to propose

10393twf.ptd Page 6 1233672 V. Description of the invention (2) A high-density flip-chip package substrate, through which the stress and strain on the wafer packaged on it can be reduced to improve the yield and reliability of the package degree. One of the objectives of the present invention is to provide a high-density flip-chip package substrate, which can be applied to package flip-chip wafers with micro-pitch bumps. By this substrate, a thin flip chip package can be achieved and has two telecommunication performances. In order to achieve the above and other objectives, the present invention provides a high-density flip-chip package substrate, including: a substrate, a thin-film interconnect layer, a laminated structure layer, and a solder resist layer. Wherein, the substrate has a wafer placement opening, and the wafer placement opening has a wafer placement area, a glue area, and a vacuum extraction area. The wafer system has a layer of two leads and a second opening in the film. The coefficient in the film is 0. Among them, the placement area of the dispensing area and the true corner have a surface of the first dielectric layer board exposed to cover the thin dielectric layer and the dielectric layer, and the connection layer is exposed. The first dielectric layer is connected to the first dielectric layer, and each solder layer intersects within the film. The anti-exposed part of the first dielectric layer structure layer has an empty area extension and a wire layer dielectric. It has two pairs of the thermal expansion system and the chip on the farthest layer. One pair of areas is covered by a first wire. The first layer has multiple thermal coefficients of thermal expansion and expansion of a plurality of adjacent laminated layers separated from the substrate. The first coefficient of the second and second structural layers interspersed with the crystals is greater than the phase of the region. Film layer. The first layer. Chip placement, block opening, dielectric layer, wire layer, solder-proof two wires are larger than the base substrate, and a dielectric layer is placed along the interconnect layer to expose the exposed layer structure, wafer openings, and layers. The thermal expansion of the board has a plurality of first and a plurality of which is thin. The thermal expansion service is to achieve the thermal expansion coefficient of the present invention.

10393twf.ptd Page 7 1233672 V. Description of the invention (3) After the inspection, the material of the first dielectric layer of the film interconnect layer of the present invention is selected from the group consisting of epoxy-containing polymers and polyimide. And polytetrafluoroethylene (PTFE), etc., and in accordance with its thermal expansion coefficient, materials such as silicon, glass, ceramics, and metals are appropriately selected as the material of the substrate to achieve the above characteristics. The circuit pattern of each of the above-mentioned wire layers is wavy at the edge corresponding to the opening where the wafer is placed. According to the features of the present invention, there are a pair of dispensing areas and a vacuuming area extending diagonally from the wafer placement area. Therefore, when the high-density flip-chip package substrate of the present invention is used for packaging, the present invention can perform spot placement in the wafer placement area. Glue, and vacuuming on the opposite side, in this way, can shorten the filling time of 1 primer, and can effectively prevent the occurrence of air bubbles. The same as above, because the dispensing area and the vacuum area have been set in the wafer placement opening, the wafer placement area can be minimized, and the reliability of the package can be improved. According to the features of the present invention, each wire layer is wavy at the edge corresponding to the opening on which the wafer is placed, and has a buffering effect when the substrate is deformed, thereby improving the substrate's ability to withstand strain. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: [Embodiment] [First Embodiment ] Please refer to Figures 1 to 4 in order, which shows a preferred implementation according to the present invention.

10393iwf.ptd Page 8 1233672 V. Description of the Invention (4) The cross-sectional view of the manufacturing process of the high-density flip-chip package substrate. Referring to FIG. 1, a substrate 200 is provided, which has a first surface 200a and a second surface 200b. An interconnecting layer 202 is formed by a thin film deposition method and covers the first surface 200a of the substrate 200. For example, a first dielectric layer 204 is formed by coating, and a first wire layer 206 is formed, for example, by using a coin key and a semi-additive method. The first dielectric layer 204 covers the first surface 200 a of the substrate 200. The first wire layer 206 is coated on the first dielectric layer 204. Here, a dry epoxy resin film or a liquid epoxy resin film (including coating and hardening processes) can be laminated to form a first epoxy resin film. A dielectric layer 2 0 4. The thickness of the first dielectric layer 204 is 10 micrometers to 50 micrometers, so that the thermal expansion coefficient of the first dielectric layer 204 is larger than the thermal expansion coefficient of the substrate 200. The purpose is to keep the epoxy resin layer in tension (bearing tension) when it is cooled to room temperature after depositing the epoxy resin layer. With this, the dielectric layer and the wire layer can be kept stable, so the position of each wire layer and the opening in the layer can be maintained at a fixed position without being affected by the environment. To meet the requirements of the present invention for the coefficient of thermal expansion, the material of the first dielectric layer 204 of the thin film interconnect layer 202 may be selected from polymers including epoxy groups, polyimide, and polytetrafluoroethylene. And, in accordance with its thermal expansion coefficient, materials including silicon, glass, ceramics, and metals are appropriately selected as the materials of the substrate to achieve the above characteristics. Please refer to Figures 2 to 3 to form a build-up structure layer 2 0 by the built-up method (see Figure 3), which is alternately formed by a dielectric layer and a wire layer, covering the interconnect layer 2 0 2, and the same as above, the thermal expansion of the laminated structure layer 208

10393twf.ptd Page 9 1233672 V. Description of the invention (5) The coefficient is greater than the thermal expansion coefficient of the substrate 200. As shown in FIG. 2, a patterned second dielectric layer 210 is formed to cover the interconnect layer 202, and then a patterned second wire layer 212 is formed to cover the second dielectric layer 21. In the process of forming the multilayer structure 2008, if a conductor material (such as metal) is selected as the material of the substrate, the following steps can be performed (see Fig. 2) to further improve the current transmission effect of the wafer. As exemplified in FIG. 2, a through hole 2 1 8 is formed in a manner of laser drilling and electroplating, and a wafer placement area 250 a is located at a wafer placement opening 2 50 of the substrate 200 (see FIG. 6 described later for details). In addition, the first dielectric layer 204 and the adjacent second dielectric layer 210 are penetrated to contact the second wire layer 212 and the substrate 200 closest to the substrate 2000, and simultaneously contact the first wire layer 206. Here, with the structural characteristics of the through-hole 2 18 described above, the substrate 2000 can be connected to the ground again. In this way, a short and wide ground connection can be formed, and the current transmission efficiency of the chip can be greatly improved. As shown in FIG. 3, a subsequent step of forming a laminated structure 208 is performed, and a patterned second dielectric layer 214 is further formed, covering the second wire layer 212, and then a patterned second wire layer is formed. 216, covering the second dielectric layer 212. A solder resist layer 220 is formed to cover the laminated structure layer 208. The solder resist layer has a plurality of openings 220a to expose a portion of the second wire layer 216 farthest from the substrate 200. A solder ball pad 2 2 2 is formed on the second guide layer 216 exposed by the opening 220a. Please refer to FIG. 4 'to form a wafer placement opening 250 on the first surface 200b of the substrate 2000 to expose a portion of the first dielectric layer 204. By making the thermal expansion coefficient of the first dielectric layer 204 of the interconnect layer 202 greater than

10393twf.ptd Page 10 1233672 V. Description of the invention (6) Thermal expansion coefficient of plate 2 0 0. The first dielectric layer 204 exposed to the bottom of the wafer placement opening 250 is also under tension. Please refer to FIG. 6 at the same time. The wafer placement opening 250 has a wafer placement area 250a, a little glue area 250b, and a vacuum extraction area 250c. The reference numeral 2 60 indicates the wafer to be attached in this area. . The shape of the wafer placement opening 2 50 is as follows. The wafer placement area 2 50 a has a shape slightly larger than the flip-chip wafer 2 6 0 (see FIG. 5) to be attached. The vacuum area 2 50 b is connected to the wafer placement area 250 a and is a pair of areas extending outward along the diagonal of the wafer placement area 250 a. Next, a plurality of bump openings 252 are formed in the exposed first dielectric layer 204 to expose a part of the first wiring layer 206. Methods of forming bump openings include, for example, laser drilling. Please refer to FIG. 8, which shows an example of a wiring pattern corresponding to the periphery of the chip placement opening of each wire layer, and the first wire layer is taken as an example in the figure. It is worth noting here that when forming the above-mentioned wire layer (206, 21, 2, 16), each wire layer is at the edge of the corresponding chip placement opening 2 50 (as shown by the dashed line 2 4 8 in the figure) Wavy line pattern. The reason for forming the wavy line pattern at the side corresponding to the opening where the wafer is placed is as follows: According to the features of the present invention, in the flip-chip ball grid array package of the present invention, the portion outside the wafer placement opening, All include metal substrates, thin-film interconnect layers, and laminated structure layers. However, there is no part of the metal substrate in the wafer placement opening, so this packaging structure becomes weaker in the structure around the corresponding wafer placement opening. Part. According to the spirit of the present invention, the edge of the opening 2 5 0 is placed on the wafer.

I1III

10393twf.ptd Page 111233672 V. Description of the invention (7) 2 4 8 is a wave-shaped elongated circuit pattern, which has a buffering effect when the substrate is deformed (for example, due to thermal expansion), so that the wire is not damaged due to deformation. Therefore, the reliability of the product can be improved. It can be seen that the present invention does not need to be limited to this wave shape, in short, such as a sawtooth shape, or any other bent shape. [Second Embodiment] In the first embodiment, a process for forming a high-density flip-chip package substrate according to a preferred embodiment of the present invention is illustrated. In the second embodiment, the structure of the high-density flip-chip ball grid array package obtained by applying the high-density flip-chip package substrate of the first embodiment will be exemplified. In the second embodiment, the same components as those in the first embodiment are designated by the same reference numerals, and repeated descriptions are omitted here. Please refer to FIG. 6, and attach a flip-chip wafer 2 60 to the wafer placement area 250 a in the wafer placement opening 250. The flip-chip wafer 260 has an active surface 260a, and a plurality of bumps 262 are formed on the active surface 260a. Through a re-soldering step, the bumps 2 6 2 and the first wire layer 2 0 6 exposed by the bump openings 2 5 2 are electrically connected. Next, a primer filling step is performed, the glue is dispensed in the dispensing area 250b of the opening 250 where the wafer is placed, and the vacuum is evacuated in the evacuation area 250c to fill a bump 2 7 0 into the bump 2 6 2 Gap between. According to the spirit of the present invention, it is not necessary to limit the shape of the wafer placement opening 250. The key is that the wafer placement area 250a is close to and slightly larger than the shape of the flip-chip wafer 260. The dispensing area 250a and the vacuuming area 250b are connected to the wafer placement area 250a, and are located at two opposite sides of the wafer placement area 250a, respectively.

10393twf.ptd Page 12 1233672 V. Description of the invention (8) side to facilitate vacuuming operation. Then, a glue step is performed, and a wafer material 2 900 is filled into the wafer placement opening 2 50 to cover the bottom glue 2 7 0 to surround the flip-chip wafer 2 600 and a part of the flip-chip wafer is exposed. 2 6 0. Then, a ball-planting step is performed, and a plurality of solder balls 2 0 are electrically connected to the second wire farthest from the substrate 2 0 through the solder ball pad 2 2 2 through the solder mask 2 2 0. Layer 2 1 6, so far to complete the high-density flip-chip ball grid array package. It can be known from the disclosure of the embodiments that the present invention has at least the following advantages: (1). The thermal expansion coefficient of the first dielectric layer of the thin film interconnect layer in the present invention is greater than the thermal expansion coefficient of the substrate. Therefore, when the first dielectric layer is cooled to room temperature after the first dielectric layer is formed, the first dielectric layer can be maintained in a stretched state (bearing a tensile force). With this, the dielectric layer and the wire layer can be kept stable, so the positions of the wires and openings in the layer can be maintained at a fixed position without being affected by the environment. (2). As above, in the present invention, the thermal expansion coefficient of the laminated structural layer is greater than the thermal expansion coefficient of the substrate, which can enhance the effect of the above point 1. (3). The present invention has a pair of dispensing areas and a vacuuming area extending diagonally from the wafer placement area. Therefore, the present invention performs dispensing on one side of the wafer placement area and vacuuming on the opposite side. This method can shorten the time for filling the bottom glue, and can effectively prevent the occurrence of air bubbles. (4). The same reason as above, because a dispensing area and a vacuum area have been set in the wafer placement opening, the wafer placement area can be minimized, and the reliability of the package can be improved. (5) Each wire layer of the present invention is wavy at the opening where the corresponding wafer is placed, and has a buffering effect when the substrate is deformed, thereby improving the ability of the substrate to withstand strain and thus improving the reliability of the product.

10393twf.ptd Page 13 1236372 5. Description of the invention (9) (6). When a conductive material (such as metal) is selected as the material of the substrate, the present invention can use a through hole to make the conductive layer of the laminated structure layer contact the metal substrate. The wiring layer of the film interconnecting layer is connected to the metal substrate through the wiring layer of the laminated structure layer, and then the metal substrate is grounded. This simplifies the manufacturing process and enables the flip-chip wafer to obtain a good current transmission effect. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

10393twf.ptd Page 14 1236372 Brief description of the drawings Figures 1 to 4 show cross-sectional views of the process flow of a high-density flip-chip package substrate according to the preferred embodiment of the present invention; Figure 5 shows the preferred method according to the present invention A structural cross-sectional view of a high-density flip-chip ball grid array package according to an embodiment; FIG. 6 illustrates an exemplary plan view of a wafer placement opening according to a preferred embodiment of the present invention; and FIG. 7 illustrates a comparison according to the present invention. An exemplary plan view of one of the wiring patterns of each of the lead layers of the preferred embodiment. [Schematic description] 200 substrate 202: interconnecting layer (film interconnecting layer) 204 first dielectric layer 206: first wire layer 208 laminated structure layer 210, 2 1 4: second dielectric layer 212 ^ 216 1 2nd wire layer 218: through hole 220 solder mask 2 2 0a: opening 222 solder ball pad 248: edge of wafer placement opening 250 wafer placement opening 2 5 0 a: wafer placement area 2 5 0 b: dispensing Area 2 5 0 c: Evacuation area 2 5 2:: Bump opening 260: Chip on wafer 2 6 0 a: Active surface 262: Bump 2 7 0:: Primer 2 8 0: Solder ball 290: Sealant

10393twf.ptd Page 15

Claims (1)

1233672 VI. Patent application scope 1. A high-density flip-chip package substrate, comprising: a substrate having a first surface and a second surface, and having a wafer placement opening, the wafer placement opening having a wafer placement area, a Dispensing area and a vacuuming area, wherein the dispensing area and the vacuuming area are connected to the wafer placement area and are a pair of areas extending outward along the diagonal of the wafer placement area; a thin film interconnecting layer Covering the first surface of the substrate, the thin film interconnect layer having a first dielectric layer and a first wire layer, the first dielectric layer covering the first surface of the substrate, the first The wire layer covers the first dielectric layer, wherein the wafer placement opening exposes a portion of the first dielectric layer, and is further within the first dielectric layer of the portion exposed by the wafer placement opening. Having a plurality of bump openings; a laminated structure layer covering the film interconnect layer, having a plurality of second dielectric layers and a plurality of second wire layers alternate with each other, and every two adjacent second wires There is a second between the layers An electrical layer; and a solder mask layer covering the laminated structure layer, the solder mask layer has a plurality of openings to expose a portion of the second wire layer farthest from the substrate, wherein the film interconnect layer The thermal expansion coefficient of the first dielectric layer is greater than the thermal expansion coefficient of the substrate, and the thermal expansion coefficient of the laminated structure layer is greater than the thermal expansion coefficient of the substrate. 2. The high-density flip-chip package substrate according to item 1 of the scope of the patent application, wherein the wafer placement area of the wafer placement opening is slightly larger than the shape of a flip-chip wafer to be attached. 3. High-density flip-chip packaging base as described in item 1 of the scope of patent application 10393twf.ptd Page 16 1233672 Board Fluorine board Board board Six, patent application board, where the first wire layer and the edge where the wafer should be placed 4 · As in the first board of the patent application, where the film is connected internally The polymer of the oxygen layer of the wire. 5. The fourth board of the scope of patent application, wherein the S-line amine of the film interconnect layer. 6. The fourth aspect of the patent application, wherein the film is an ethylene interconnect layer. 7. If the scope of the patent application is No. 1, the material of the substrate includes 8. If the scope of the patent application is No. 1, where the material of the substrate includes 9. If the scope of patent is No. 1, where the material of the substrate includes 10. The scope of the patent, where the substrate is made of metal 1 1. As the scope of the patent application, the board further includes a through hole located in the second time contact that passes through the first dielectric layer and is closest to the first contact with the substrate. The first wire layer. The circuit patterns of these second wire layers are wavy in pairs. The high-density flip-chip package base described in item 1, the material of the first dielectric layer includes the high-density flip-chip package base described in ring item, and the material of the first dielectric layer includes the high-density flip-chip described in the sub-item. The material of the first dielectric layer of the package base includes the high-density flip-chip package base stone described in the above item. The high-density flip-chip packaging base glass as described in the item. The high-density flip-chip package-based ceramics described in the item. The high-density flip-chip package base according to item 1; the high-density flip-chip package-based substrate according to item 1; outside the wafer placement area of the high-density flip-chip package base substrate according to item 1, the second dielectric layer adjacent to the dielectric layer is a wire layer, and Contact the substrate, and 10393twf.ptd Page 17 1233672 VI. Scope of Patent Application 1 2 · The high-density flip-chip package substrate described in item 11 of the patent application scope, where the substrate is used as a ground point. 1 3. A high-density flip-chip ball grid array package, comprising: a substrate having a first surface and a second surface, and having a wafer placement opening, the wafer placement opening having a wafer placement area, a Dispensing area and a vacuuming area, wherein the dispensing area and the vacuuming area are connected to the wafer placement area and are a pair of areas extending outward along the diagonal of the wafer placement area; a thin film interconnecting layer Covering the first surface of the substrate, the thin film interconnect layer having a first dielectric layer and a first wire layer, the first dielectric layer covering the first surface of the substrate, the first The wire layer covers the first dielectric layer, wherein the wafer placement opening exposes a portion of the first dielectric layer, and is further within the first dielectric layer of the portion exposed by the wafer placement opening. Having a plurality of bump openings, wherein a thermal expansion coefficient of the first dielectric layer of the thin film interconnecting layer is greater than a thermal expansion coefficient of the substrate; a laminated structure layer covering the thin film interconnecting layer having a plurality of second Dielectric layer and a plurality of second wires Alternate with each other, there is a second dielectric layer between every two adjacent second wire layers, wherein the thermal expansion coefficient of the laminated structure layer is greater than the thermal expansion coefficient of the substrate; a flip-chip wafer is attached to the In the wafer placement opening, the flip-chip wafer has an active surface, and a plurality of bumps are formed on the active surface. The flip-chip wafer is electrically connected to the bump openings through the bumps being electrically connected to the bump openings. The first wire layer; a solder resist layer covering the laminated structure layer, the solder resist layer has a plurality of 10393twf.ptd Page 18 1233672 6. Apply for a patent to open an opening to expose a portion of the second wire layer farthest from the substrate, a primer, and fill the gap between the bumps; and a plurality of Each solder ball is electrically connected to the second wire layer farthest from the substrate of the exposed portion of the solder resist opening. 1 4. The high-density flip-chip ball grid array package according to item 13 of the scope of the patent application, wherein the wafer placement area of the wafer placement opening is slightly larger than the shape of the flip-chip wafer. 1 5 · The high-density flip-chip ball grid array package according to item 13 of the scope of the patent application, wherein the circuit patterns of the first wire layer and the second wire layers are tied at the edges corresponding to the openings where the chip is placed. Wavy. 16. The high-density flip-chip ball grid array package according to item 13 of the scope of the patent application, wherein the material of the first dielectric layer of the film interconnect layer includes an epoxy-based polymer. 1 7. The high-density flip-chip ball grid array package as described in item 16 of the scope of patent application, wherein the material of the first dielectric layer of the film interconnect layer includes polyimide. 1 8. The high-density flip-chip ball grid array package as described in item 16 of the scope of patent application, wherein the material of the first dielectric layer of the thin film interconnect layer includes polytetrafluoroethylene. 19. The high-density flip-chip ball grid array package as described in item 13 of the scope of patent application, wherein the material of the substrate includes silicon. 20. The high-density flip-chip ball grid array package according to item 13 of the scope of patent application, wherein the material of the substrate includes glass. 2 1. High-density flip chip lattice as described in item 13 of the scope of patent application 10393twf.ptd Page 19 1233672 6. Scope of patent application In-line package, in which the material of the substrate includes ceramic. 2 2 · The high-density flip-chip ball grid array package according to item 13 of the scope of patent application, wherein the substrate is made of metal. 2 3. The high-density flip-chip ball grid array package as described in item 22 of the patent application scope further includes a through hole located outside the wafer placement area of the substrate, penetrating the first dielectric layer and communicating with the The second dielectric layer adjacent to the first dielectric layer contacts the second wire layer and the substrate closest to the substrate, and simultaneously contacts the first wire layer. 2 4. The high-density flip-chip ball grid array package as described in item 23 of the patent application scope, wherein the substrate is used as a ground point. 2 5. The high-density flip-chip ball grid array package as described in item 13 of the scope of the patent application, further comprising a piece of glue filled in the wafer placement opening to cover the primer to surround the flip-chip wafer. 'And exposed part of the flip chip 0 10393twf.ptd Page 20