AU2002232747A1 - Microelectronic package having an integrated heat sink and build-up layers - Google Patents

Microelectronic package having an integrated heat sink and build-up layers

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Publication number
AU2002232747A1
AU2002232747A1 AU2002232747A AU3274702A AU2002232747A1 AU 2002232747 A1 AU2002232747 A1 AU 2002232747A1 AU 2002232747 A AU2002232747 A AU 2002232747A AU 3274702 A AU3274702 A AU 3274702A AU 2002232747 A1 AU2002232747 A1 AU 2002232747A1
Authority
AU
Australia
Prior art keywords
build
layers
heat sink
microelectronic package
integrated heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002232747A
Inventor
Maria V. Henao
Qing Ma
Xiao-Chun Mu
Steven N. Towle
Quat T. Vu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2002232747A1 publication Critical patent/AU2002232747A1/en
Abandoned legal-status Critical Current

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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AU2002232747A 2000-12-08 2001-11-09 Microelectronic package having an integrated heat sink and build-up layers Abandoned AU2002232747A1 (en)

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US09/733,289 US20020070443A1 (en) 2000-12-08 2000-12-08 Microelectronic package having an integrated heat sink and build-up layers
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Families Citing this family (151)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6890829B2 (en) * 2000-10-24 2005-05-10 Intel Corporation Fabrication of on-package and on-chip structure using build-up layer process
US6706553B2 (en) * 2001-03-26 2004-03-16 Intel Corporation Dispensing process for fabrication of microelectronic packages
US6888240B2 (en) * 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US7183658B2 (en) * 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TW517361B (en) * 2001-12-31 2003-01-11 Megic Corp Chip package structure and its manufacture process
US6964881B2 (en) * 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP3813945B2 (en) * 2003-05-07 2006-08-23 任天堂株式会社 GAME DEVICE AND GAME PROGRAM
TWI286372B (en) * 2003-08-13 2007-09-01 Phoenix Prec Technology Corp Semiconductor package substrate with protective metal layer on pads formed thereon and method for fabricating the same
CN100418211C (en) * 2003-12-25 2008-09-10 卡西欧计算机株式会社 Semiconductor device and method of fabricating the same
US7489032B2 (en) * 2003-12-25 2009-02-10 Casio Computer Co., Ltd. Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same
CN1316611C (en) * 2004-03-19 2007-05-16 矽品精密工业股份有限公司 Wafer-level semiconductor package having lamination structure and making method thereof
TWI245350B (en) * 2004-03-25 2005-12-11 Siliconware Precision Industries Co Ltd Wafer level semiconductor package with build-up layer
CN1316604C (en) * 2004-03-31 2007-05-16 矽品精密工业股份有限公司 Semiconductor package device with layer-increasing structure and making method thereof
US20060051912A1 (en) * 2004-09-09 2006-03-09 Ati Technologies Inc. Method and apparatus for a stacked die configuration
US7468545B2 (en) * 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
JP4533248B2 (en) * 2005-06-03 2010-09-01 新光電気工業株式会社 Electronic equipment
US7582556B2 (en) * 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
TWI293202B (en) * 2005-11-23 2008-02-01 Phoenix Prec Technology Corp Carrier board structure with semiconductor component embedded therein
US20080099910A1 (en) * 2006-08-31 2008-05-01 Ati Technologies Inc. Flip-Chip Semiconductor Package with Encapsulant Retaining Structure and Strip
US20080054490A1 (en) 2006-08-31 2008-03-06 Ati Technologies Inc. Flip-Chip Ball Grid Array Strip and Package
US7911044B2 (en) * 2006-12-29 2011-03-22 Advanced Chip Engineering Technology Inc. RF module package for releasing stress
US8106496B2 (en) * 2007-06-04 2012-01-31 Stats Chippac, Inc. Semiconductor packaging system with stacking and method of manufacturing thereof
TW200900628A (en) * 2007-06-28 2009-01-01 Wen-Chin Shiau Manufacturing method of heat-dissipating structure of high-power LED lamp seat and product thereof
US8217511B2 (en) * 2007-07-31 2012-07-10 Freescale Semiconductor, Inc. Redistributed chip packaging with thermal contact to device backside
KR101538648B1 (en) * 2007-07-31 2015-07-22 인벤사스 코포레이션 Semiconductor packaging process using through silicon vias
US20090051019A1 (en) * 2007-08-20 2009-02-26 Chih-Feng Huang Multi-chip module package
US20090072382A1 (en) * 2007-09-18 2009-03-19 Guzek John S Microelectronic package and method of forming same
US9941245B2 (en) * 2007-09-25 2018-04-10 Intel Corporation Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
US9123614B2 (en) 2008-10-07 2015-09-01 Mc10, Inc. Methods and applications of non-planar imaging arrays
US8097926B2 (en) 2008-10-07 2012-01-17 Mc10, Inc. Systems, methods, and devices having stretchable integrated circuitry for sensing and delivering therapy
US8389862B2 (en) 2008-10-07 2013-03-05 Mc10, Inc. Extremely stretchable electronics
JP4833307B2 (en) * 2009-02-24 2011-12-07 インターナショナル・ビジネス・マシーンズ・コーポレーション Semiconductor module, terminal plate, method for manufacturing terminal plate, and method for manufacturing semiconductor module
KR101170878B1 (en) * 2009-06-29 2012-08-02 삼성전기주식회사 Semiconductor chip package and method for manufacturing the same
KR101058621B1 (en) * 2009-07-23 2011-08-22 삼성전기주식회사 Semiconductor package and manufacturing method thereof
US8003496B2 (en) 2009-08-14 2011-08-23 Stats Chippac, Ltd. Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die
US8502394B2 (en) * 2009-12-31 2013-08-06 Stmicroelectronics Pte Ltd. Multi-stacked semiconductor dice scale package structure and method of manufacturing same
US8884422B2 (en) 2009-12-31 2014-11-11 Stmicroelectronics Pte Ltd. Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture
US20110156240A1 (en) * 2009-12-31 2011-06-30 Stmicroelectronics Asia Pacific Pte. Ltd. Reliable large die fan-out wafer level package and method of manufacture
US8436255B2 (en) * 2009-12-31 2013-05-07 Stmicroelectronics Pte Ltd. Fan-out wafer level package with polymeric layer for high reliability
US8466997B2 (en) * 2009-12-31 2013-06-18 Stmicroelectronics Pte Ltd. Fan-out wafer level package for an optical sensor and method of manufacture thereof
US20110186960A1 (en) * 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
JP5610422B2 (en) * 2010-02-04 2014-10-22 富士通株式会社 Semiconductor device and manufacturing method of semiconductor device
KR101110345B1 (en) * 2010-03-31 2012-02-15 한상일 Detachable cover member of illuminator
US8455300B2 (en) 2010-05-25 2013-06-04 Stats Chippac Ltd. Integrated circuit package system with embedded die superstructure and method of manufacture thereof
US20120112336A1 (en) * 2010-11-05 2012-05-10 Guzek John S Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package
JP5636265B2 (en) * 2010-11-15 2014-12-03 新光電気工業株式会社 Semiconductor package and manufacturing method thereof
US9013037B2 (en) 2011-09-14 2015-04-21 Stmicroelectronics Pte Ltd. Semiconductor package with improved pillar bump process and structure
US9679863B2 (en) * 2011-09-23 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect substrate for FO-WLCSP
US8779601B2 (en) 2011-11-02 2014-07-15 Stmicroelectronics Pte Ltd Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US8916481B2 (en) 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
CN102738073B (en) * 2012-05-24 2015-07-29 日月光半导体制造股份有限公司 Distance piece and manufacture method thereof
US9136236B2 (en) 2012-09-28 2015-09-15 Intel Corporation Localized high density substrate routing
US8912670B2 (en) * 2012-09-28 2014-12-16 Intel Corporation Bumpless build-up layer package including an integrated heat spreader
US9171794B2 (en) * 2012-10-09 2015-10-27 Mc10, Inc. Embedding thin chips in polymer
CN105008949A (en) 2012-10-09 2015-10-28 Mc10股份有限公司 Conformal electronics integrated with apparel
US9190380B2 (en) 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US9583414B2 (en) 2013-10-31 2017-02-28 Qorvo Us, Inc. Silicon-on-plastic semiconductor device and method of making the same
DE102013102542A1 (en) 2013-03-13 2014-09-18 Schweizer Electronic Ag Electronic component and method for manufacturing an electronic component
US9706647B2 (en) 2013-05-14 2017-07-11 Mc10, Inc. Conformal electronics including nested serpentine interconnects
US9576909B2 (en) * 2013-08-21 2017-02-21 Intel Corporation Bumpless die-package interface for bumpless build-up layer (BBUL)
US9159690B2 (en) 2013-09-25 2015-10-13 Intel Corporation Tall solders for through-mold interconnect
US9349703B2 (en) 2013-09-25 2016-05-24 Intel Corporation Method for making high density substrate interconnect using inkjet printing
JP6711750B2 (en) 2013-11-22 2020-06-17 エムシー10 インコーポレイテッドMc10,Inc. Conformal sensor system for detection and analysis of cardiac activity
WO2015175517A1 (en) * 2014-05-12 2015-11-19 Skyworks Solutions, Inc. Devices and methods for processing singulated radio-frequency units
TWI543320B (en) * 2014-08-29 2016-07-21 矽品精密工業股份有限公司 Semiconductor package and a method for fabricating the same
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
CN105514080B (en) * 2014-10-11 2018-12-04 意法半导体有限公司 Electronic device and correlation technique with redistributing layer and reinforcer
USD781270S1 (en) 2014-10-15 2017-03-14 Mc10, Inc. Electronic device having antenna
US9530709B2 (en) 2014-11-03 2016-12-27 Qorvo Us, Inc. Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
KR101647559B1 (en) * 2014-11-07 2016-08-10 앰코 테크놀로지 코리아 주식회사 Method of manufactuing semiconductor package and semiconductor package
US20160172313A1 (en) * 2014-12-16 2016-06-16 Nantong Fujitsu Microelectronics Co., Ltd. Substrate with a supporting plate and fabrication method thereof
WO2016134306A1 (en) 2015-02-20 2016-08-25 Mc10, Inc. Automated detection and configuration of wearable devices based on on-body status, location, and/or orientation
US9613831B2 (en) 2015-03-25 2017-04-04 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
US9819144B2 (en) 2015-05-14 2017-11-14 Apple Inc. High-efficiency vertical emitters with improved heat sinking
US10034375B2 (en) 2015-05-21 2018-07-24 Apple Inc. Circuit substrate with embedded heat sink
US20160343604A1 (en) 2015-05-22 2016-11-24 Rf Micro Devices, Inc. Substrate structure with embedded layer for post-processing silicon handle elimination
US9553036B1 (en) * 2015-07-09 2017-01-24 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
US9735539B2 (en) 2015-07-20 2017-08-15 Apple Inc. VCSEL structure with embedded heat sink
CN105023900A (en) * 2015-08-11 2015-11-04 华天科技(昆山)电子有限公司 Embedded silicon substrate fan-out type packaging structure and manufacturing method thereof
US10620300B2 (en) 2015-08-20 2020-04-14 Apple Inc. SPAD array with gated histogram construction
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
US9997551B2 (en) 2015-12-20 2018-06-12 Apple Inc. Spad array with pixel-level bias control
US10324171B2 (en) 2015-12-20 2019-06-18 Apple Inc. Light detection and ranging sensor
US10020405B2 (en) 2016-01-19 2018-07-10 Qorvo Us, Inc. Microelectronics package with integrated sensors
EP3206229B1 (en) * 2016-02-09 2020-10-07 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Methods of manufacturing flexible electronic devices
EP3420733A4 (en) 2016-02-22 2019-06-26 Mc10, Inc. System, device, and method for coupled hub and sensor node on-body acquisition of sensor information
EP3829187A1 (en) 2016-02-22 2021-06-02 Medidata Solutions, Inc. System, devices, and method for on-body data and power transmission
US11154235B2 (en) 2016-04-19 2021-10-26 Medidata Solutions, Inc. Method and system for measuring perspiration
US10062583B2 (en) 2016-05-09 2018-08-28 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US10079196B2 (en) 2016-07-18 2018-09-18 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10486965B2 (en) * 2016-08-12 2019-11-26 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10486963B2 (en) 2016-08-12 2019-11-26 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10447347B2 (en) 2016-08-12 2019-10-15 Mc10, Inc. Wireless charger and high speed data off-loader
WO2018031995A1 (en) 2016-08-12 2018-02-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10090339B2 (en) 2016-10-21 2018-10-02 Qorvo Us, Inc. Radio frequency (RF) switch
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10490471B2 (en) 2017-07-06 2019-11-26 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
CN109300794B (en) * 2017-07-25 2021-02-02 中芯国际集成电路制造(上海)有限公司 Package structure and method for forming the same
US10366972B2 (en) 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US12062700B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
CN118213279A (en) 2018-07-02 2024-06-18 Qorvo美国公司 RF semiconductor device and method for manufacturing the same
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
KR102595864B1 (en) * 2018-12-07 2023-10-30 삼성전자주식회사 Semiconductor package
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
CN113632209A (en) 2019-01-23 2021-11-09 Qorvo美国公司 RF semiconductor device and method for manufacturing the same
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
IT201900006740A1 (en) 2019-05-10 2020-11-10 Applied Materials Inc SUBSTRATE STRUCTURING PROCEDURES
IT201900006736A1 (en) 2019-05-10 2020-11-10 Applied Materials Inc PACKAGE MANUFACTURING PROCEDURES
US11721657B2 (en) 2019-06-14 2023-08-08 Stmicroelectronics Pte Ltd Wafer level chip scale package having varying thicknesses
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US10881028B1 (en) 2019-07-03 2020-12-29 Apple Inc. Efficient heat removal from electronic modules
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11710945B2 (en) 2020-05-25 2023-07-25 Apple Inc. Projection of patterned and flood illumination
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US12087659B2 (en) * 2020-08-28 2024-09-10 Delphi Technologies Ip Limited Electronic power package and heat sink/cold rail arrangement
US11699715B1 (en) 2020-09-06 2023-07-11 Apple Inc. Flip-chip mounting of optoelectronic chips
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US12062571B2 (en) 2021-03-05 2024-08-13 Qorvo Us, Inc. Selective etching process for SiGe and doped epitaxial silicon
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
EP4199071A1 (en) * 2021-12-15 2023-06-21 IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik Fan-out wafer-level package
EP4199072A3 (en) * 2021-12-15 2023-08-09 IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik Fan-out wafer-level package

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3343255A (en) * 1965-06-14 1967-09-26 Westinghouse Electric Corp Structures for semiconductor integrated circuits and methods of forming them
US3407479A (en) * 1965-06-28 1968-10-29 Motorola Inc Isolation of semiconductor devices
US3745984A (en) * 1971-12-27 1973-07-17 Gen Motors Corp Purge control valve and system
US4400870A (en) * 1980-10-06 1983-08-30 Texas Instruments Incorporated Method of hermetically encapsulating a semiconductor device by laser irradiation
JPS624351A (en) * 1985-06-29 1987-01-10 Toshiba Corp Manufacture of semiconductor carrier
FR2599893B1 (en) * 1986-05-23 1996-08-02 Ricoh Kk METHOD FOR MOUNTING AN ELECTRONIC MODULE ON A SUBSTRATE AND INTEGRATED CIRCUIT CARD
US4882614A (en) * 1986-07-14 1989-11-21 Matsushita Electric Industrial Co., Ltd. Multiplex signal processing apparatus
JP2579937B2 (en) * 1987-04-15 1997-02-12 株式会社東芝 Electronic circuit device and method of manufacturing the same
JPH03155144A (en) * 1989-11-13 1991-07-03 Sharp Corp Mounting method for bare semiconductor ic chip
US5111278A (en) * 1991-03-27 1992-05-05 Eichelberger Charles W Three-dimensional multichip module systems
US5291066A (en) * 1991-11-14 1994-03-01 General Electric Company Moisture-proof electrical circuit high density interconnect module and method for making same
US5324687A (en) * 1992-10-16 1994-06-28 General Electric Company Method for thinning of integrated circuit chips for lightweight packaged electronic systems
US5422513A (en) * 1992-10-16 1995-06-06 Martin Marietta Corporation Integrated circuit chip placement in a high density interconnect structure
EP0604005A1 (en) * 1992-10-26 1994-06-29 Texas Instruments Incorporated Device packaged in a high interconnect density land grid array package having electrical and optical interconnects
US6274391B1 (en) * 1992-10-26 2001-08-14 Texas Instruments Incorporated HDI land grid array packaged device having electrical and optical interconnects
US5300461A (en) * 1993-01-25 1994-04-05 Intel Corporation Process for fabricating sealed semiconductor chip using silicon nitride passivation film
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5306670A (en) * 1993-02-09 1994-04-26 Texas Instruments Incorporated Multi-chip integrated circuit module and method for fabrication thereof
US5422514A (en) * 1993-05-11 1995-06-06 Micromodule Systems, Inc. Packaging and interconnect system for integrated circuits
US5353195A (en) * 1993-07-09 1994-10-04 General Electric Company Integral power and ground structure for multi-chip modules
US5397921A (en) * 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
US5563664A (en) * 1994-01-05 1996-10-08 Samsung Electronics Co., Ltd. Pre-frame-comb as well as pre-line-comb partial-response filtering of BPSK buried in a TV signal
US5527741A (en) * 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
US5745984A (en) * 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
US5821608A (en) * 1995-09-08 1998-10-13 Tessera, Inc. Laterally situated stress/strain relieving lead for a semiconductor chip package
US5696666A (en) * 1995-10-11 1997-12-09 Motorola, Inc. Low profile exposed die chip carrier package
US6404049B1 (en) * 1995-11-28 2002-06-11 Hitachi, Ltd. Semiconductor device, manufacturing method thereof and mounting board
US5567657A (en) * 1995-12-04 1996-10-22 General Electric Company Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
JPH1084014A (en) * 1996-07-19 1998-03-31 Shinko Electric Ind Co Ltd Manufacture of semiconductor device
JP2982729B2 (en) * 1997-01-16 1999-11-29 日本電気株式会社 Semiconductor device
US5894108A (en) * 1997-02-11 1999-04-13 National Semiconductor Corporation Plastic package with exposed die
KR100237328B1 (en) * 1997-02-26 2000-01-15 김규현 Structure of semiconductor package and manufacturing method
US5889654A (en) * 1997-04-09 1999-03-30 International Business Machines Corporation Advanced chip packaging structure for memory card applications
US5977639A (en) * 1997-09-30 1999-11-02 Intel Corporation Metal staples to prevent interlayer delamination
US6025995A (en) * 1997-11-05 2000-02-15 Ericsson Inc. Integrated circuit module and method
JPH11233678A (en) * 1998-02-16 1999-08-27 Sumitomo Metal Electronics Devices Inc Manufacture of ic package
US6180881B1 (en) * 1998-05-05 2001-01-30 Harlan Ruben Isaak Chip stack and method of making same
US6130472A (en) * 1998-07-24 2000-10-10 International Business Machines Corporation Moisture and ion barrier for protection of devices and interconnect structures
US6396136B2 (en) * 1998-12-31 2002-05-28 Texas Instruments Incorporated Ball grid package with multiple power/ground planes
US6127833A (en) * 1999-01-04 2000-10-03 Taiwan Semiconductor Manufacturing Co. Test carrier for attaching a semiconductor device
US6306680B1 (en) * 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6117704A (en) * 1999-03-31 2000-09-12 Irvine Sensors Corporation Stackable layers containing encapsulated chips
US6288905B1 (en) * 1999-04-15 2001-09-11 Amerasia International Technology Inc. Contact module, as for a smart card, and method for making same
US6239482B1 (en) * 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
KR100333388B1 (en) * 1999-06-29 2002-04-18 박종섭 chip size stack package and method of fabricating the same
US6221694B1 (en) * 1999-06-29 2001-04-24 International Business Machines Corporation Method of making a circuitized substrate with an aperture
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) * 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
JP3813402B2 (en) * 2000-01-31 2006-08-23 新光電気工業株式会社 Manufacturing method of semiconductor device
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6423570B1 (en) * 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby

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EP1354354A2 (en) 2003-10-22
CN1555573A (en) 2004-12-15
JP2005506678A (en) 2005-03-03
WO2002047162A2 (en) 2002-06-13
KR20040014432A (en) 2004-02-14
WO2002047162A3 (en) 2003-08-07
US20020070443A1 (en) 2002-06-13

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