CN100418211C - Semiconductor device and method of fabricating the same - Google Patents
Semiconductor device and method of fabricating the same Download PDFInfo
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- CN100418211C CN100418211C CNB200480022204XA CN200480022204A CN100418211C CN 100418211 C CN100418211 C CN 100418211C CN B200480022204X A CNB200480022204X A CN B200480022204XA CN 200480022204 A CN200480022204 A CN 200480022204A CN 100418211 C CN100418211 C CN 100418211C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
A semiconductor device includes a base plate, and a semiconductor constituent body formed on the base plate. The semiconductor constituent body has a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constituent body. A hard sheet is formed on the insulating layer. An interconnection is connected to the external connecting electrodes of the semiconductor constituent body.
Description
Technical field
The present invention relates to the method for a kind of semiconductor device and this device of manufacturing.
Background technology
Disclosed conventional semiconductor device comprises that soldered ball is as the splicing ear outside the semiconductor chip with preliminary dimension in Japanese patent application KOKAI NO.2003-298005.Therefore, this semiconductor device has such structure, and wherein semiconductor chip has a plurality of connection pads on the surface thereon and is formed on the upper surface of substrate.Insulating barrier is formed on the upper surface of substrate round semiconductor chip.Upper nonconductive Film forms on the upper surface of semiconductor chip and insulating barrier, upper interconnect forms on the upper surface of upper nonconductive Film, so that be connected to the connection pads of semiconductor chip, the part except the pad portion that is used to connect upper interconnect is covered by the dielectric film of the superiors.Soldered ball forms on the connection pads part of upper interconnect respectively.
For example, the manufacture process of above-mentioned conventional semiconductor device is as described below.In order to increase productivity ratio, a plurality of semiconductor chips are arranged on the upper surface of substrate discretely, and this substrate has the area that can form a plurality of complete semiconductor device.Insulating barrier is formed on the upper surface of substrate round semiconductor chip.Upper nonconductive Film forms on the upper surface of semiconductor chip and insulating barrier.Upper interconnect forms on the upper surface of upper nonconductive Film, so that be electrically connected to the connection pads of semiconductor chip.Part except the pad portion that is used to connect upper interconnect is covered by the topmost dielectric film.On the connection pads part of upper interconnect, form soldered ball.Between semiconductor chip, substrate, insulating barrier, upper nonconductive Film and topmost dielectric film are cut, obtain a plurality of above-mentioned conventional semiconductor device thus.
In the method, semi-conductor device manufacturing method of this routine, by thermmohardening with shrink on the insulating barrier cambium layer upper surface of base plate and form insulating barrier round semiconductor chip, for example make by epoxy and polyimide-based resin by unhardened resin for this insulating barrier cambium layer.Therefore, substrate is warpage largely, and this has hindered the execution of subsequent step, has reduced the processing accuracy in the subsequent step.For example, when the substrate with the area that can form a plurality of completed semiconductor devices was of a size of 300mm * 250mm, the amount of warpage of this substrate can reach 13 to 15mm.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of method that can reduce the semiconductor device of substrate warp and make this device.
In order to achieve the above object, hardboard is placed on the insulating barrier cambium layer, this insulating barrier cambium layer is formed on the substrate and by the material that comprises semi-harden at least resin or liquid resin and makes, and forms insulating barrier by the semi-harden resin or the liquid resin that heat and push in the insulating barrier cambium layer that hardens fully.
In the present invention, hardboard is placed on and is formed on the substrate and comprises on the insulating barrier cambium layer of semi-harden resin or liquid resin.Therefore, in this, the material setting on the thickness direction is symmetrical basically.Therefore, when applying heat and pressure, the insulating barrier cambium layer substantially symmetrically hardens on thickness direction and shrinks.Therefore, can reduce the warpage of substrate.
Additional objects and advantages of this invention will be elaborated in the following description, and part is understood by illustrating apparent or putting into practice by the present invention.Objects and advantages of the present invention can realize and obtain by means of means that hereinafter particularly point out and combination.
The accompanying drawing summary
Included and accompanying drawing that constituted the part of specification is for example understood embodiments of the invention, and is used from together with the detailed description one of top total description and the embodiment that hereinafter provides principle of the present invention is described.
Fig. 1 is the sectional view according to the semiconductor device of first embodiment of the invention;
Fig. 2 is the sectional view that is illustrated in the initial material of preparing in the example of method of manufacturing semiconductor device as shown in Figure 1;
Fig. 3 is the sectional view of the assembly in Fig. 2 step afterwards;
Fig. 4 is the sectional view of the assembly in Fig. 3 step afterwards;
Fig. 5 is the sectional view of the assembly in Fig. 4 step afterwards;
Fig. 6 is the sectional view of the assembly in Fig. 5 step afterwards;
Fig. 7 is the sectional view of the assembly in Fig. 6 step afterwards;
Fig. 8 is the sectional view of the assembly in Fig. 7 step afterwards;
Fig. 9 is the sectional view of the assembly in Fig. 8 step afterwards;
Figure 10 is the sectional view of the assembly in Fig. 9 step afterwards;
Figure 11 is the sectional view of the assembly in Figure 10 step afterwards;
Figure 12 is the sectional view of the assembly in Figure 11 step afterwards;
Figure 13 is the sectional view of the assembly in Figure 12 step afterwards;
Figure 14 is the sectional view of the assembly in Figure 13 step afterwards;
Figure 15 is the sectional view of the assembly in Figure 14 step afterwards;
Figure 16 is the sectional view of the assembly in Figure 15 step afterwards;
Figure 17 is the sectional view of the assembly in Figure 16 step afterwards;
Figure 18 is the sectional view that is used for explaining the assembly in the predetermined process of second embodiment of the invention;
Figure 19 is the sectional view that is used for explaining the assembly in the predetermined process of third embodiment of the invention;
Figure 20 is the sectional view that is used for explaining the assembly in the predetermined process of fourth embodiment of the invention;
Figure 21 is the sectional view of the assembly in Figure 20 step afterwards;
Figure 22 is the sectional view that is used for explaining the assembly in the predetermined process of fifth embodiment of the invention;
Figure 23 is the sectional view that is used for explaining the assembly in the predetermined process of sixth embodiment of the invention;
Figure 24 is the sectional view according to the semiconductor device of seventh embodiment of the invention;
Figure 25 is the sectional view according to the semiconductor device of eighth embodiment of the invention;
Figure 26 is the sectional view according to the semiconductor device of ninth embodiment of the invention;
Figure 27 is the sectional view according to the semiconductor device of tenth embodiment of the invention;
Figure 28 is the sectional view according to the semiconductor device of eleventh embodiment of the invention;
Figure 29 is the sectional view according to the semiconductor device of the 12nd embodiment of the present invention; And
Figure 30 is the sectional view according to the semiconductor device of thirteenth embodiment of the invention.
Preferred forms
First embodiment
Fig. 1 is the sectional view according to the semiconductor device of first embodiment of the invention.This semiconductor device comprises the substrate 1 of square even shape.Substrate 1 is made by the material that is used as printed circuit board (PCB) usually.This examples of material be by inorganic material for example glass cloth, glass fibre or aramid fibre make and injected for example substrate of epoxy, polyimide-based resin or BT (bismaleimides-triazine) resin of thermosetting resin, and thermosetting resin epoxy for example.
Have square even shape and size and be attached to the upper surface of substrate 1 than the lower surface of the little semiconductor structure bodies 2 to a certain degree of the size of substrate 1 by the adhesive linkage of making by the die bonding material 3.Semiconductor structure bodies 2 has interconnection 11, cylindrical electrode 12 and wrap film 13 (all these will be explained in the back), and is called CSP (chip size packages) usually.Because independently semiconductor structure bodies 2 obtains by cutting after interconnection 11, cylindrical electrode 12 and wrap film 13 form on silicon wafer, this will be explained below, so semiconductor structure bodies 2 also is called silicon chip level CSP (W-CSP) especially.The structure of semiconductor structure bodies 2 will make an explanation below.
By insulating material for example the diaphragm 8 made of epoxy or polyimide-based resin be formed on the upper surface of dielectric film 6.Diaphragm 8 corresponding to those parts in the hole in the dielectric film 67 in form hole 9.The metal undercoating of being made by copper etc. 10 is formed on the upper surface of diaphragm 8.Copper-connection 11 is formed directly on the entire upper surface of metal undercoating 10.An end of metal undercoating 10 and interconnect thus and 11 be electrically connected to the end of connection pads 5 by hole 7 and 9.
The cylindrical electrode that is made of copper (external connecting electrode) 12 is formed on the upper surface of connection pads part or 11 the other end of interconnecting.By insulating material for example, the wrap film 13 that epoxy or polyimide-based resin are made is formed on the upper surface of diaphragm 8 and interconnection 11, makes the upper surface of wrap film 13 concordant with the upper surface of cylindrical electrode 12 like this.As mentioned above, be called the semiconductor structure bodies 2 of W-CSP, comprise silicon substrate 4, connection pads 5 and dielectric film 6, and comprise diaphragm 8, interconnection 11, cylindrical electrode 12 and wrap film 13.
Square box shape insulating barrier 14 is formed on the upper surface of substrate 1 round semiconductor structure bodies 2.Insulating barrier 14 is commonly referred to preimpregnation material, it is to comprise inorganic material, for example glass cloth, glass fibre or aramid fibre and injected thermosetting resin, for example substrate of epoxy, polyimide-based resin or BT (bismaleimides-triazine) resin.The hard sheet 15 of square box shape is buried in the periphery of the upper surface of insulating barrier 14.The material of hard sheet 15 and thickness are identical with substrate 1.Insulating barrier 14 is concordant with the upper surface of semiconductor structure bodies 2 basically with the upper surface of hard sheet 15.
On the upper surface of semiconductor structure bodies 2, insulating barrier 14 and hard sheet 15, form upper nonconductive Film 16 to have smooth upper surface.Upper nonconductive Film 16 is commonly referred to build-up materials, is used for piling up substrate, and by at thermosetting resin, for example disperses reinforcing material for example fiber or filler and form in epoxy, polyimide-based resin or the BT resin.Fiber for example is glass fibre or aramid fibre.Filler for example is silica filler or ceramic base filler.
In upper face center those parts partly of upper nonconductive Film 16, form hole 17 corresponding to cylindrical electrode 12.The last metal undercoating of being made by copper etc. 18 is formed on the upper surface of upper nonconductive Film 16.The upper interconnect 19 that is made of copper is formed on the entire upper surface of metal undercoating 18.An end of last metal undercoating 18, and interconnect thus and 19 be electrically connected to the upper surface of cylindrical electrode 12 by the hole in the upper nonconductive Film 16 17.
The uppermost 20 that is formed by solder resist (solder resist) etc. is formed on the upper surface of upper nonconductive Film 16 and upper interconnect 19.In connection pads those parts partly of uppermost 20, form through hole 21 corresponding to upper interconnect 19.Soldered ball 22 the inside in hole 21 and above formation so that electricity and be mechanically connected to the connection pads part of upper interconnect 19.Soldered ball 22 is arranged to matrix on uppermost 20, and some or all soldered balls are positioned at the outside of semiconductor structure bodies 2.
Be formed on the lower surface of substrate 1 by the following dielectric film made from upper nonconductive Film 16 identical materials 23.Be formed on down on the lower surface of dielectric film 23 by the orlop dielectric film made from uppermost 20 identical materials 24.
As mentioned above, for the size in the formation district that makes soldered ball 22 according to the increase of connection pads 5 quantity on the silicon substrate 4 and than the size of semiconductor structure bodies 2 greatly to a certain degree, the size that makes substrate 1 is than the size of semiconductor structure bodies 2 greatly to a certain degree.This makes the size of connection pads part (part in the hole 21 of uppermost 20) of upper interconnect 19 and spacing size and the spacing greater than cylindrical electrode 12.
Therefore, not only in zone, and in, form those connection pads parts of being arranged to matrix of upper interconnect 19 corresponding to the zone of the insulating barrier 14 that is formed on semiconductor structure bodies 2 lateral outer corresponding to semiconductor structure bodies 2.That is to say that in the soldered ball 22 of being arranged to matrix, outmost at least soldered ball 22 is formed on the periphery that is arranged in semiconductor structure bodies 2 outsides.
To introduce an example of the method for making this semiconductor device below.The example of the manufacture method of semiconductor structure bodies 2 at first, is described.In this method, preparation assembly as shown in Figure 2.In this assembly, on the silicon substrate (Semiconductor substrate) 4 of wafer-like, form the connection pads 5 for example make, the dielectric film of for example making by silica 6 and the diaphragm of for example making 8 by epoxy or polyimide-based resin by aluminium based metal.By the hole 7 and 9 that forms in dielectric film 6 and the diaphragm 8 middle body of connection pads 5 is come out.In wafer-like silicon substrate 4, in the zone that will form each semiconductor structure bodies, form integrated circuit, and each connection pads 5 is electrically connected to the integrated circuit that forms in the corresponding zone with predetermined function with this structure.
As shown in Figure 3, on the entire upper surface of the diaphragm 8 that comprises the upper surface that connection pads 5 exposes by hole 7 and 9, form metal undercoating 10.The copper layer that metal undercoating 10 can be the copper layer that forms by plated by electroless plating, form by sputter, and the film of the titanium that forms by sputter etc. and be formed on any in the combination of the copper layer on this film by sputter.
Form platedresist film 31 by composition on the upper surface of metal undercoating 10.In platedresist film 31, in part, formed hole 32 corresponding to the zone that will form interconnection 11.Then by utilizing metal undercoating 10 to carry out the plated by electroless plating of copper as the electroplating current path, thus in the hole 32 of platedresist film 31, on the upper surface of metal undercoating 10, form interconnection 11.After this, remove platedresist film 31.
As shown in Figure 4, form platedresist film 33 by composition on the upper surface of metal undercoating 10 and interconnection 11.In platedresist film 33, in corresponding to the part in the zone that will form cylindrical electrode 12, formed hole 34.Then by utilizing metal undercoating 10 to carry out the plated by electroless plating of copper, thus in the hole 34 of platedresist film 33, on the upper surface of the connection pads part of interconnection 11, form cylindrical electrode 12 as the electroplating current path.After this, remove platedresist film 33, and, etch away the unwanted part of metal undercoating 10 by using interconnection 11 as mask.Therefore, as shown in Figure 5, only metal undercoating 10 keeps below interconnection 11.
As shown in Figure 6; be coated with (die coating) by for example silk screen printing, spin coating or mould and on diaphragm 8, cylindrical electrode 12 and 11 the entire upper surface of interconnecting, form and make wrap film 13, make the thickness of wrap film 13 greater than the height of cylindrical electrode 12 by epoxy or polyimide-based resin.Therefore, in this state, be wrapped film 13 of the upper surface of cylindrical electrode 12 covers.
As shown in Figure 7, suitably polish the upper surface of wrap film 13 and cylindrical electrode 12, exposing the upper surface of cylindrical electrode 12, and planarization comprises the upper surface of wrap film 13 of those upper surfaces that come out of cylindrical electrode 12.Upper surface to cylindrical electrode 12 so suitably polishes, so that make the height of cylindrical electrode 12 even by the difference in height of eliminating the cylindrical electrode 12 that plated by electroless plating forms.
As shown in Figure 8, adhesive linkage 3 is attached to the whole lower surface of silicon substrate 4.Adhesive linkage 3 by the die bonding material for example epoxy or polyimide-based resin make, and under semi-harden state, be attached to silicon substrate 4 by heating and pressurization.Then, the adhesive linkage 3 that adheres to silicon substrate 4 is attached to cutting belt (dicing tape) and goes up (not shown).After carrying out cutting step shown in Figure 9, remove tack coat 3 from cutting belt.Therefore, as shown in Figure 1, obtained a plurality of semiconductor structure bodies 2, each semiconductor structure bodies 2 all has adhesive linkage 3 at the lower surface of silicon substrate 4.
The semiconductor structure bodies 2 that so obtains has adhesive linkage 3 on the lower surface of silicon substrate 4.This has eliminated after the cutting step the very operation of trouble that forms adhesive linkage on the lower surface of the silicon substrate 4 of each semiconductor structure bodies 2.Notice that it is more much easier than the operation at the lower surface formation adhesive linkage of the silicon substrate 4 of each semiconductor structure bodies 2 cutting step after to remove this operation of adhesive linkage from cutting belt after the cutting step.
To introduce below by using the semiconductor structure bodies 2 that so obtains to make an example of the method for semiconductor device shown in Figure 1.At first, as shown in figure 10, preparation substrate 1, its area can form a plurality of complete semiconductor device as shown in Figure 1.Substrate 1 for example has square even shape, although its shape is not limited to this shape.By with thermosetting resin for example epoxy inject the substrate for example forms by glass cloth, and by the thermosetting resin that hardens resulting substrate-like is become plate and forms substrate 1.
Be attached to the adhesive linkage 3 of lower surface of the silicon substrate 4 of semiconductor structure bodies 2 separately, be attached to a plurality of predetermined portions on the upper surface of substrate 1.In this attaching process, adhesive linkage 3 is hardened fully by heating and pressurization.After this, when by location such as pins, two trellis insulating barriers form plate (insulating barrier cambium layer) 14a and 14b and lattice-like hard sheet 15 and are stacked on the upper surface of substrate 1 round semiconductor structure bodies 2.Note also can after stacked these two insulating barriers form plate 14a and 14b and hardboard 15, semiconductor structure bodies 2 being set.
By with thermosetting resin for example epoxy inject the substrate that forms by for example glass cloth, semi-harden thermosetting resin (in the B stage) to be forming tabular preimpregnation material, and by for example punching, boring or excavate (rooter) and handle and form a plurality of square openings 35 and obtain the trellis insulating barrier and form plate 14a and 14b.The material of lattice-like hard sheet 15 and thickness are identical with substrate 1.Lattice-like hard sheet 15 is to form a plurality of square openings 36 by for example punching, boring or excavation processing in the thermosetting resin plate of sclerosis to obtain.
Although the plate of insulating barrier formation in the present embodiment 14a has identical thickness with 14b, their thickness also can be different.In addition, as mentioned above, the number that insulating barrier forms plate is two, but also can be one or three or more.Key is by making with substrate 1 identical materials, that is, 15 needs of hardboard with the thermal coefficient of expansion identical with substrate 1 and identical thickness are stacked on the upper surface that insulating barrier forms plate.
Then, as shown in figure 11, a pair of heat/ pressure plate 38 and 39 be used for from top and below, insulating barrier is formed plate 14a and 14b and hardboard 15 heats and pressurize.As a result, the thermosetting resin of the fusing among insulating barrier formation plate 14a and the 14b is extruded and is filled in the gap shown in Figure 10 37.When after when cooling off, around each semiconductor structure bodies 2, on the upper surface of substrate 1, form insulating barrier 14.
On the other hand, hardboard 15 is not distortion in heating and pressurization, because the sclerosis in advance of the thermosetting resin in the hardboard 15, and is buried in the presumptive area on the upper surface of insulating barrier 14 (except gap shown in Figure 10 37).In this state, the upper surface of insulating barrier 14 and hardboard 15 is concordant with the upper surface of semiconductor structure bodies 2 basically.If necessary, can remove the 37 unnecessary thermosetting resins of giving prominence to from the gap shown in Figure 10 by soft material (buff) polishing or similar fashion.Note always not needing to bury hardboard 15 so that the upper surface of the upper surface of its upper surface and insulating barrier 14 or semiconductor structure bodies 2 is concordant.
As shown in figure 10, when cooling with fully when hardening, be stacked on that insulating barrier on the upper surface of substrate 1 forms plate 14a and 14b shrinks, because they are from semi-harden state fusing and sclerosis.Therefore, do not form on the plate 14b if hardboard 15 is formed on insulating barrier, then substrate 1 can cause big warpage.Yet, in the present invention, form at the insulating barrier that is stacked on substrate 1 upper surface and to form hardboard 15 on plate 14a and the 14b, and substrate 1 and hardboard 15 harden in advance.Therefore, even also shrinking, heating and pressurizing do not take place.In addition, substrate 1 and hardboard 15 are made by identical materials, and just they have identical thermal coefficient of expansion and identical thickness, so be symmetrical in this part, material setting on thickness direction.Therefore, substrate 1 and hardboard 15 bear by insulating barrier and form the identical stress that the contraction of plate 14a and 14b causes.Therefore, the warpage of substrate 1 is eliminated or has alleviated.This makes subsequent step to carry out smoothly, and has guaranteed processing accuracy high in the subsequent step.Notice that the warpage of substrate 1 can eliminate or alleviate by the way, though when substrate 1 and hardboard 15 by forming plate 14a with insulating barrier and the 14b identical materials is made.In this case, do not enter this material from the material of semi-harden state by heat fused, that is, in advance in Ying Hua the hardboard 15.Cooling off and fully after the sclerosis substrate 1 and form down border between the plate 14a, and hardboard 15 and go up the border that forms between the plate 14b and significantly remain.
In addition, if do not use hardboard 15, then the gross thickness of insulating barrier formation plate 14a and 14b must increase the amount corresponding to the volume of hardboard 15.As a result, the insulating barrier upper surface that forms plate 14b becomes than the upper surface height of semiconductor structure bodies 2 to a certain degree.This has increased the amount of the molten resin of the upper surface that moves to semiconductor structure bodies 2.And if the thermosetting resin that forms among plate 14a and the 14b melts, the pressure that is applied on this thermosetting resin becomes inhomogeneous.As a result, the resin flows of fusing, and the problems referred to above worsen.
On the contrary, when using hardboard 15, the gross thickness of insulating barrier formation plate 14a and 14b can reduce the amount corresponding to the volume of hardboard 15.And because pressure is applied on the hardboard 15 equably, even the thermosetting resin fusing therefore in these plates, it also is uniform being applied to the pressure that forms plate 14a and 14b.In addition, even the thermosetting resin that forms among plate 14a and the 14b has melted, hardboard 15 also can maintain the resin of this fusing, and suppresses flowing of molten resin.This feasible amount that can reduce the molten resin of the upper surface that moves to semiconductor structure bodies 2 well.
As shown in figure 12, upper nonconductive Film forms plate 16a and is formed on the upper surface of semiconductor structure bodies 2, insulating barrier 14 and hardboard 15, and dielectric film formation plate 23a is formed on the lower surface of substrate 1 down.Upper nonconductive Film forms plate 16a and following dielectric film formation plate 23a is preferably made by tabular accumulation material, although to they not restrictions.This accumulation material is by in thermosetting resin mixed silica filler in the epoxy for example, and semi-harden this thermosetting resin obtains.
Then, a pair of heat/pressure plate (not shown) be used for from top and below upper nonconductive Film is formed plate 16a and following dielectric film formation plate 23a heat and pressurize.Thereby upper nonconductive Film 16 is formed on the upper surface of semiconductor structure bodies 2, insulating barrier 14 and hardboard 15, and dielectric film 23 is formed on the lower surface of substrate 1 down.
In this case, upper and lower dielectric film forms plate 16a and 23a is made by identical materials, and therefore has identical thermal coefficient of expansion.Therefore, if these two plates have identical thickness, then in the part of insulating barrier 14, the material setting is symmetrical on thickness direction.Therefore, when heating and pressurize, upper nonconductive Film formation plate 16a and following dielectric film formation plate 23a harden symmetrically on thickness direction and shrink, thereby the warpage of substrate 1 has just reduced.This makes subsequent step to carry out smoothly, and has guaranteed processing accuracy high in the subsequent step.
And the upper surface of upper nonconductive Film 16 is flattened, because by the lower surface of last heat/pressure plate (not shown) pressurizeed in this surface.The lower surface of following dielectric film 23 also is flattened, and the upper surface of heat/pressure plate (not shown) pressurizes to this surface because pass through down.This has just saved the demand for the polishing step of the lower surface of the upper surface of planarization upper nonconductive Film 16 and following dielectric film 23.
Notice, form plate 16a and 23a as upper and lower dielectric film, can also use by with thermosetting resin for example epoxy inject the substrate that forms by for example glass cloth, and the preimpregnation material that this thermosetting resin semihard is changed into plate and obtain only perhaps uses the panel material of being made by the thermosetting resin of flinty soil filler not.
As shown in figure 13, use the laser treatment give off laser beam to form holes 17 in those parts of upper nonconductive Film 16 corresponding to the middle body of cylindrical electrode 12 upper surfaces.Then, if necessary, remove the epoxy that occurs in 17 grades of hole and defile etc. by removing technology.
As shown in figure 14, on the upper surface that exposes by hole 17 with cylindrical electrode 12 on the entire upper surface of upper nonconductive Film 16, form metal undercoating 18 by for example electroless plating copper.Form anti-plate film 41 by on the upper surface of last metal undercoating 18, carrying out patterning then.In this state, the part corresponding to the formation district of upper interconnect 19 at anti-plate film 41 forms hole 42.
Then by using metal undercoating 18 to carry out electroless plating copper as the electroplating current path, thus in the hole 42 of anti-plate film 41, on the upper surface of last metal undercoating 18 formation upper interconnect 19.Afterwards, remove anti-plate film 41, and by using upper interconnect 19 to etch away the unessential part of metal undercoating 18 as mask.Therefore, as shown in figure 15,18 of last metal undercoating are retained under the upper interconnect 19.
As shown in figure 16, for example use silk screen printing or be spin-coated on upper nonconductive Film 16 and the upper surface of upper interconnect 19 on form soldering-resistance layer 20a, and form soldering-resistance layer 24a at the lower surface of dielectric film 23 down.When after when heating, on the upper surface of dielectric film 16 and upper interconnect 19, form uppermost 20, and form orlop dielectric film 24 at the lower surface of dielectric film 23 down.
In this structure, be respectively applied for the soldering-resistance layer 20a and the 24a that form uppermost 20 and orlop dielectric film 24 and make, and therefore have identical thermal coefficient of expansion by identical materials.Therefore, if the thickness of soldering- resistance layer 20a and 24a is also identical, then the material setting in the part of insulating barrier 14, on thickness direction is symmetrical.As a result, be respectively applied for the soldering-resistance layer 20a that forms uppermost 20 and orlop dielectric film 24 and 24a and on thickness direction, harden symmetrically and shrink, so the warpage of substrate 1 has reduced.This makes subsequent step to carry out smoothly, and has guaranteed processing accuracy high in the subsequent step.
Then, form holes 21 in uppermost 20 corresponding to those parts of the connection pads of upper interconnect 19 part by photoetching.Form soldered ball 22 in hole 21 and on the hole 21, so that its connection pads with upper interconnect 19 partly is electrically connected.
As shown in figure 17, between semiconductor structure bodies adjacent one another are 2, uppermost 20, upper nonconductive Film 16, hardboard 15, insulating barrier 14, substrate 1, following dielectric film 23 and orlop dielectric film 24 are cut.By this way, obtain a plurality of semiconductor device as shown in Figure 1.
In each semiconductor device that obtains like this, by make with substrate 1 identical materials and have with the hardboard 15 of substrate 1 same thickness and substrate 1 be respectively formed at the top of insulating barrier 14 and below, upper nonconductive Film 16 and by make with upper nonconductive Film 16 identical materials and have following dielectric film 23 with upper nonconductive Film 16 basic identical thickness be respectively formed at hardboard 15 top and substrate 1 below, and uppermost 20 and by make with uppermost 20 same materials and have orlop dielectric film 24 with uppermost 20 basic identical thickness be respectively formed at the top of upper nonconductive Film 16 and following dielectric film 23 below.Therefore, in this section in, the material setting is basic symmetry on thickness direction, this makes total be difficult to produce warpage.
In above-mentioned manufacture method, a plurality of semiconductor structure bodies 2 are arranged on the substrate 1 by adhesive linkage 3, and upper interconnect 19 and soldered ball 22 form jointly with respect to semiconductor structure bodies 2, and resulting then structure is cut into a plurality of semiconductor device.Therefore, manufacturing step can be simplified.In addition, a plurality of semiconductor structure bodies 2 can shift from manufacturing step shown in Figure 11 together with substrate 1.This has also simplified manufacturing step.
Second embodiment
Figure 18 is the sectional view of assembly that is used for explaining the predetermined process of second embodiment of the invention.In first embodiment, after step shown in Figure 10, form insulating barrier 14 and hardboard 15 as shown in figure 11, and form upper nonconductive Film 16 and following dielectric film 23 as shown in figure 12.
On the contrary, in the second embodiment of the present invention, after step shown in Figure 10, on the upper surface of hardboard 15, form upper nonconductive Film and form plate 16a, and dielectric film forms plate 23a under forming on the lower surface of substrate 1, as shown in figure 18.Then, a pair of heat/pressure plate be used for as shown in figure 12 from top and below resulting structure is carried out heating and pressurizing, thereby form insulating barrier 14, hardboard 15, upper nonconductive Film 16 and following dielectric film 23 simultaneously.Therefore, in this embodiment, can make the number of heat/pressure step be less than first embodiment.
When using hardboard 15 as mentioned above, can reduce the amount of the molten resin of the upper surface that moves to semiconductor structure bodies 2 well.Therefore, when insulating barrier 14, hardboard 15, upper nonconductive Film 16 and following dielectric film 23 formed simultaneously, the amount of molten resin of upper surface that moves to semiconductor structure bodies 2 was considerably less.Therefore, on semiconductor structure bodies 2, can make the thickness of the upper nonconductive Film 16 that comprises mobile molten resin even basically.This has promoted to form as shown in figure 13 the laser treatment in hole 17 in upper nonconductive Film 16.In other words, become easily owing in upper nonconductive Film 16, form the laser treatment in hole 17, so insulating barrier 14, hardboard 15, upper nonconductive Film 16 and following dielectric film 23 can form simultaneously.
The 3rd embodiment
Figure 19 is the sectional view of assembly that is used for explaining the predetermined process of third embodiment of the invention.In first embodiment, as shown in figure 10, two trellis insulating barriers form plate 14a and 14b and lattice-like hard sheet 15 and are stacked on the upper surface of substrate 1 round semiconductor structure bodies 2.
On the contrary, in the third embodiment of the present invention, as shown in figure 19,, on the upper surface of substrate 1, form the insulating barrier cambium layer 14c that makes by the material that comprises liquid thermosetting resin at least round semiconductor structure bodies 2 by for example silk screen printing or spin coating.Then, lattice-like hard sheet 15 is placed on the upper surface of insulating barrier cambium layer 14c.
Subsequently, upper nonconductive Film is formed on the upper surface that plate 16a is placed on hardboard 15, and will descend dielectric film to form plate 23a to be placed on the lower surface of substrate 1.Afterwards, a pair of heat/pressure plate be used for as shown in figure 11 from top and below resulting structure is carried out heating and pressurizing, thereby form insulating barrier 14, hardboard 15, upper nonconductive Film 16 and following dielectric film 23 simultaneously.Therefore, in this embodiment, can make the number of heat/pressure step be less than first embodiment.
The 4th embodiment
Figure 20 is the sectional view of assembly that is used for explaining the predetermined process of fourth embodiment of the invention.In first embodiment, as shown in figure 10, the insulating barrier of two trellis forms plate 14a and 14b and lattice-like hard sheet 15 and is stacked on the upper surface of substrate 1 round semiconductor structure bodies 2.
On the contrary, in the fourth embodiment of the present invention, as shown in figure 20, by for example silk screen printing or spin coating, with the upper surface of the material coating hardboard 15 that comprises liquid thermosetting resin at least, and integrally form insulating barrier cambium layer 14d by semi-harden this thermosetting resin.
Then, as shown in figure 21, handle formation a plurality of rectangular through- hole 35a and 36 in insulating barrier cambium layer 14d and hardboard 15, thereby insulating barrier cambium layer 14d and hardboard 15 are formed trellis by for example punching, boring or excavation.Afterwards, as shown in figure 10, the structure shown in Figure 20 is inverted, and is placed on round semiconductor structure bodies 2 on the upper surface of substrate 1.Therefore, in this embodiment, can make the number of steps that insulating barrier cambium layer 14d and hardboard 15 are set be less than first embodiment.
The 5th embodiment
Figure 22 is the sectional view of assembly that is used for explaining the predetermined process of fifth embodiment of the invention.In first embodiment, as shown in figure 10, a hardboard 15 is placed on insulating barrier forms on the plate 14b.On the contrary, in the fifth embodiment of the present invention, as shown in figure 22, another hardboard 15b is inserted two insulating barriers with same thickness form between plate 14a and the 14b.Just, the insulating barrier formation plate that even number has same thickness is stacked up, and another hardboard is inserted between the adjacent plate, so that be symmetrical on thickness direction.As a result, it is symmetrical can making the material setting in this part, on thickness direction.
The 6th embodiment
Figure 23 is the sectional view of assembly that is used for explaining the predetermined process of sixth embodiment of the invention.In first embodiment, substrate 1 is made by the material that comprises thermosetting resin at least, and hardboard 15 is by making with substrate 1 identical materials, and has the thickness identical with substrate 1.On the contrary, in the sixth embodiment of the present invention, as shown in figure 23, for example use the metallic plate of making by copper or stainless steel, and hardboard 15a is by making with substrate 1a identical materials, and has the thickness identical with substrate 1a as substrate 1a.Just, substrate 1a and hardboard 15a needn't be made by the material that comprises thermosetting resin at least, and can be the metallic plates of being made by for example copper or stainless steel.For example can also use ceramic substrate or glass substrate as substrate 1 and hardboard 15.
In this embodiment, upper nonconductive Film is formed on the upper surface that plate 16a is placed on hardboard 15a, dielectric film is down formed plate 23a be placed on the lower surface of substrate 1, in the part that forms plate 14a and 14b, make the material of thickness direction that symmetry is set thus.Then, a pair of heat/pressure plate be used for from top and below resulting structure is carried out heating and pressurizing, thereby form insulating barrier 14, hardboard 15a, upper nonconductive Film 16 and following dielectric film 23 simultaneously.
Attention is in Figure 23, can also form among substrate 1a and the hardboard 15a one by using the metallic plate of making by for example copper or stainless steel, and the material that has the thermal coefficient of expansion identical with the former and comprise thermosetting resin at least by use forms another.For example, the thermal coefficient of expansion of copper is approximately 16ppm/ ℃, and stainless thermal coefficient of expansion is 16ppm/ ℃.On the other hand, the thermal coefficient of expansion of the glass cloth substrate epoxy resin of sclerosis is 10 to 20ppm/ ℃ fully.Therefore, hardboard 15 can be formed by the material that has the thermal coefficient of expansion substantially the same with substrate 1 and comprise thermosetting resin at least.
The 7th embodiment
Figure 24 is the sectional view according to the semiconductor device of seventh embodiment of the invention.This semiconductor device difference to that indicated in the drawings is on the lower surface of substrate 1 to form the orlop dielectric film of being made by solder resist 24, and does not form any by the thermosetting resin following dielectric film 23 made of epoxy for example.
With reference to Figure 11, after heating and pressurizing, the part that comprises substrate 1, is formed on semiconductor structure bodies 2 on the substrate 1, is formed on the insulating barrier 14 on the substrate 1 and is buried in the hardboard 15 in the upper surface of insulating barrier 14 round semiconductor structure bodies 2 accounts for major part on entire semiconductor device thickness direction shown in Figure 1, account for the overwhelming majority of whole hardness, and be the whole the most influential part that warpage takes place.
Therefore, even in ought semiconductor device as shown in figure 24 like that, on the lower surface of substrate 1, form the orlop dielectric film of making by solder resist 24, and do not form any by the thermosetting resin following dielectric film 23 made of epoxy for example, also can be in allowed limits with the warpage control of substrate 1.The contraction of noting solder resist is much larger than for example contraction of epoxy of thermosetting resin.Therefore, it is worthless saving the orlop dielectric film of being made by solder resist 24, although can save by the thermosetting resin following dielectric film 23 made of epoxy for example.
Just, can be broken slightly, if the warpage of substrate 1 can control within the permissible scope in the symmetry of the part of insulating barrier 14, material setting on thickness direction.Therefore, hardboard 15 can be slightly different with the thickness of substrate 1, and perhaps the thickness of the thickness of orlop dielectric film 24 and uppermost 20 can be slightly different.Instantly dielectric film 23 is not saved, and then descends the thickness of dielectric film 23 can be slightly different with the thickness of upper nonconductive Film 16.
The 8th embodiment
Figure 25 is the sectional view according to the semiconductor device of eighth embodiment of the invention.The semiconductor structure bodies 2 of this semiconductor device is that with the difference of semiconductor structure bodies 2 shown in Figure 2 cylindrical electrode 12 and wrap film 13 all not have to form, and has connection pads interconnection 11 partly and form as external connecting electrode.In this structure, comprise an end of each upper interconnect 19 of metal undercoating 18 is connected to interconnection 11 by the hole 17 that forms and the internally coated part in the hole 17 in upper nonconductive Film 16 connection pads part.
The 9th embodiment
Figure 26 is the sectional view according to the semiconductor device of ninth embodiment of the invention.The semiconductor structure bodies 2 of this semiconductor device is to form the coverlay of for example being made by epoxy or polyimide-based resin 43 with the difference of semiconductor structure bodies 2 shown in Figure 25 on the upper surface of the diaphragm 8 that comprises interconnection 11.In this structure, in connection pads those parts formation holes 44 partly of coverlay 43 corresponding to interconnection 11.An end of each upper interconnect 19 that comprises metal undercoating 18 is by being formed on the connection pads part that hole 17 in the upper nonconductive Film 16 and the hole 44 in the coverlay 43 are connected to interconnection 11.
Attention need not form hole 44 at first in coverlay 43 in semiconductor structure bodies shown in Figure 26 2.In this case, as shown in figure 13,, by the laser treatment of emission of lasering beam, in upper nonconductive Film 16 and coverlay 43, form hole 17 and 44 continuously.
The tenth embodiment
Figure 27 is the sectional view according to the semiconductor device of tenth embodiment of the invention.The semiconductor structure bodies 2 of this semiconductor device is that with the difference of semiconductor structure bodies 2 shown in Figure 26 formation is as the metal undercoating 45 and the last connection pads 46 of external connecting electrode around 44 neutralizations of the hole of coverlay 43.Comprise that connection pads 46 on each of metal undercoating 45 is connected to the connection pads part of interconnection 11.Equally, an end that comprises each upper interconnect 19 of metal undercoating 18 is connected to connection pads 46 by the hole 17 that is formed in the upper nonconductive Film 16.
Figure 25 does not have the wrap film 13 shown in Fig. 1 to the semiconductor structure bodies shown in Figure 27 2, so the upper surface of each semiconductor structure bodies 2 is subjected to mechanical damage easily.Therefore, in order to make Figure 25, use the heat/pressure step shown in Figure 18 and 19 to replace heat/pressure step shown in Figure 11 to the semiconductor device shown in Figure 27.Because upper nonconductive Film forms plate 16a and reduces pressure, therefore can reduce mechanical damage to the upper surface of semiconductor structure bodies 2.
The 11 embodiment
Figure 28 is the sectional view according to the semiconductor device of eleventh embodiment of the invention.The big difference of this semiconductor device and semiconductor device shown in Figure 1 is to form respectively on the upper and lower surface of hardboard 15 for example upper-surface interconnection 51 and the lower-surface interconnection 52 made of Copper Foil of each free metal forming.Upper-surface interconnection 51 is the ground interconnection that formed by solid pattern.Lower-surface interconnection 52 is the power supply interconnection that formed by solid pattern.
Attention is in Figure 28, and upper interconnect 51 is the ground interconnection that formed by solid pattern, also can form microstrip line construction so form the interconnection 51 and the upper interconnect on upper nonconductive Film 16 19 of this ground interconnection.The ground interconnection or the power supply interconnection that are formed by solid pattern also can only form on the upper surface of hardboard 15, so that be connected to upper interconnect 19.In addition, also common interconnection pattern can only be formed on the upper surface of hardboard 15, so that be connected to upper interconnect 19.
The 12 embodiment
Figure 29 is the sectional view according to the semiconductor device of twelveth embodiment of the invention.The big difference of this semiconductor device and semiconductor device shown in Figure 1 is to form respectively for example solid thermal radiating layer 57 and 58 made of Copper Foil of each free metal forming on the upper and lower surface of substrate 1.Note also can only on a surface of substrate 1, forming heat radiation layer.
The 13 embodiment
Figure 30 is the sectional view according to the semiconductor device of thriteenth embodiment of the invention.The big difference of this semiconductor device and semiconductor device shown in Figure 1 is that upper nonconductive Film, upper interconnect and following dielectric film are two membranes.Just, on the upper surface of the first upper nonconductive Film 16A that comprises the first upper interconnect 19A, form by the second upper nonconductive Film 16B that makes with the first upper nonconductive Film 16A identical materials.On the upper surface of the second upper nonconductive Film 16B, form the second upper interconnect 19B that comprises metal undercoating 18B.
The end of the first upper interconnect 19A that comprises metal undercoating 18A is by being formed on the upper surface that hole 17A among the first upper nonconductive Film 16A is connected to cylindrical electrode 12.The end of the second upper interconnect 19B that comprises metal undercoating 18B is by being formed on the connection pads part that hole 17B among the second upper nonconductive Film 16B is connected to the first upper interconnect 19A.Soldered ball 22 is by being formed on the connection pads part that hole 21 in the uppermost 20 is connected to the second upper interconnect 19B.
In order to reduce in the manufacture process or the warpage of substrate 1 afterwards, on the lower surface of substrate 1, form by with the first upper nonconductive Film 16A identical materials is made and thickness is identical first time dielectric film 23A, on the lower surface of first time dielectric film 23A, form by with second time dielectric film 23B that the second upper nonconductive Film 16B identical materials is made and thickness is identical, and on the lower surface of second time dielectric film 23B, form by with uppermost 20 identical materials are made and thickness is identical orlop dielectric film 24.In attention upper nonconductive Film, upper interconnect and the following dielectric film each also can comprise three layers or more multi-layered.
Another embodiment
Among described in front first embodiment, as shown in figure 17, cutting semiconductor chip between semiconductor structure bodies adjacent one another are 2.Yet two or more semiconductor structure bodies 2 also can separate as one group together, to obtain the semiconductor device of a multi-chip module.In this semiconductor device, the type that forms a plurality of semiconductor structure bodies 2 of one group can be the same or different.
Those skilled in the art will readily appreciate that other advantage and modification.Therefore, the present invention is not limited to describe here and the detail that shows and represent embodiment in broad aspect.Therefore, can under the situation of the spirit and scope that do not break away from the total inventive concept that limits by appended claims and their equivalent, make various modifications.
Claims (41)
1. semiconductor device comprises:
Substrate (1), it has upper surface and lower surface;
Semiconductor structure bodies (2) is formed on the upper surface of this substrate (1), and has Semiconductor substrate (4) and be formed on a plurality of external connecting electrodes (5,12) on this Semiconductor substrate (4);
Insulating barrier (14), it has upper surface and thickness, and it is formed on the upper surface of this substrate (1) round this semiconductor structure bodies (2);
Hardboard (15), its thickness is buried in the upper surface of this insulating barrier (14) less than the thickness of this insulating barrier (14) and its, makes the upper surface of this hardboard (15) and the upper surface of this semiconductor structure bodies (2) and the upper surface of this insulating barrier (14) form single plane;
Upper nonconductive Film (16) is formed on this semiconductor structure bodies (2) and this hardboard (15);
And interconnection (19), be formed on this upper nonconductive Film (16), and be connected to the external connecting electrode (5,12) of this semiconductor structure bodies (2).
2. semiconductor device as claimed in claim 1, wherein said hardboard (15) is by making with described substrate (1) identical materials.
3. semiconductor device as claimed in claim 1, wherein said hardboard (15) have and the identical thickness of described substrate (1).
4. semiconductor device as claimed in claim 1, wherein said substrate (1) is made by the material that comprises thermosetting resin at least with hardboard (15).
5. semiconductor device as claimed in claim 4, wherein said substrate (1) is formed by the substrate that comprises inorganic material with hardboard (15).
6. semiconductor device as claimed in claim 1, wherein said hardboard (15) is by making with described insulating barrier (14) identical materials.
7. semiconductor device as claimed in claim 1, wherein said hardboard (15) is made by the material with thermal coefficient of expansion identical with substrate (1).
8. semiconductor device as claimed in claim 1, one of wherein said substrate (1) and hardboard (15) are made by metallic plate (1a, 15a), and another is made by the material that comprises thermosetting resin at least.
9. semiconductor device as claimed in claim 8, wherein said metallic plate (1a, 15a) is made by the material that is selected from the group that copper and stainless steel constitute.
10. semiconductor device as claimed in claim 1, at least a portion of wherein said hardboard (15) is buried in the described insulating barrier (14).
11. semiconductor device as claimed in claim 10, the upper surface of wherein said hardboard (15) is concordant with the upper surface of described insulating barrier (14).
12. semiconductor device as claimed in claim 1 wherein is formed in the described insulating barrier (14) by another hardboard (15b) made from described hardboard (15) identical materials.
13. semiconductor device as claimed in claim 1, wherein said interconnection (19) is formed in the upper interconnect on the upper nonconductive Film (16), and described upper nonconductive Film (16) is formed on described semiconductor structure bodies (2) and the hardboard (15).
14. semiconductor device as claimed in claim 13 wherein is formed under the described substrate (1) by the following dielectric film made from described upper nonconductive Film (16) identical materials (23,24).
15. semiconductor device as claimed in claim 13, also comprise uppermost (20), it has covered the part except that the connection pads part of described upper interconnect (19), and orlop dielectric film (24), it is formed on the lowermost surface of described substrate (1), and by making with described uppermost (20) identical materials basically.
16. semiconductor device as claimed in claim 15, wherein said uppermost (20) and described orlop dielectric film (24) are formed by solder resist.
17. semiconductor device as claimed in claim 15, wherein soldered ball (22) is formed on the described connection pads part of described upper interconnect (19).
18. semiconductor device as claimed in claim 1 wherein forms one of the ground plane (51) made by solid pattern and bus plane (52), at least so that be connected to described interconnection (19) on the upper surface of described hardboard (15).
19. semiconductor device as claimed in claim 18, wherein said solid pattern are ground plane (51), and described ground plane (51) and upper interconnect (19) formation microstrip line construction.
20. semiconductor device as claimed in claim 1 wherein comprises heat radiation layer (57,58) in the described upper surface of described substrate (1) and at least one surface in the lower surface.
21. a method, semi-conductor device manufacturing method comprises:
A plurality of semiconductor structure bodies (2) are set respectively on substrate (1), and each semiconductor structure bodies (2) has Semiconductor substrate (4) and is formed on a plurality of external connecting electrodes (5,12) on the described Semiconductor substrate (4),
Round each semiconductor structure bodies (2), at the last insulating barrier cambium layer of making by the material that comprises resin (14a, 14b) that forms of described substrate (1), this resin is selected from the group that is made of semi-harden resin and liquid resin, and go up placement hardboard (15), this hardboard (15) porose in part (35) corresponding to each semiconductor structure bodies at described insulating barrier cambium layer (14a, 14b);
Heat and pressurize, form insulating barrier (14) to go up at described substrate (1) round each semiconductor structure bodies (2), and at least a portion of described hardboard (15) is buried in the described insulating barrier (14) by described semi-harden resin in the described insulating barrier cambium layer (14a, 14b) that hardens fully or liquid resin;
Formation will be connected to the interconnection (19) of the described external connecting electrode (5,12) of each semiconductor structure bodies (2); And
Obtain a plurality of semiconductor device by cutting described hardboard (15), insulating barrier (14) and substrate (1) between described semiconductor structure bodies (2).
22. method, semi-conductor device manufacturing method as claimed in claim 21, wherein said insulating barrier cambium layer (14a, 14b) forms plate (14a, 14b) by semi-harden and insulating barrier have hole (35) in the part corresponding to each semiconductor structure bodies (2) and makes.
23. method, semi-conductor device manufacturing method as claimed in claim 22, wherein form described insulating barrier cambium layer and also be included in another insulating barrier formation plate (14a, 14b) of formation on the described hardboard, and form another hardboard of placement on plate at described another insulating barrier.
24. method, semi-conductor device manufacturing method as claimed in claim 21 wherein forms described insulating barrier formation plate (14a, 14b) and comprises the material that contains liquid thermosetting resin round described semiconductor structure bodies (2) in the last coating of described substrate (1).
25. method, semi-conductor device manufacturing method as claimed in claim 21, wherein said insulating barrier cambium layer (14a, 14b) is semi-harden, and is integrally formed on the upper surface of described hardboard (15).
26. method, semi-conductor device manufacturing method as claimed in claim 21, wherein said hardboard (15) is by making with described substrate (1) identical materials.
27. method, semi-conductor device manufacturing method as claimed in claim 21, wherein said hardboard (15) have and the identical thickness of described substrate (1).
28. method, semi-conductor device manufacturing method as claimed in claim 21, wherein said substrate (1) and hardboard (15) are made by the material that comprises thermosetting resin at least.
29. method, semi-conductor device manufacturing method as claimed in claim 21, wherein said substrate (1) and hardboard (15) are formed by the substrate that comprises inorganic material.
30. method, semi-conductor device manufacturing method as claimed in claim 21, wherein said hardboard (15) is by making with described insulating barrier (14) identical materials.
31. method, semi-conductor device manufacturing method as claimed in claim 21, wherein said hardboard (15) is made by thermal coefficient of expansion and described substrate (1) identical materials.
32. method, semi-conductor device manufacturing method as claimed in claim 21, one of wherein said substrate (1) and hardboard (15) are made by metallic plate (1a, 15a), and another is made by the material that comprises thermosetting resin at least.
33. method, semi-conductor device manufacturing method as claimed in claim 32, wherein said metallic plate (1a, 15a) is made by the material of selecting from comprise copper and stainless group.
34. method, semi-conductor device manufacturing method as claimed in claim 21, wherein said interconnection (19) is a upper interconnect, and this method also is included in described hardboard (15) and goes up formation upper nonconductive Film (16), and goes up formation described upper interconnect (19) at described upper nonconductive Film (16).
35. method, semi-conductor device manufacturing method as claimed in claim 34 wherein forms the described upper nonconductive Film (16) that described upper nonconductive Film comprises that formation is semi-harden on described hardboard, and by the heating and the described upper nonconductive Film that hardens fully that pressurizes.
36. method, semi-conductor device manufacturing method as claimed in claim 35 wherein makes the sclerosis fully simultaneously of described insulating barrier (14) and upper nonconductive Film (16) by heating and pressurization.
37. method, semi-conductor device manufacturing method as claimed in claim 35, wherein by heating with when pressurization harden described upper nonconductive Film (16) fully, formation is by the following dielectric film made from described upper nonconductive Film (16) identical materials (23,24) on the lower surface of described substrate (1).
38. method, semi-conductor device manufacturing method as claimed in claim 37 wherein makes the sclerosis fully simultaneously of described insulating barrier (14), upper nonconductive Film (16) and following dielectric film (23,24) by heating and pressurization.
39. method, semi-conductor device manufacturing method as claimed in claim 34, the uppermost (20) that also comprises the part the connection pads part of form to cover removing described upper interconnect (19), and on the orlop surface of described substrate (1) formation by the orlop dielectric film made from described uppermost (20) identical materials (24).
40. method, semi-conductor device manufacturing method as claimed in claim 39, wherein said uppermost (20) and orlop dielectric film (24) are formed by solder resist.
41. method, semi-conductor device manufacturing method as claimed in claim 39, the connection pads that also is included in described upper interconnect (19) partly goes up and forms soldered ball (22).
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| JP428695/2003 | 2003-12-25 | ||
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| JP2003298005A (en) * | 2002-02-04 | 2003-10-17 | Casio Comput Co Ltd | Semiconductor device and method of manufacturing thereof |
| US20030168254A1 (en) * | 2002-02-06 | 2003-09-11 | Takashi Kariya | Semiconductor chip mounting wiring board, manufacturing method for same, and semiconductor module |
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|---|---|
| CN1830081A (en) | 2006-09-06 |
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