TWI543320B - Semiconductor package and a method for fabricating the same - Google Patents

Semiconductor package and a method for fabricating the same Download PDF

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Publication number
TWI543320B
TWI543320B TW103129815A TW103129815A TWI543320B TW I543320 B TWI543320 B TW I543320B TW 103129815 A TW103129815 A TW 103129815A TW 103129815 A TW103129815 A TW 103129815A TW I543320 B TWI543320 B TW I543320B
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Taiwan
Prior art keywords
package
carrier
semiconductor package
electronic components
support frame
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TW103129815A
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Chinese (zh)
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TW201608686A (en
Inventor
陳彥亨
詹慕萱
紀傑元
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矽品精密工業股份有限公司
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Priority to TW103129815A priority Critical patent/TWI543320B/en
Priority to CN201410464411.6A priority patent/CN105470209A/en
Publication of TW201608686A publication Critical patent/TW201608686A/en
Application granted granted Critical
Publication of TWI543320B publication Critical patent/TWI543320B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

半導體封裝件及其製法 Semiconductor package and its manufacturing method

本發明係有關一種半導體封裝件之製法,尤指一種提昇產能之半導體封裝件及其製法。 The invention relates to a method for manufacturing a semiconductor package, in particular to a semiconductor package for improving productivity and a method for manufacturing the same.

隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求,係發展出晶圓級封裝(Wafer Level Packaging,WLP)的技術。 With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements for semiconductor package miniaturization, Wafer Level Packaging (WLP) technology was developed.

如第1A至1E圖,係為習知晶圓級半導體封裝件1之製法之剖面示意圖。 1A to 1E are schematic cross-sectional views showing a conventional method of fabricating a wafer-level semiconductor package 1.

如第1A圖所示,形成一熱化離型膠層(thermal release tape)11於一承載件10上。 As shown in FIG. 1A, a thermal release tape 11 is formed on a carrier 10.

接著,置放複數半導體元件12於該熱化離型膠層11上,該些半導體元件12具有相對之主動面12a與非主動面12b,各該主動面12a上均具有複數電極墊120,且各該主動面12a黏著於該熱化離型膠層11上。 Next, a plurality of semiconductor elements 12 are disposed on the thermal release adhesive layer 11, the semiconductor elements 12 having opposite active planes 12a and inactive surfaces 12b, each of which has a plurality of electrode pads 120 thereon, and Each of the active faces 12a is adhered to the thermal release adhesive layer 11.

如第1B圖所示,形成一封裝膠體13於該熱化離型膠層11上,以包覆該半導體元件12,且使該半導體元件12 之非主動面12b外露於該封裝膠體13。 As shown in FIG. 1B, an encapsulant 13 is formed on the thermal release adhesive layer 11 to encapsulate the semiconductor component 12, and the semiconductor component 12 is formed. The inactive surface 12b is exposed to the encapsulant 13 .

如第1C圖所示,於該封裝膠體13及該半導體元件12之非主動面12b上藉由一結合層170貼覆一支撐件17,再烘烤該封裝膠體13以硬化該熱化離型膠層11而移除該熱化離型膠層11與該承載件10,使該半導體元件12之主動面12a外露。之後,固化(curing)該封裝膠體13。 As shown in FIG. 1C, a support member 17 is attached to the encapsulant 13 and the inactive surface 12b of the semiconductor device 12 by a bonding layer 170, and the encapsulant 13 is baked to harden the thermal release type. The adhesive layer 11 removes the thermal release adhesive layer 11 and the carrier 10 to expose the active surface 12a of the semiconductor component 12. Thereafter, the encapsulant 13 is cured.

如第1D圖所示,進行線路重佈層(Redistribution layer,RDL)製程,係形成一線路重佈結構14於該封裝膠體13與該半導體元件12之主動面12a上,令該線路重佈結構14電性連接該半導體元件12之電極墊120。 As shown in FIG. 1D, a circuit redistribution layer (RDL) process is performed to form a line redistribution structure 14 on the encapsulant 13 and the active surface 12a of the semiconductor component 12, so that the circuit is re-wired. The electrode pad 120 of the semiconductor element 12 is electrically connected.

接著,形成一絕緣保護層15於該線路重佈結構14上,且該絕緣保護層15外露該線路重佈結構14之部分表面,以供結合如銲球之導電元件16。 Next, an insulating protective layer 15 is formed on the circuit redistribution structure 14, and the insulating protective layer 15 exposes a portion of the surface of the circuit redistribution structure 14 for bonding the conductive elements 16 such as solder balls.

如第1E圖所示,沿如第1D圖所示之切割路徑S進行切單製程,以獲取複數個半導體封裝件1(即封裝單元)。 As shown in FIG. 1E, a singulation process is performed along the dicing path S as shown in FIG. 1D to obtain a plurality of semiconductor packages 1 (ie, package units).

習知半導體封裝件1之製法係為晶圓級(wafer form),而為降低生產成本,係以整版面形式(Panel form)製作。目前製作之整版面形式之尺寸,其長與寬分別為370mm×470mm,目標發展為600mm×700mm。 The conventional semiconductor package 1 is manufactured in a wafer form, and is manufactured in a panel form in order to reduce production costs. The size of the full-face form currently produced is 370 mm × 470 mm in length and width, and the target is developed to be 600 mm × 700 mm.

惟,習知半導體封裝件1之製法中,目前現有切單機台最大僅能置放100mm×240mm,因而無法放置370mm×470mm或更大尺寸,故現階段需先以人工方式切割成適合尺寸,再放入現有切單機中,導致難以提升產量。 However, in the manufacturing method of the conventional semiconductor package 1, the current singulation machine can only be placed at a maximum size of 100 mm × 240 mm, and thus cannot be placed at a size of 370 mm × 470 mm or more, so that it is necessary to manually cut into a suitable size at this stage. Putting it into the existing singer, it is difficult to increase the output.

再者,若要直接將370mm×470mm或更大尺寸之版面進 行切單製程,需額外特製機台,導致產品製作成本提高。 Furthermore, if you want to directly enter the layout of 370mm × 470mm or larger The line cutting process requires an extra special machine, which leads to an increase in production costs.

因此,如何克服上述習知技術的種種問題,實已成目前亟欲解決的課題。 Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

鑑於上述習知技術之種種缺失,本發明係提供一種半導體封裝件,係為整版面結構,其包括:一支撐框,係具有複數置放區;複數電子元件,係容置於各該置放區中,且單一該置放區中設有複數個該電子元件;以及封裝材,係形成於該些置放區中以包覆該些電子元件。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides a semiconductor package, which is a full-page structure, comprising: a support frame having a plurality of placement areas; a plurality of electronic components, the system is placed in each of the placements And a plurality of the electronic components are disposed in the single region, and the packaging material is formed in the placement regions to encapsulate the electronic components.

本發明亦提供一種半導體封裝件,係為封裝區塊,其包括:一支撐框,係僅具有一置放區;複數電子元件,係容置於該置放區中;以及封裝材,係形成於該置放區中以包覆該些電子元件。 The present invention also provides a semiconductor package, which is a package block, comprising: a support frame having only one placement area; a plurality of electronic components, the system is placed in the placement area; and the package material is formed In the placement area, the electronic components are covered.

前述之兩種半導體封裝件中,復包括一承載體,係形成於該封裝材上。 In the foregoing two kinds of semiconductor packages, a carrier is further included and formed on the package.

本發明復提供一種半導體封裝件之製法,係包括:提供一其上設有一支撐框與複數電子元件的承載件,且該支撐框具有複數容置各該電子元件之置放區,並於該承載件上形成有包覆該些電子元件與該支撐框之封裝材;結合一承載體於該封裝材上;移除該承載件;以及沿該些置放區進行分離製程。 The present invention provides a method for fabricating a semiconductor package, comprising: providing a carrier having a support frame and a plurality of electronic components thereon, and the support frame has a plurality of placement regions for accommodating the electronic components, and Forming a package on the carrier with the electronic component and the support frame; bonding a carrier to the package; removing the carrier; and performing a separation process along the placement areas.

前述之製法中,復包括於進行該分離製程後,移除該承載體。 In the foregoing method, the carrier is removed after the separation process is performed.

前述之製法中,復包括於移除該承載件後,先移除該 承載體,再進行該分離製程。 In the foregoing method, after the removal of the carrier, the first removal is performed. The carrier is further subjected to the separation process.

前述之製法中,復包括於進行該分離製程後,進行切單製程。 In the above method, the singulation process is performed after the separation process is performed.

前述之兩種半導體封裝件及其製法中,該電子元件具有相對之主動面與非主動面,且該電子元件以其主動面結合於該承載件上。 In the foregoing two kinds of semiconductor packages and methods of manufacturing the same, the electronic components have opposite active and non-active surfaces, and the electronic components are coupled to the carrier with their active faces.

前述之兩種半導體封裝件及其製法中,復包括於移除該承載件後,形成一線路重佈結構於該封裝材與該電子元件上,且該線路重佈結構電性連接該電子元件。 In the foregoing two kinds of semiconductor packages and the manufacturing method thereof, the method further comprises: after removing the carrier, forming a line redistribution structure on the package material and the electronic component, and the circuit redistribution structure electrically connecting the electronic component .

由上可知,本發明之半導體封裝件及其製法,係藉由該支撐框之設計,以將整版面結構分割成所需尺寸之封裝區塊,而於後續製程中,可進行切單、封裝與組裝等製程,故藉此方法可依需求增加整版面之尺寸以提升產量,且能省去機台開發之成本。 It can be seen from the above that the semiconductor package of the present invention and the manufacturing method thereof are designed by the support frame to divide the entire layout structure into package blocks of a desired size, and in the subsequent process, the singulation and packaging can be performed. With the assembly process, the method can increase the size of the full-face to increase the output according to the demand, and can save the cost of machine development.

1,2,3‧‧‧半導體封裝件 1,2,3‧‧‧Semiconductor package

10,20‧‧‧承載件 10,20‧‧‧Carrier

11‧‧‧熱化離型膠層 11‧‧‧heating release layer

12‧‧‧半導體元件 12‧‧‧Semiconductor components

12a,22a‧‧‧主動面 12a, 22a‧‧‧ active surface

12b,22b‧‧‧非主動面 12b, 22b‧‧‧ inactive surface

120‧‧‧電極墊 120‧‧‧electrode pads

13‧‧‧封裝膠體 13‧‧‧Package colloid

14,24‧‧‧線路重佈結構 14,24‧‧‧Line redistribution structure

15‧‧‧絕緣保護層 15‧‧‧Insulation protective layer

16,26‧‧‧導電元件 16,26‧‧‧ conductive elements

17,271‧‧‧支撐件 17,271‧‧‧Support

170,270‧‧‧結合層 170, 270‧‧‧ bonding layer

21‧‧‧黏著層 21‧‧‧Adhesive layer

22‧‧‧電子元件 22‧‧‧Electronic components

23‧‧‧封裝材 23‧‧‧Package

240‧‧‧介電層 240‧‧‧ dielectric layer

241‧‧‧線路層 241‧‧‧Line layer

27‧‧‧承載體 27‧‧‧Carrier

28‧‧‧支撐框 28‧‧‧Support frame

280‧‧‧置放區 280‧‧‧Placement area

3a‧‧‧封裝單元 3a‧‧‧Package unit

L‧‧‧分割路徑 L‧‧‧ split path

S,S’‧‧‧切割路徑 S, S’‧‧‧ cutting path

第1A至1E圖係為習知半導體封裝件之製法之剖面示意圖;以及第2A至2F圖係本發明之半導體封裝件之製法之剖面示意圖;其中,第2A’與2B’圖係第2A與2B圖之上視圖,第2F’圖係第2F圖之下視圖。 1A to 1E are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package; and 2A to 2F are schematic cross-sectional views showing a method of fabricating the semiconductor package of the present invention; wherein 2A' and 2B' are 2A and The view above the 2B diagram, the 2F' diagram is the view below the 2F diagram.

以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper" and "one" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship is changed or adjusted. Substantially changing the technical content is also considered to be within the scope of the invention.

第2A至2F圖係為本發明之半導體封裝件2,3之製法的剖面示意圖。 2A to 2F are schematic cross-sectional views showing the manufacturing method of the semiconductor package 2, 3 of the present invention.

如第2A及2A’圖所示,設置一支撐框28於一承載件20上。 As shown in Figures 2A and 2A', a support frame 28 is provided on a carrier member 20.

於本實施例中,該承載件20係為如晶圓、矽板之半導體基板或玻璃基板,且該承載件20藉由其表面上之黏著層21以結合該支撐框28。 In this embodiment, the carrier 20 is a semiconductor substrate such as a wafer or a silicon plate or a glass substrate, and the carrier 20 is bonded to the support frame 28 by an adhesive layer 21 on the surface thereof.

再者,該黏著層21係為熱化離型膠層(thermal release tape)。 Furthermore, the adhesive layer 21 is a thermal release tape.

又,該支撐框28係為金屬框,其具有複數外露出該黏著層21之置放區280。 Moreover, the support frame 28 is a metal frame having a plurality of placement areas 280 that expose the adhesive layer 21.

如第2B及2B’圖所示,設置複數電子元件22於該置放區280中之黏著層21上,再形成封裝材23於該黏著層21上,以包覆該些電子元件22與支撐框。 As shown in FIGS. 2B and 2B', a plurality of electronic components 22 are disposed on the adhesive layer 21 in the placement area 280, and a package 23 is formed on the adhesive layer 21 to encapsulate the electronic components 22 and support. frame.

於本實施例中,該承載件20藉由其表面上之黏著層21結合該些電子元件22。 In the present embodiment, the carrier 20 is bonded to the electronic components 22 by an adhesive layer 21 on the surface thereof.

再者,該電子元件22係為主動元件、被動元件或其組合者,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。例如,該電子元件22具有相對之主動面22a與非主動面22b,且該電子元件22以其主動面22a結合該黏著層21。 Furthermore, the electronic component 22 is an active component, a passive component or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 22 has an opposite active surface 22a and an inactive surface 22b, and the electronic component 22 incorporates the adhesive layer 21 with its active surface 22a.

另外,該封裝材23係以壓合(Lamination)方式或模壓(molding)方式形成於該承載件20上,且該封裝材23之材質係為乾膜型(Dry Film Type)環氧樹脂(Epoxy)或流體狀環氧樹脂、或有機材質,如ABF(Ajinomoto Build-up Film)樹脂。 In addition, the package material 23 is formed on the carrier 20 by a lamination method or a molding method, and the material of the package material 23 is a dry film type epoxy resin (Epoxy). ) or a fluid epoxy resin, or an organic material such as ABF (Ajinomoto Build-up Film) resin.

如第2C圖所示,結合一承載體27於該封裝材23上(於該電子元件22之非主動面22b上方),且該承載體27係包含設於該封裝材23上之結合層270、及設於該結合層270上之支撐件271。 As shown in FIG. 2C, a carrier 27 is bonded to the package 23 (above the inactive surface 22b of the electronic component 22), and the carrier 27 includes a bonding layer 270 disposed on the package 23. And a support member 271 disposed on the bonding layer 270.

於本實施例中,該支撐件271之材質係為無機材質或有機材質,該無機材質係例如玻璃、矽(Si)、陶瓷、碳化矽(SiC)、二氧化矽(SiO2)、砷化鎵(gallium arsenide,GaAs)、磷砷化鎵(gallium arsenide phosphide,GaAsP)、磷化銦(indium phosphide,InP)、砷化鋁鎵(gallium aluminum arsenide,GaAlAs)或磷化銦鎵(indium gallium phosphide,InGaP)等,該有機材質係例如塑膠、玻璃纖維強化樹脂(如bismaleimide-triazine,簡稱BT)、玻璃纖維強化環氧樹脂 (fiberglass reinforced epoxy resin)(如FR-4)或環氧樹脂(epoxy)等。 In this embodiment, the material of the support member 271 is an inorganic material or an organic material, such as glass, bismuth (Si), ceramic, tantalum carbide (SiC), cerium oxide (SiO 2 ), arsenic. Gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), indium phosphide (InP), gallium aluminum arsenide (GaAlAs) or indium gallium phosphide , InGaP), etc., the organic material is, for example, plastic, glass fiber reinforced resin (such as bismaleimide-triazine, BT for short), fiberglass reinforced epoxy resin (such as FR-4) or epoxy resin (epoxy) )Wait.

再者,該結合層270係為黏性材質,如乾膜型環氧樹脂。 Furthermore, the bonding layer 270 is a viscous material such as a dry film epoxy resin.

又,可先以如旋塗(spin coating)方式形成該結合層270於該支撐件271上,再將該承載體27結合於該封裝材23上。 Moreover, the bonding layer 270 may be formed on the support member 271 by spin coating, and the carrier 27 may be bonded to the package member 23.

另外,亦可先形成該結合層270於該封裝材23上,再將該支撐件271結合於該結合層270上。 Alternatively, the bonding layer 270 may be formed on the package 23, and the support member 271 may be bonded to the bonding layer 270.

如第2D圖所示,移除該承載件20及該黏著層21,以外露該電子元件22之主動面22a。之後,硬化(curing)該封裝材23。 As shown in FIG. 2D, the carrier 20 and the adhesive layer 21 are removed, and the active surface 22a of the electronic component 22 is exposed. Thereafter, the package 23 is cured.

於本實施例中,由於該黏著層21係為熱化離型膠層(thermal release tape),故進行如烘烤之加熱製程以硬化該封裝材23,且使該黏著層21一併受熱而失去黏性,藉此移除該黏著層21與該承載件20。 In this embodiment, since the adhesive layer 21 is a thermal release tape, a heating process such as baking is performed to harden the package 23, and the adhesive layer 21 is heated together. The adhesive is lost, thereby removing the adhesive layer 21 and the carrier 20.

如第2E圖所示,進行線路重佈層(Redistribution layer,RDL)製程,即形成一線路重佈結構24於該封裝材23、支撐框與該些電子元件22上,且該線路重佈結構24電性連接各該電子元件22。藉此,完成整版面(panel)結構之半導體封裝件2。 As shown in FIG. 2E, a line redistribution layer (RDL) process is performed, that is, a line redistribution structure 24 is formed on the package material 23, the support frame, and the electronic components 22, and the line redistribution structure is formed. 24 is electrically connected to each of the electronic components 22. Thereby, the semiconductor package 2 of the full-panel structure is completed.

於本實施例中,該線路重佈結構24係包含相疊之至少一線路層241與至少一介電層240,該介電層240係形成於該封裝材23上,且該線路層241係電性連接該電子元件 22。 In this embodiment, the circuit redistribution structure 24 includes at least one circuit layer 241 and at least one dielectric layer 240 stacked on each other. The dielectric layer 240 is formed on the package 23, and the circuit layer 241 is Electrically connecting the electronic component twenty two.

接著,形成一絕緣保護層(圖略,可參考第1D圖之絕緣保護層15)於該線路重佈結構24上,且該絕緣保護層外露該線路層241之部分表面,俾供作為電性接觸墊,以結合如銲球之導電元件26而接置其它電子裝置(如電路板)。 Then, an insulating protective layer (not shown, which can be referred to the insulating protective layer 15 of FIG. 1D) is formed on the circuit redistributing structure 24, and the insulating protective layer exposes a part of the surface of the circuit layer 241, and is used as an electrical property. Contact pads are used to bond other electronic devices (such as circuit boards) in conjunction with conductive elements 26 such as solder balls.

如第2F及2F’圖所示,沿如第2E圖所示之分割路徑L(即沿該些置放區280之邊緣)進行分離製程。之後移除該承載體27及該結合層270。 As shown in Figs. 2F and 2F', the separation process is performed along the division path L as shown in Fig. 2E (i.e., along the edges of the placement areas 280). The carrier 27 and the bonding layer 270 are then removed.

於本實施例中,該分離製程係將整版面結構分割成複數封裝區塊(strip),如第2B’圖所示之8塊封裝區塊(strip),且該封裝區塊之尺寸係為100mm×240mm,其由複數封裝單元3a(如第2F’圖所示之切單製程之切割路徑S’之範圍)構成。具體地,單一該封裝單元3a中之電子元件22之數量可依需求而定,即藉由調整切單製程之切割路徑S’,例如,第2F’圖所示之單一該封裝單元3a中具有一個電子元件22,而於其它實施例中,單一該封裝單元3a中亦可具有四個電子元件22。 In this embodiment, the separation process divides the full-page structure into a plurality of package strips, such as the 8 package strips shown in FIG. 2B′, and the size of the package block is 100 mm × 240 mm, which is composed of a plurality of package units 3a (the range of the cutting path S' of the singulation process shown in Fig. 2F'). Specifically, the number of the electronic components 22 in the single package unit 3a can be determined according to requirements, that is, by adjusting the cutting path S' of the singulation process, for example, the single package unit 3a shown in FIG. 2F' has One electronic component 22, and in other embodiments, there may be four electronic components 22 in a single package unit 3a.

再者,藉由該支撐框28支撐該封裝區塊,以避免該封裝區塊發生翹曲。 Furthermore, the package block is supported by the support frame 28 to avoid warping of the package block.

於其它實施例中,亦可先移除該承載體27及該結合層270,再進行該分離製程。 In other embodiments, the carrier 27 and the bonding layer 270 may be removed first, and then the separation process is performed.

本發明之製法中,藉由該支撐框28之設計,以將整版面結構分割成尺寸100mm×240mm之封裝區塊,而於後續製 程中,可將該封裝區塊進行切單製程以獲得複數封裝單元3a,故藉此方法可依需求增加整版面之尺寸,而變換整版面之尺寸,以提升產量。 In the manufacturing method of the present invention, the design of the support frame 28 is used to divide the entire layout structure into a package block having a size of 100 mm×240 mm, and In the process, the package block can be singulated to obtain the plurality of package units 3a. Therefore, the size of the full-page surface can be increased according to the requirement, and the size of the entire layout surface can be changed to increase the yield.

再者,藉由該支撐框28之設計,可將整版面結構分割成現有切單機所需之切單尺寸(即該封裝區塊之尺寸),即可進行量產,無需額外開發新機台,故能降低機台開發之成本。 Furthermore, by designing the support frame 28, the entire layout structure can be divided into the singulation size required for the existing singulator (ie, the size of the package block), and mass production can be performed without additional development of a new machine. Therefore, it can reduce the cost of machine development.

又,藉由該支撐框28之設計,能以自動化方式將整版面結構分離成所需尺寸之封裝區塊,再放入現有切單機中,以提升產量。 Moreover, by the design of the support frame 28, the entire layout structure can be separated into the package blocks of the required size in an automated manner, and then placed in the existing singulator to increase the yield.

本發明復提供一種半導體封裝件2,係包括:具有複數置放區280之一支撐框28、容置於各該置放區280中之複數電子元件22、以及形成於該些置放區280中以包覆該些電子元件22之封裝材23。 The present invention further provides a semiconductor package 2 comprising: a support frame 28 having a plurality of placement areas 280, a plurality of electronic components 22 housed in each of the placement areas 280, and a plurality of electronic components 22 formed in the placement areas 280. The package 23 covering the electronic components 22 is covered.

所述之半導體封裝件2係為由複數封裝區塊構成之整版面結構,其單一該置放區280中設有複數個該電子元件22。 The semiconductor package 2 is a full-surface structure composed of a plurality of package blocks, and a plurality of the electronic components 22 are disposed in the single placement area 280.

所述之電子元件22具有相對之主動面22a與非主動面22b,且該電子元件22之主動面22a外露於該封裝材23。 The electronic component 22 has an opposite active surface 22a and an inactive surface 22b, and the active surface 22a of the electronic component 22 is exposed to the package 23.

本發明亦提供一種半導體封裝件3,係為由複數封裝單元3a構成之封裝區塊,其支撐框28僅具有一置放區280,且複數電子元件22係容置於該置放區280中。 The present invention also provides a semiconductor package 3, which is a package block composed of a plurality of package units 3a. The support frame 28 has only one placement area 280, and the plurality of electronic components 22 are housed in the placement area 280. .

於一實施例中,復包括一線路重佈結構24,係形成於該封裝材23與該電子元件22之主動面22a上,且該線路 重佈結構24電性連接該電子元件22之主動面22a。 In an embodiment, a circuit redistribution structure 24 is formed on the package 23 and the active surface 22a of the electronic component 22, and the circuit The redistribution structure 24 is electrically connected to the active surface 22a of the electronic component 22.

於一實施例中,復包括一承載體27,係形成於該封裝材23上。 In an embodiment, a carrier 27 is formed on the package 23 .

綜上所述,本發明之半導體封裝件及其製法,主要藉由該支撐框之設計,以將整版面結構分割成所需尺寸之封裝區塊,以於後續製程中,可使用現有機台進行生產,故不僅能省去機台開發之成本,且藉此可依需求增加整版面之尺寸以提升產量。 In summary, the semiconductor package of the present invention and the method for manufacturing the same are mainly used to divide the entire layout structure into package blocks of a desired size by using the support frame, so that the existing machine can be used in the subsequent process. Production is carried out, so not only can the cost of machine development be saved, but also the size of the entire layout can be increased to increase production.

上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧半導體封裝件 2‧‧‧Semiconductor package

22‧‧‧電子元件 22‧‧‧Electronic components

23‧‧‧封裝材 23‧‧‧Package

24‧‧‧線路重佈結構 24‧‧‧Line redistribution structure

240‧‧‧介電層 240‧‧‧ dielectric layer

241‧‧‧線路層 241‧‧‧Line layer

26‧‧‧導電元件 26‧‧‧Conductive components

27‧‧‧承載體 27‧‧‧Carrier

28‧‧‧支撐框 28‧‧‧Support frame

280‧‧‧置放區 280‧‧‧Placement area

L‧‧‧分割路徑 L‧‧‧ split path

Claims (11)

一種半導體封裝件,係為整版面結構,其包括:一支撐框,係具有複數置放區,該支撐框之框架位於切割道上;複數電子元件,係容置於各該置放區中,且單一該置放區中設有複數個該電子元件;以及封裝材,係形成於該些置放區中以包覆該些電子元件。 A semiconductor package, which is a full-surface structure, comprising: a support frame having a plurality of placement areas, the frame of the support frame is located on the cutting path; and a plurality of electronic components are disposed in each of the placement areas, and A plurality of the electronic components are disposed in the single placement area; and an encapsulating material is formed in the placement areas to encapsulate the electronic components. 一種半導體封裝件,係為封裝區塊,其包括:一支撐框,係僅具有一置放區,該支撐框之框架位於切割道上;複數電子元件,係容置於該置放區中;以及封裝材,係形成於該置放區中以包覆該些電子元件。 A semiconductor package is a package block, comprising: a support frame having only one placement area, the frame of the support frame is located on the cutting track; and a plurality of electronic components are disposed in the placement area; An encapsulating material is formed in the placement area to encapsulate the electronic components. 如申請專利範圍第1或2項所述之半導體封裝件,其中,該電子元件具有相對之主動面與非主動面,且該電子元件之主動面外露於該封裝材。 The semiconductor package of claim 1 or 2, wherein the electronic component has an opposite active surface and a non-active surface, and the active surface of the electronic component is exposed to the package. 如申請專利範圍第3項所述之半導體封裝件,復包括一線路重佈結構,係形成於該封裝材與該電子元件之主動面上,且該線路重佈結構電性連接該些電子元件。 The semiconductor package of claim 3, further comprising a line redistribution structure formed on the active surface of the package and the electronic component, and the circuit redistribution structure electrically connecting the electronic components . 如申請專利範圍第1或2項所述之半導體封裝件,復包括一承載體,係形成於該封裝材上。 The semiconductor package of claim 1 or 2, further comprising a carrier formed on the package. 一種半導體封裝件之製法,係包括:提供一其上設有一支撐框與複數電子元件的承載件,且該支撐框具有複數容置各該電子元件之置放區,並 於該承載件上形成有包覆該些電子元件與該支撐框之封裝材;結合一承載體於該封裝材上;移除該承載件;以及沿該些置放區進行分離製程。 A method for manufacturing a semiconductor package, comprising: providing a support member having a support frame and a plurality of electronic components thereon, wherein the support frame has a plurality of placement areas for accommodating the electronic components, and Forming a package covering the electronic components and the support frame on the carrier; bonding a carrier to the package; removing the carrier; and performing a separation process along the placement areas. 如申請專利範圍第6項所述之半導體封裝件之製法,其中,該電子元件具有相對之主動面與非主動面,且該電子元件以其主動面結合於該承載件上。 The method of fabricating a semiconductor package according to claim 6, wherein the electronic component has an opposite active surface and a non-active surface, and the electronic component is bonded to the carrier with its active surface. 如申請專利範圍第6項所述之半導體封裝件之製法,復包括於移除該承載件後,形成一線路重佈結構於該封裝材與該電子元件上,並令該線路重佈結構電性連接該電子元件。 The method for manufacturing a semiconductor package according to claim 6 is characterized in that after removing the carrier, a circuit redistribution structure is formed on the package and the electronic component, and the circuit is re-wired. Sexually connect the electronic component. 如申請專利範圍第6項所述之半導體封裝件之製法,復包括於進行該分離製程後,移除該承載體。 The method for fabricating a semiconductor package according to claim 6 is to include removing the carrier after performing the separation process. 如申請專利範圍第6項所述之半導體封裝件之製法,復包括於移除該承載件後,先移除該承載體,再進行該分離製程。 The method for manufacturing a semiconductor package according to claim 6 is characterized in that after the carrier is removed, the carrier is removed and the separation process is performed. 如申請專利範圍第6項所述之半導體封裝件之製法,復包括於進行該分離製程後,進行切單製程。 The method for manufacturing a semiconductor package according to claim 6, wherein the method further comprises performing a singulation process after performing the separation process.
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