TWI543320B - Semiconductor package and a method for fabricating the same - Google Patents

Description

Semiconductor package and its manufacturing method

The invention relates to a method for manufacturing a semiconductor package, in particular to a semiconductor package for improving productivity and a method for manufacturing the same.

With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements for semiconductor package miniaturization, Wafer Level Packaging (WLP) technology was developed.

1A to 1E are schematic cross-sectional views showing a conventional method of fabricating a wafer-level semiconductor package 1.

As shown in FIG. 1A, a thermal release tape 11 is formed on a carrier 10.

Next, a plurality of semiconductor elements 12 are disposed on the thermal release adhesive layer 11, the semiconductor elements 12 having opposite active planes 12a and inactive surfaces 12b, each of which has a plurality of electrode pads 120 thereon, and Each of the active faces 12a is adhered to the thermal release adhesive layer 11.

As shown in FIG. 1B, an encapsulant 13 is formed on the thermal release adhesive layer 11 to encapsulate the semiconductor component 12, and the semiconductor component 12 is formed. The inactive surface 12b is exposed to the encapsulant 13 .

As shown in FIG. 1C, a support member 17 is attached to the encapsulant 13 and the inactive surface 12b of the semiconductor device 12 by a bonding layer 170, and the encapsulant 13 is baked to harden the thermal release type. The adhesive layer 11 removes the thermal release adhesive layer 11 and the carrier 10 to expose the active surface 12a of the semiconductor component 12. Thereafter, the encapsulant 13 is cured.

As shown in FIG. 1D, a circuit redistribution layer (RDL) process is performed to form a line redistribution structure 14 on the encapsulant 13 and the active surface 12a of the semiconductor component 12, so that the circuit is re-wired. The electrode pad 120 of the semiconductor element 12 is electrically connected.

Next, an insulating protective layer 15 is formed on the circuit redistribution structure 14, and the insulating protective layer 15 exposes a portion of the surface of the circuit redistribution structure 14 for bonding the conductive elements 16 such as solder balls.

As shown in FIG. 1E, a singulation process is performed along the dicing path S as shown in FIG. 1D to obtain a plurality of semiconductor packages 1 (ie, package units).

The conventional semiconductor package 1 is manufactured in a wafer form, and is manufactured in a panel form in order to reduce production costs. The size of the full-face form currently produced is 370 mm × 470 mm in length and width, and the target is developed to be 600 mm × 700 mm.

However, in the manufacturing method of the conventional semiconductor package 1, the current singulation machine can only be placed at a maximum size of 100 mm × 240 mm, and thus cannot be placed at a size of 370 mm × 470 mm or more, so that it is necessary to manually cut into a suitable size at this stage. Putting it into the existing singer, it is difficult to increase the output.

Furthermore, if you want to directly enter the layout of 370mm × 470mm or larger The line cutting process requires an extra special machine, which leads to an increase in production costs.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides a semiconductor package, which is a full-page structure, comprising: a support frame having a plurality of placement areas; a plurality of electronic components, the system is placed in each of the placements And a plurality of the electronic components are disposed in the single region, and the packaging material is formed in the placement regions to encapsulate the electronic components.

The present invention also provides a semiconductor package, which is a package block, comprising: a support frame having only one placement area; a plurality of electronic components, the system is placed in the placement area; and the package material is formed In the placement area, the electronic components are covered.

In the foregoing two kinds of semiconductor packages, a carrier is further included and formed on the package.

The present invention provides a method for fabricating a semiconductor package, comprising: providing a carrier having a support frame and a plurality of electronic components thereon, and the support frame has a plurality of placement regions for accommodating the electronic components, and Forming a package on the carrier with the electronic component and the support frame; bonding a carrier to the package; removing the carrier; and performing a separation process along the placement areas.

In the foregoing method, the carrier is removed after the separation process is performed.

In the foregoing method, after the removal of the carrier, the first removal is performed. The carrier is further subjected to the separation process.

In the above method, the singulation process is performed after the separation process is performed.

In the foregoing two kinds of semiconductor packages and methods of manufacturing the same, the electronic components have opposite active and non-active surfaces, and the electronic components are coupled to the carrier with their active faces.

In the foregoing two kinds of semiconductor packages and the manufacturing method thereof, the method further comprises: after removing the carrier, forming a line redistribution structure on the package material and the electronic component, and the circuit redistribution structure electrically connecting the electronic component .

It can be seen from the above that the semiconductor package of the present invention and the manufacturing method thereof are designed by the support frame to divide the entire layout structure into package blocks of a desired size, and in the subsequent process, the singulation and packaging can be performed. With the assembly process, the method can increase the size of the full-face to increase the output according to the demand, and can save the cost of machine development.

1,2,3‧‧‧Semiconductor package

10,20‧‧‧Carrier

11‧‧‧heating release layer

12‧‧‧Semiconductor components

12a, 22a‧‧‧ active surface

12b, 22b‧‧‧ inactive surface

120‧‧‧electrode pads

13‧‧‧Package colloid

14,24‧‧‧Line redistribution structure

15‧‧‧Insulation protective layer

16,26‧‧‧ conductive elements

17,271‧‧‧Support

170, 270‧‧‧ bonding layer

21‧‧‧Adhesive layer

22‧‧‧Electronic components

23‧‧‧Package

240‧‧‧ dielectric layer

241‧‧‧Line layer

27‧‧‧Carrier

28‧‧‧Support frame

280‧‧‧Placement area

3a‧‧‧Package unit

L‧‧‧ split path

S, S’‧‧‧ cutting path

1A to 1E are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package; and 2A to 2F are schematic cross-sectional views showing a method of fabricating the semiconductor package of the present invention; wherein 2A' and 2B' are 2A and The view above the 2B diagram, the 2F' diagram is the view below the 2F diagram.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper" and "one" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship is changed or adjusted. Substantially changing the technical content is also considered to be within the scope of the invention.

2A to 2F are schematic cross-sectional views showing the manufacturing method of the semiconductor package 2, 3 of the present invention.

As shown in Figures 2A and 2A', a support frame 28 is provided on a carrier member 20.

In this embodiment, the carrier 20 is a semiconductor substrate such as a wafer or a silicon plate or a glass substrate, and the carrier 20 is bonded to the support frame 28 by an adhesive layer 21 on the surface thereof.

Furthermore, the adhesive layer 21 is a thermal release tape.

Moreover, the support frame 28 is a metal frame having a plurality of placement areas 280 that expose the adhesive layer 21.

As shown in FIGS. 2B and 2B', a plurality of electronic components 22 are disposed on the adhesive layer 21 in the placement area 280, and a package 23 is formed on the adhesive layer 21 to encapsulate the electronic components 22 and support. frame.

In the present embodiment, the carrier 20 is bonded to the electronic components 22 by an adhesive layer 21 on the surface thereof.

Furthermore, the electronic component 22 is an active component, a passive component or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 22 has an opposite active surface 22a and an inactive surface 22b, and the electronic component 22 incorporates the adhesive layer 21 with its active surface 22a.

In addition, the package material 23 is formed on the carrier 20 by a lamination method or a molding method, and the material of the package material 23 is a dry film type epoxy resin (Epoxy). ) or a fluid epoxy resin, or an organic material such as ABF (Ajinomoto Build-up Film) resin.

As shown in FIG. 2C, a carrier 27 is bonded to the package 23 (above the inactive surface 22b of the electronic component 22), and the carrier 27 includes a bonding layer 270 disposed on the package 23. And a support member 271 disposed on the bonding layer 270.

In this embodiment, the material of the support member 271 is an inorganic material or an organic material, such as glass, bismuth (Si), ceramic, tantalum carbide (SiC), cerium oxide (SiO ₂ ), arsenic. Gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), indium phosphide (InP), gallium aluminum arsenide (GaAlAs) or indium gallium phosphide , InGaP), etc., the organic material is, for example, plastic, glass fiber reinforced resin (such as bismaleimide-triazine, BT for short), fiberglass reinforced epoxy resin (such as FR-4) or epoxy resin (epoxy) )Wait.

Furthermore, the bonding layer 270 is a viscous material such as a dry film epoxy resin.

Moreover, the bonding layer 270 may be formed on the support member 271 by spin coating, and the carrier 27 may be bonded to the package member 23.

Alternatively, the bonding layer 270 may be formed on the package 23, and the support member 271 may be bonded to the bonding layer 270.

As shown in FIG. 2D, the carrier 20 and the adhesive layer 21 are removed, and the active surface 22a of the electronic component 22 is exposed. Thereafter, the package 23 is cured.

In this embodiment, since the adhesive layer 21 is a thermal release tape, a heating process such as baking is performed to harden the package 23, and the adhesive layer 21 is heated together. The adhesive is lost, thereby removing the adhesive layer 21 and the carrier 20.

As shown in FIG. 2E, a line redistribution layer (RDL) process is performed, that is, a line redistribution structure 24 is formed on the package material 23, the support frame, and the electronic components 22, and the line redistribution structure is formed. 24 is electrically connected to each of the electronic components 22. Thereby, the semiconductor package 2 of the full-panel structure is completed.

In this embodiment, the circuit redistribution structure 24 includes at least one circuit layer 241 and at least one dielectric layer 240 stacked on each other. The dielectric layer 240 is formed on the package 23, and the circuit layer 241 is Electrically connecting the electronic component twenty two.

Then, an insulating protective layer (not shown, which can be referred to the insulating protective layer 15 of FIG. 1D) is formed on the circuit redistributing structure 24, and the insulating protective layer exposes a part of the surface of the circuit layer 241, and is used as an electrical property. Contact pads are used to bond other electronic devices (such as circuit boards) in conjunction with conductive elements 26 such as solder balls.

As shown in Figs. 2F and 2F', the separation process is performed along the division path L as shown in Fig. 2E (i.e., along the edges of the placement areas 280). The carrier 27 and the bonding layer 270 are then removed.

In this embodiment, the separation process divides the full-page structure into a plurality of package strips, such as the 8 package strips shown in FIG. 2B′, and the size of the package block is 100 mm × 240 mm, which is composed of a plurality of package units 3a (the range of the cutting path S' of the singulation process shown in Fig. 2F'). Specifically, the number of the electronic components 22 in the single package unit 3a can be determined according to requirements, that is, by adjusting the cutting path S' of the singulation process, for example, the single package unit 3a shown in FIG. 2F' has One electronic component 22, and in other embodiments, there may be four electronic components 22 in a single package unit 3a.

Furthermore, the package block is supported by the support frame 28 to avoid warping of the package block.

In other embodiments, the carrier 27 and the bonding layer 270 may be removed first, and then the separation process is performed.

In the manufacturing method of the present invention, the design of the support frame 28 is used to divide the entire layout structure into a package block having a size of 100 mm×240 mm, and In the process, the package block can be singulated to obtain the plurality of package units 3a. Therefore, the size of the full-page surface can be increased according to the requirement, and the size of the entire layout surface can be changed to increase the yield.

Furthermore, by designing the support frame 28, the entire layout structure can be divided into the singulation size required for the existing singulator (ie, the size of the package block), and mass production can be performed without additional development of a new machine. Therefore, it can reduce the cost of machine development.

Moreover, by the design of the support frame 28, the entire layout structure can be separated into the package blocks of the required size in an automated manner, and then placed in the existing singulator to increase the yield.

The present invention further provides a semiconductor package 2 comprising: a support frame 28 having a plurality of placement areas 280, a plurality of electronic components 22 housed in each of the placement areas 280, and a plurality of electronic components 22 formed in the placement areas 280. The package 23 covering the electronic components 22 is covered.

The semiconductor package 2 is a full-surface structure composed of a plurality of package blocks, and a plurality of the electronic components 22 are disposed in the single placement area 280.

The electronic component 22 has an opposite active surface 22a and an inactive surface 22b, and the active surface 22a of the electronic component 22 is exposed to the package 23.

The present invention also provides a semiconductor package 3, which is a package block composed of a plurality of package units 3a. The support frame 28 has only one placement area 280, and the plurality of electronic components 22 are housed in the placement area 280. .

In an embodiment, a circuit redistribution structure 24 is formed on the package 23 and the active surface 22a of the electronic component 22, and the circuit The redistribution structure 24 is electrically connected to the active surface 22a of the electronic component 22.

In an embodiment, a carrier 27 is formed on the package 23 .

In summary, the semiconductor package of the present invention and the method for manufacturing the same are mainly used to divide the entire layout structure into package blocks of a desired size by using the support frame, so that the existing machine can be used in the subsequent process. Production is carried out, so not only can the cost of machine development be saved, but also the size of the entire layout can be increased to increase production.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Semiconductor package

22‧‧‧Electronic components

23‧‧‧Package

24‧‧‧Line redistribution structure

240‧‧‧ dielectric layer

241‧‧‧Line layer

26‧‧‧Conductive components

27‧‧‧Carrier

28‧‧‧Support frame

280‧‧‧Placement area

L‧‧‧ split path

Claims (11)

A semiconductor package, which is a full-surface structure, comprising: a support frame having a plurality of placement areas, the frame of the support frame is located on the cutting path; and a plurality of electronic components are disposed in each of the placement areas, and A plurality of the electronic components are disposed in the single placement area; and an encapsulating material is formed in the placement areas to encapsulate the electronic components. A semiconductor package is a package block, comprising: a support frame having only one placement area, the frame of the support frame is located on the cutting track; and a plurality of electronic components are disposed in the placement area; An encapsulating material is formed in the placement area to encapsulate the electronic components. The semiconductor package of claim 1 or 2, wherein the electronic component has an opposite active surface and a non-active surface, and the active surface of the electronic component is exposed to the package. The semiconductor package of claim 3, further comprising a line redistribution structure formed on the active surface of the package and the electronic component, and the circuit redistribution structure electrically connecting the electronic components . The semiconductor package of claim 1 or 2, further comprising a carrier formed on the package. A method for manufacturing a semiconductor package, comprising: providing a support member having a support frame and a plurality of electronic components thereon, wherein the support frame has a plurality of placement areas for accommodating the electronic components, and Forming a package covering the electronic components and the support frame on the carrier; bonding a carrier to the package; removing the carrier; and performing a separation process along the placement areas. The method of fabricating a semiconductor package according to claim 6, wherein the electronic component has an opposite active surface and a non-active surface, and the electronic component is bonded to the carrier with its active surface. The method for manufacturing a semiconductor package according to claim 6 is characterized in that after removing the carrier, a circuit redistribution structure is formed on the package and the electronic component, and the circuit is re-wired. Sexually connect the electronic component. The method for fabricating a semiconductor package according to claim 6 is to include removing the carrier after performing the separation process. The method for manufacturing a semiconductor package according to claim 6 is characterized in that after the carrier is removed, the carrier is removed and the separation process is performed. The method for manufacturing a semiconductor package according to claim 6, wherein the method further comprises performing a singulation process after performing the separation process.