TWI611484B - Electronic package structure and the manufacture thereof - Google Patents

Abstract

An electronic package structure is formed by disposing a plurality of electronic components on opposite sides of a carrier and forming an encapsulation layer, so that the encapsulation layer encapsulates the electronic components, and then forming a wiring structure on the encapsulation layer to make the circuit structure The electronic components are electrically connected, and the electronic components, the encapsulation layer and the circuit structure are uniformly disposed on opposite sides of the carrier, so that the stress on both sides of the carrier can be balanced to prevent the carrier from occurring. Warping. The present invention provides the electronic package structure.

Description

Electronic package structure and its manufacturing method

The invention relates to a packaging technology, in particular to an electronic packaging structure with a full-page and a manufacturing method thereof.

With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements of miniaturization of electronic package structures, technologies such as Wafer Level Packaging (WLP) or Chip Scale Package (CSP) have been developed.

1A to 1E are schematic cross-sectional views showing a method of fabricating a semiconductor package of a conventional wafer level package.

As shown in FIG. 1A, a thermal release tape 100 is formed on a carrier 10 such as a substrate or an organic sheet.

Next, a plurality of semiconductor elements 11 are disposed on the thermal release layer 100, and the semiconductor elements 11 have opposing surfaces 11a and 11b, each of which has a plurality of electrode pads 110, and Each of the active surfaces 11a is adhered to the heated release layer 100.

As shown in FIG. 1B, an encapsulant 14 is formed on the thermal release layer 100 to encapsulate the semiconductor element 11.

As shown in FIG. 1C, the encapsulant 14 is baked to harden the thermal release layer 100, thereby removing the thermal release layer 100 and the carrier 10, thereby exposing the semiconductor element 11 Face 11a.

As shown in FIG. 1D, a wiring structure 16 is formed on the encapsulating body 14 and the active surface 11a of the semiconductor component 11, so that the wiring structure 16 is electrically connected to the electrode pad 110. Next, an insulating protective layer 18 is formed on the wiring structure 16, and the insulating protective layer 18 exposes a portion of the surface of the wiring structure 16 for bonding the conductive elements 17 such as solder balls.

As shown in FIG. 1E, a singulation process is performed along the dicing path L as shown in FIG. 1D to obtain a plurality of wafer-level package semiconductor packages 1.

However, in the process of the conventional semiconductor package 1, the carrier 10 is a full-face (ie, mass-produced), and the carrier 10 is disposed on only one side of the semiconductor device 11, so that when the encapsulant 14 is formed The carrier 10 is prone to thermal stress non-uniformity due to mismatch with the coefficient of thermal expansion (CTE) of the encapsulant 14 , resulting in the carrier 10 being generated during thermal cycling. Warpage, which in turn causes problems such as the falling of the ball (i.e., the conductive member 17) and the non-wetting of the conductive member 17.

Moreover, the warpage may also cause the structure in the process to be unable to be placed in the machine table, or the semiconductor element 11 may be chipped to lower the product yield.

In addition, the carrier 10 forms the semiconductor packages 1 on only a single side, resulting in a low throughput, which results in an extremely high production cost of the semiconductor package 1.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned deficiencies of the prior art, the present invention provides an electronic package structure including a plurality of package units, and each of the package units includes: an encapsulation layer having opposite first and second surfaces; at least one electronic component, Embedded in the encapsulation layer; and a wiring structure formed on the first surface of the encapsulation layer and electrically connected to the electronic component.

The invention provides a method for manufacturing an electronic package structure, comprising: providing a carrier having opposite first and second sides; and providing a plurality of electronic components on the first side and the second side of the carrier, and forming The encapsulation layer is on the first side and the second side of the carrier, so that the encapsulation layer covers the electronic components; and forming a wiring structure on the encapsulation layer, and electrically connecting the wire structure portions to the electronic components element.

In the foregoing method, the carrier is removed after forming the line structure.

In the foregoing electronic package structure and method of manufacturing the same, the layout structure above the second side of the carrier is the same as the layout above the first side of the carrier.

In the foregoing electronic package structure and method of fabricating the same, the complex includes forming a plurality of conductive elements on the line structure.

In the foregoing electronic package structure and method of manufacturing the same, the method further comprises forming a plurality of conductive pillars in the encapsulation layer and electrically connecting the wiring structure.

In the foregoing electronic package structure and method of manufacturing the same, the electronic component has a phase The working surface and the non-active surface have a plurality of electrode pads, and the electrode pads are combined with an electrical conductor, and the end faces of the electrical conductors expose the encapsulating layer.

It can be seen from the above that the electronic package structure of the present invention and the manufacturing method thereof can balance the first part of the carrier by mainly distributing the electronic component, the encapsulation layer and the line structure on the first side and the second side of the carrier. The stress on the side and the second side is such that the present invention prevents warpage of the carrier compared to conventional techniques.

Furthermore, in the present invention, since the electronic package can be fabricated on the first side and the second side of the carrier, the present invention can increase the throughput thereof compared with the prior art, thereby greatly reducing the manufacturing cost.

1‧‧‧Semiconductor package

10‧‧‧ Carrier

100‧‧‧heating release layer

11‧‧‧Semiconductor components

11a, 21a‧‧‧ action surface

11b, 21b‧‧‧ non-active surface

110,210‧‧‧electrode pads

14‧‧‧Package colloid

16‧‧‧Line structure

17,27‧‧‧Conducting components

18‧‧‧Insulating protective layer

2,3‧‧‧Electronic package structure

2a, 3a‧‧‧electronic package

20‧‧‧Carrier

20a‧‧‧ first side

20b‧‧‧ second side

200‧‧‧ metal layer

21‧‧‧Electronic components

212‧‧‧Electric conductor

214‧‧‧Combination layer

24‧‧‧Encapsulation layer

24a‧‧‧ first surface

24b‧‧‧second surface

26‧‧‧Line structure

260,260'‧‧‧Insulation

261‧‧‧Line redistribution

270‧‧‧ Metal layer under the bump

33‧‧‧conductive column

A‧‧‧Package unit

X‧‧‧ imaginary boundary

L‧‧‧ cutting path

1A to 1E are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package; and FIGS. 2A to 2F are cross-sectional views showing a first embodiment of the method for fabricating an electronic package structure of the present invention, wherein the 2F' is a FIG. 3A to FIG. 3B are schematic cross-sectional views showing a second embodiment of the electronic package structure of the present invention. FIG.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It should be noted that the structure, proportion and size depicted in the drawings of this specification And the like, which are used for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the invention, and thus do not have technical significance, any structural modification, The change of the proportional relationship or the adjustment of the size should be within the scope of the technical content disclosed by the present invention without affecting the effects and the achievable effects of the present invention. In the meantime, the terms "upper" and "one" as used in the specification are for convenience of description and are not intended to limit the scope of the invention, and the relative relationship may be changed or adjusted. Without substantial changes to the technical content, it is also considered to be within the scope of the invention.

2A to 2F are schematic cross-sectional views showing a first embodiment of the manufacturing method of the electronic package structure 2 of the present invention.

As shown in FIG. 2A, a carrier 20 having an opposite first side 20a and a second side 20b is provided, which may be optionally provided with a metal layer 200 on the first side 20a and the second side 20b. Then, a plurality of electronic components 21 are disposed on the first side 20a, and an encapsulation layer 24 is formed on the first side 20a to encapsulate the electronic component 21.

In this embodiment, the carrier 20 is a full-face (ie, mass production size), and the carrier 20 is an insulating plate, and a release layer (not shown) can be coated thereon to make the carrier The release layer is provided between the metal layer 200 and the metal layer 200.

Furthermore, the electronic component 21 is an active component, a passive component or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. In this embodiment, the electronic component 21 The semiconductor wafer has an opposite active surface 21a and an inactive surface 21b. The electronic component 21 is adhered to the first side 20a by a bonding layer 214, and the active surface 21a is adhered to the first side 20a. A plurality of electrode pads 210 are disposed, and the plurality of electrical conductors 212 are electrically coupled to the electrode pads 210. Specifically, the conductor 212 is a ball shape such as a solder ball, or a columnar shape of a metal material such as a copper post or a solder bump, or a stud made by a wire bonding machine, but is not limited thereto.

Moreover, the encapsulation layer 24 is an insulating material, such as an encapsulant of epoxy resin, which may be formed on the first side 20a by lamination or molding.

Additionally, the encapsulation layer 24 has opposing first and second surfaces 24a, 24b joined to the first side 20a by the second surface 24b.

As shown in FIG. 2B, a plurality of electronic components 21 are disposed on the second side 20b of the carrier 20, and an encapsulation layer 24 is formed on the second side 20b to allow the encapsulation layer 24 to encapsulate the electronic components. twenty one.

In the embodiment, the electronic components 21 and the encapsulation layer 24 are disposed on the first side 20a, and the electronic components 21 and the encapsulation layer 24 are disposed on the second side 20b. In another embodiment, after the electronic components 21 are disposed on the first side 20a and the second side 20b of the carrier 20, the encapsulation layer 24 is formed on the first side 20a of the carrier 20. With the second side 20b.

As shown in FIG. 2C, the first surface 24a of the encapsulation layer 24 is flushed with the surface of the conductor 212 by the leveling process, so that the end surface of the conductor 212 is exposed on the first surface 24a of the encapsulation layer 24. .

In this embodiment, the leveling process removes a portion of the material of the encapsulation layer 24 by grinding (a portion of the material of the conductor 212 may also be removed as needed).

It should be understood that, when the encapsulation layer 24 is formed, the electrical conductor 212 is exposed to the encapsulation layer 24, and no flattening process is required.

As shown in FIG. 2D, a wiring structure 26 is formed on the first surface 24a of the encapsulation layer 24, and the wiring structure 26 is electrically connected to the electrical conductors 212.

In this embodiment, the circuit structure 26 includes a plurality of insulating layers 260, 260', and a redistribution layer (RDL) 261 disposed on the insulating layers 260, 260' and electrically connected to the electrical conductors 212. The outermost insulating layer 260' can serve as a solder resist layer to expose a portion of the surface of the outermost layer redistribution layer 261 to the solder resist layer. Alternatively, the line structure 26 may also include only a single insulating layer 260 and a single line redistribution layer 261.

Furthermore, the material forming the circuit redistribution layer 261 is copper, and the material of the insulating layer 260, 260' is formed such as poly-p-oxazobenzene (PBO), polyimide (PI), pre-dip. A dielectric material (Prepreg, PP for short) or a solder material such as green paint.

Moreover, the laying structure above the second side 20b of the carrier 20 is the same as the laying structure above the first side 20a of the carrier 20.

In addition, the encapsulation layer 24 defines a plurality of adjacent package units A (such as the imaginary boundary line X shown in FIG. 2D), and each package unit A includes at least one of the electronic components 21.

As shown in FIG. 2E, the carrier 20 (and the release layer thereon) is removed and the metal layer 200 is retained.

As shown in FIG. 2F, the metal layer 200 is removed by, for example, etching or otherwise, and the bonding layer 214 (or the non-active surface 21b of the electronic component 21) is exposed. Next, a plurality of conductive elements 27, such as solder balls, are formed on the outermost circuit redistribution layer 261 for subsequent connection to an electronic device such as a package structure or other structure such as another package or wafer (not shown).

In this embodiment, an Under Bump Metallurgy (UBM) 270 can be formed on the outermost circuit redistribution layer 261 to facilitate bonding of the conductive element 27.

In addition, the electronic package structure 2 defines a plurality of package units A (ie, the electronic package 2a), wherein each of the package units A (the electronic package 2a) has at least one of the electronic components 21 and encapsulates the electronic components. The encapsulation layer 24 of 21, and the circuit structure disposed on the electronic component 21 and the encapsulation layer 24, that is, a single electronic component 21 can be provided in a single electronic package 2a.

Further, a singulation process can be performed in a subsequent process to obtain a CSP electronic package 2a as shown in Fig. 2F'.

Therefore, the method of the present invention is characterized in that the first side 20a and the second side 20b of the carrier 20 are uniformly provided with the electronic component 21, the encapsulation layer 24 and the circuit structure 26 (preferably, the second of the carrier 20). The arrangement above the side 20b is the same as the arrangement above the first side 20a of the carrier 20, and the stress on the first side 20a and the second side 20b of the carrier 20 can be balanced, so during thermal cycling. , can prevent the carrier 20 from warping to avoid occurrence The problem that the ball is dropped or cracked, and the electronic component 21 can be prevented from being chipped, thereby improving the product yield.

Furthermore, the method of the present invention can be used to fabricate the electronic package 2a on the first side 20a and the second side 20b of the carrier 20. Therefore, the productivity of the present invention can be improved as compared with the prior art. At least twice the system, which can significantly reduce production costs.

3A to 3B are cross-sectional views showing a second embodiment of the manufacturing method of the electronic package structure 3 of the present invention. The difference between this embodiment and the first embodiment is that a new conductive column is added, so only the differences will be described below, and the same points will not be described again.

As shown in FIG. 3A, in the process of FIG. 2A, a plurality of conductive pillars 33 are formed on the first side 20a, so that the encapsulation layer 24 covers the conductive pillars 33, and the process of FIG. 2B is performed. A plurality of conductive pillars 33 are formed on the second side 20b to cover the conductive pillars 33.

In the embodiment, in the leveling process of FIG. 2C, the first surface 24a of the encapsulation layer 24 is flush with the end surface of the conductive pillar 33 and the end surface of the conductor 212, so that the end surface of the conductive pillar 33 and the conductor The end face of 212 is exposed to the encapsulation layer 24. For example, in the leveling process, part of the material of the conductive pillar 33 and the conductor 212 may be removed.

Furthermore, in the circuit structure process of FIG. 2D, the circuit redistribution layer 261 of the circuit structure 26 is electrically connected to the conductive pillar 33 and the electrical conductor 212, wherein the material of the conductive pillar 33 is formed as copper. Metal or solder.

Moreover, in another embodiment, after the leveling process of FIG. 2C, A through hole penetrating the encapsulation layer 24 is formed, and then a metal material is formed in the perforation as the conductive post 33.

As shown in FIG. 3B, in the process shown in FIGS. 2E and 2F, the carrier 20 (and the release layer thereon) and the metal layer 200 are removed, so that the end face of the conductive post 33 is exposed. The second surface 24b of the encapsulation layer 24. Next, the conductive elements 27 are formed on the line structure 26.

In the embodiment, the electronic package structure 3 defines a plurality of electronic packages 3a, and the single electronic package 3a has at least one of the electronic components 21.

Therefore, the method of the present invention balances the carrier 20 by distributing the electronic component 21, the conductive pillars 33, the encapsulation layer 24 and the wiring structure 26 on the first side 20a and the second side 20b of the carrier 20. The stress on the first side 20a and the second side 20b is such that during the thermal cycle, the carrier 20 can be prevented from warping to avoid problems such as falling or cracking of the ball, and the electronic component 21 can be avoided. Fragmentation occurs, which in turn increases product yield.

Furthermore, the method of the present invention can be used to fabricate the electronic package 3a on the first side 20a and the second side 20b of the carrier 20. Therefore, the productivity of the present invention can be improved as compared with the prior art. Double the system, which can significantly reduce production costs.

The present invention provides an electronic package structure 2, 3 comprising a plurality of package units A (electronic package 2a), and each package unit A comprises: an encapsulation layer 24, at least one electronic component 21, and a line structure 26.

The encapsulation layer 24 has opposite first and second surfaces 24a, 24b.

The electronic component 21 is embedded in the encapsulation layer 24, and a plurality of electrical conductors 212 are disposed on the active surface of the electronic component 21.

The circuit structure 26 is formed on the first surface 24a of the encapsulation layer 24 and electrically connected to the electrical conductor 212 of the electronic component 21.

In one embodiment, the electronic package structure 2, 3 includes a carrier 20 having a first side 20a and a second side 20b opposite thereto, with the first side 20a bonded to the second surface 24b of the encapsulation layer 24. on. For example, the laying structure above the second side 20b of the carrier 20 is the same as the laying structure above the first side 20a of the carrier 20, that is, the second side 20b of the carrier 20 is formed with the first The encapsulation layer 24, the electronic component 21, and the wiring structure 26 corresponding to one side 20a.

In one embodiment, the electronic package structure 2, 3 includes a plurality of conductive elements 27 formed on the line structure 26.

In one embodiment, the electronic package structure 3 includes a plurality of conductive pillars 33 formed in the package layer 24 and electrically connected to the circuit structure 26 .

In summary, the electronic package structure of the present invention and the method for manufacturing the electronic package are performed on the first side and the second side of the carrier to prevent the carrier from being warped during thermal cycling. Qu, so it can avoid the problems caused by the warpage of the bearing.

Furthermore, in the present invention, since the electronic package can be fabricated on the first side and the second side of the carrier, the production capacity can be increased, thereby reducing the manufacturing cost.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Anyone who is familiar with this skill can The above embodiments are modified without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

20‧‧‧Carrier

20a‧‧‧ first side

20b‧‧‧ second side

21‧‧‧Electronic components

212‧‧‧Electric conductor

24‧‧‧Encapsulation layer

24a‧‧‧ first surface

26‧‧‧Line structure

260,260'‧‧‧Insulation

261‧‧‧Line redistribution

A‧‧‧Package unit

X‧‧‧ imaginary boundary

Claims (11)

An electronic package structure comprising a plurality of package units, and each package unit comprises: an encapsulation layer having opposite first and second surfaces; and a carrier having opposite first and second sides The first side is bonded to the second surface of the encapsulation layer; at least one electronic component is embedded in the encapsulation layer; and the circuit structure is formed on the first surface of the encapsulation layer and electrically connected to the electron And an element, wherein the second side of the carrier is formed with an encapsulation layer, an electronic component and a wiring structure corresponding to the first side of the carrier. The electronic package structure of claim 1, further comprising a plurality of conductive elements formed on the circuit structure. The electronic package structure of claim 1, further comprising a plurality of conductive pillars formed in the encapsulation layer and electrically connected to the circuit structure. The electronic package structure of claim 1, wherein the electronic component has a relative active surface and a non-active surface, the active surface has a plurality of electrode pads, the electrode pads are combined with an electrical conductor, and the electrical conductor The end face exposes the encapsulation layer. An electronic package structure includes: providing a carrier having opposite first and second sides; and providing a plurality of electronic components on the first side and the second side of the carrier, and forming an encapsulation layer thereon a first side and a second side of the carrier to encapsulate the electronic component; and Forming a wiring structure on the encapsulation layer, and electrically connecting the circuit structures to the electronic components to form an electronic package structure. The method for manufacturing an electronic package structure according to claim 5, wherein the method further comprises: after forming the line structure, removing the carrier. The method of fabricating an electronic package structure according to claim 5, further comprising forming a plurality of conductive elements on the line structure. The method for manufacturing an electronic package structure according to claim 5, further comprising forming a plurality of conductive pillars in the encapsulation layer, and electrically connecting the wiring structure to the conductive pillar. The method of manufacturing an electronic package structure according to claim 5, wherein the electronic package structure defines a plurality of electronic packages, each of the electronic packages having at least one of the electronic components and an encapsulation layer covering the electronic components And a circuit structure disposed on the electronic component and the encapsulation layer. The method for manufacturing an electronic package structure according to claim 9 of the patent application, further comprising performing a singulation operation to separate the electronic packages. The method of manufacturing an electronic package structure according to claim 5, wherein the electronic component has a relative active surface and a non-active surface, the active surface has a plurality of electrode pads, and the electrode pads are combined with a conductor, and the electrode pad The end face of the electrical conductor exposes the encapsulation layer.