JPS624351A - Manufacture of semiconductor carrier - Google Patents
Manufacture of semiconductor carrierInfo
- Publication number
- JPS624351A JPS624351A JP60143734A JP14373485A JPS624351A JP S624351 A JPS624351 A JP S624351A JP 60143734 A JP60143734 A JP 60143734A JP 14373485 A JP14373485 A JP 14373485A JP S624351 A JPS624351 A JP S624351A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor carrier
- semiconductor
- chip
- chips
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体チップを小型パッケージに実装した半
導体キャリアの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor carrier in which a semiconductor chip is mounted in a small package.
ＩＣ，ＬＳＩ等の半導体素子の実装法については従来よ
り様々なものがあるが、その一つとして半導体チップを
セラミック製のパッケージ内にマウントし、パッケージ
に設けられた入出力端子に導体パターンを介して接続さ
れた電極パッドと、チップの電極パッドとをワイヤボン
ディングにより接続して半導体キャリア（チップキャリ
アともいう）を得る方法がある。There are various methods of mounting semiconductor elements such as ICs and LSIs, one of which is to mount the semiconductor chip in a ceramic package and connect the input/output terminals provided in the package with conductive patterns. There is a method of obtaining a semiconductor carrier (also referred to as a chip carrier) by connecting electrode pads connected to each other and electrode pads of a chip by wire bonding.
しかしながら、このような方法では半導体キャリアの小
型化に限界がある。即ち、縦横方向についてはチップと
パッケージ内壁との間にスペースが必要なために、寸法
がチップの縦横寸法に比較してかなり大きくなる。高さ
方向については、パッケージ底面の厚さとチップの厚さ
およびボンディングワイヤの占める高さの合計に若干の
マージンを見た寸法が必要であり、２． ５Ｊｌ１１程
度が限界となっている。However, there is a limit to the miniaturization of semiconductor carriers in such a method. That is, since a space is required between the chip and the inner wall of the package in the vertical and horizontal directions, the dimensions become considerably larger than the vertical and horizontal dimensions of the chip. Regarding the height direction, the dimensions must include a slight margin in the sum of the thickness of the bottom of the package, the thickness of the chip, and the height occupied by the bonding wire; 2. The limit is about 5Jl11.
また、この方法では半導体チップをチップ単位で、予め
用意されたパッケージに別々に実装するため、多数のキ
ャリアをまとめて製造することができず、生産性の面で
も問題があった。In addition, in this method, semiconductor chips are individually mounted in pre-prepared packages, making it impossible to manufacture a large number of carriers at once, which poses a problem in terms of productivity.
本発明はこのような従来の問題点に鑑みてなされたもの
で、より小型な半導体キャリアが得られ、しかも生産性
の良い半導体キャリアの製造方法を提供することを目的
とする。The present invention has been made in view of these conventional problems, and an object of the present invention is to provide a method for manufacturing a semiconductor carrier that allows a smaller semiconductor carrier to be obtained and that has good productivity.
本発明はこの目的を達成するため、まず、素子が形成さ
れ且つ電極パッドを有する半導体ウェハを可撓性支持シ
ート上で個々のチップに切断し、該シートを伸長させる
ことによって、そのチップ間間隙を拡大する。In order to achieve this object, the present invention first cuts a semiconductor wafer on which elements are formed and has electrode pads into individual chips on a flexible support sheet, and then stretches the sheet so that the gaps between the chips are Expand.
次に、チップをシート上に載せた状態で、この拡大され
たチップ間間隙を埋めるように、半導体キャリアの側面
部材となる絶縁体フレームを装着して、各チップの位置
を固定する。絶縁体フレームは例えば、予め作製された
樹脂成型品が使用されるか、あるいはチップ間間隙に紫
外線硬化性樹脂樹脂を充填した後、固化させることによ
り、て形成される。Next, with the chips placed on the sheet, an insulator frame serving as a side member of the semiconductor carrier is attached so as to fill the expanded gap between the chips, thereby fixing the position of each chip. The insulator frame is formed, for example, by using a resin molded product prepared in advance, or by filling the gap between the chips with an ultraviolet curable resin and then solidifying the resin.
次に、この絶縁体フレームが装着された状態で、半導体
キャリアの表面部材となる絶縁層をチップ上に形成する
。この絶縁層としては、例えばフォトレジストのような
紫外線硬化性樹脂、また°はポリイミド、アクリル、エ
ポキシ、ブタジェン等の熱硬化性樹脂を用いることがで
きる。Next, with this insulator frame attached, an insulating layer that will become the surface member of the semiconductor carrier is formed on the chip. As this insulating layer, for example, an ultraviolet curable resin such as a photoresist, or a thermosetting resin such as polyimide, acrylic, epoxy, butadiene, etc. can be used.
次に、この絶縁層の半導体チップに設けられた電極パッ
ド上方を選択的に溶解して、開口部を形成する。絶縁層
が上述したような樹脂で形成されている場合、これを選
択的に溶解するには、反応性イオンエツチング、ケミカ
ルドライエツチング、または紫外線照射等による光反応
、あるいはレーザ、マイクロ波照射等による熱反応を利
用すればよい。Next, the insulating layer above the electrode pads provided on the semiconductor chip is selectively dissolved to form an opening. If the insulating layer is made of the resin described above, in order to selectively dissolve it, photoreaction such as reactive ion etching, chemical dry etching, ultraviolet irradiation, or laser or microwave irradiation may be used. A thermal reaction can be used.
次に、絶縁体フレームおよび絶縁層の表面に、該絶縁層
に形成された開口部を通して半導体チップの電極パッド
と接続される導体パターンを形成する。Next, a conductor pattern is formed on the surfaces of the insulating frame and the insulating layer to be connected to the electrode pads of the semiconductor chip through the openings formed in the insulating layer.
そして、最後に半導体チップの相互間で絶縁体フレーム
を切断することにより、チップ単位に分割された半導体
キャリアを得る。Finally, by cutting the insulator frame between the semiconductor chips, semiconductor carriers divided into chip units are obtained.
なお、半導体キャリアの入出力端子としては例えば、半
導体チップの電極パッドに接続された導体パターンの端
部をそのまま使用することができる。また、絶縁体フレ
ームに上記導体パターンと接触する位置に金属ピンを挿
入しておけば、この金属ピンを入出力端子とすることも
できる。さらに別の方法として、絶縁体フレームに開口
部を設けておき、ここに例えば上記導体パターンの形成
時に導体を同時に充填しておけば、絶縁体フレームを切
断した時に半導体キャリアの側面上に該導体が露出する
ので、これを入出力端子とすることが可能である。Note that, for example, the ends of the conductive patterns connected to the electrode pads of the semiconductor chip can be used as they are as the input/output terminals of the semiconductor carrier. Furthermore, if a metal pin is inserted into the insulator frame at a position where it contacts the conductor pattern, this metal pin can be used as an input/output terminal. Still another method is to provide an opening in the insulator frame and fill it with a conductor at the same time, for example, when forming the above-mentioned conductor pattern, so that when the insulator frame is cut, the conductor will appear on the side surface of the semiconductor carrier. is exposed, so it can be used as an input/output terminal.
本発明の方法によって得られた半導体キャリアは、絶縁
体フレームの構成部材からなる側面部材と絶縁層からな
る上面部材とにより形成されたパッケージに半導体チッ
プが埋め込まれ、しかもチップ上の電極パッドとキャリ
アの入出力端子とが導体パターンによって接続された構
造となるので、従来法によって得られた半導体キャリア
に比較して小型化される。即ち、従来法では予め別工程
で作製されたパッケージ内にチップをマウントする関係
で、パッケージ内壁とチップとの間にスペースが必要で
あるため、縦横寸法が増加するが、本発明によるとこの
ようなスペースが不要であり、またワイヤボンディング
のためのスペースが不要であるため、高さ方向の寸法も
大きく減少する。The semiconductor carrier obtained by the method of the present invention has a semiconductor chip embedded in a package formed by a side member consisting of an insulating frame component and a top member consisting of an insulating layer, and electrode pads on the chip and a carrier. Since the structure is such that the input and output terminals of the semiconductor carrier are connected to each other by a conductive pattern, the semiconductor carrier is smaller in size than a semiconductor carrier obtained by a conventional method. In other words, in the conventional method, the chip is mounted in a package that has been prepared in a separate process in advance, which requires a space between the inner wall of the package and the chip, which increases the vertical and horizontal dimensions. Since no additional space is required, and no space is required for wire bonding, the height dimension is also greatly reduced.
さらに、本発明によると同一の半導体ウェハから切出さ
れたチップを、一連の工程で同時に半導体キャリア化で
きるため、チップ単位で別々に半導体キャリアにする従
来法に比較して生産性が著しく向上し、キャリアの単価
を引下げることが可能である。Furthermore, according to the present invention, chips cut from the same semiconductor wafer can be made into semiconductor carriers at the same time in a series of steps, which significantly improves productivity compared to the conventional method of making semiconductor carriers for each chip separately. , it is possible to lower the unit price of carriers.
第１図を参照して本発明の第１の実施例を説明する。ま
ず、第１図（ａ）に示すように既に素子が形成され、且
つ所要位置に電極パッドが形成された半導体ウェハ１に
、チップ切出し用の切れ口２を入れた後、ウェハ１を同
図（ｂ）に示すようにゴムシートのような可撓性シート
３上に貼り付ける。この状態で例えばローラ等を用いて
ウェハ１に適当な力を加えることにより、ウェハ１を切
れ目２に沿って切断して個々の半導体チップ４に分割す
る。この後、シート３を四方へ方に伸長することにより
、第１図（Ｃ）に示すようにチップ４間の間隙を拡大す
る。この第１図（ｃ）の状態では、チップ４間の間隙は
規定されていない。A first embodiment of the present invention will be described with reference to FIG. First, as shown in FIG. 1(a), a cut 2 for chip cutting is made in a semiconductor wafer 1 on which elements have already been formed and electrode pads are formed at required positions, and then the wafer 1 is As shown in (b), it is pasted onto a flexible sheet 3 such as a rubber sheet. In this state, by applying an appropriate force to the wafer 1 using, for example, a roller, the wafer 1 is cut along the cuts 2 and divided into individual semiconductor chips 4. Thereafter, by stretching the sheet 3 in all directions, the gap between the chips 4 is enlarged as shown in FIG. 1(C). In this state shown in FIG. 1(c), the gap between the chips 4 is not defined.
次に、第１図（ｄ）に示すような絶縁体フレーム５を用
意し、これを同図（ｅ）に示す如くチップ４間の間隙を
埋めるように装着する。絶縁体フレーム５は、この例で
は樹脂の成型品が使用される。Next, an insulator frame 5 as shown in FIG. 1(d) is prepared and mounted so as to fill the gap between the chips 4 as shown in FIG. 1(e). In this example, the insulator frame 5 is made of resin.
次に、第１図（ｆ）に示すようにチップ４上に絶縁層６
を形成する。この絶縁層６は例えばチップ４上に紫外線
硬化性樹脂を充填し、これを上側から紫外線の照射によ
り硬化させることによって形成することができる。Next, as shown in FIG. 1(f), an insulating layer 6 is placed on the chip 4.
form. This insulating layer 6 can be formed, for example, by filling the chip 4 with an ultraviolet curable resin and curing it by irradiating ultraviolet rays from above.
次に、第１図（ｇ）（ｈ）に示すように絶縁層６の、チ
ップ４上の電極パッド４ａ上方に開口部７を形成する。Next, as shown in FIGS. 1(g) and 1(h), an opening 7 is formed in the insulating layer 6 above the electrode pad 4a on the chip 4.
この開口部７の形成方法としては、絶縁層６が紫外線硬
化性樹脂の場合は例えば開口部７を形成すべき部分を選
択的に露光した後、ＲＩＥ（反応性イオンエツチング）
またはＣＤＥ（ケミカルドライエツチング）、または紫
外線の照射による光反応、あるいはレーザ光またはマイ
クロ波の照射による熱反応を利用して除去すればよい。When the insulating layer 6 is made of an ultraviolet curable resin, the opening 7 can be formed by, for example, selectively exposing the portion where the opening 7 is to be formed, and then performing RIE (reactive ion etching).
Alternatively, it may be removed using CDE (chemical dry etching), a photoreaction caused by ultraviolet irradiation, or a thermal reaction caused by laser light or microwave irradiation.
次に、第１図（ｉ）（ｊ）に示すように、絶縁体フレー
ム５および絶縁層６上に導体パターン８を形成する。こ
の導体パターン８の一端側は第１図（ｇ）（ｈ）の工程
により形成された開口部７を通してチップ４上の電極パ
ッド４ａと接続され、他端側はフレーム５上に延在され
る。導体パターン８の形成法としては、無電解めっき、
蒸着またはＣＶＤとフォトエツチングの工程、あるいは
印刷、導体箔の接着等のいずれでもよく、特に限定され
ない。ここで、チップ４間の間隙がフレーム５によって
均一に規定されていることにより、導体パターン８のパ
ターニングを全チップ４について共通にできる、即ちフ
ォトエツチングで用いるマスクや、印刷で用いるスクリ
ーン等のパターンが単純な繰返しパターンでよいから、
導体パターン８の形成を容易に行なうことができる。Next, as shown in FIGS. 1(i) and 1(j), a conductive pattern 8 is formed on the insulating frame 5 and the insulating layer 6. One end side of this conductor pattern 8 is connected to the electrode pad 4a on the chip 4 through the opening 7 formed by the steps shown in FIGS. 1(g) and 1(h), and the other end side is extended on the frame 5. . The method of forming the conductor pattern 8 includes electroless plating,
It may be a process of vapor deposition, CVD and photoetching, printing, adhesion of conductive foil, etc., and is not particularly limited. Here, since the gaps between the chips 4 are uniformly defined by the frame 5, the patterning of the conductor pattern 8 can be made common to all the chips 4, that is, the pattern of a mask used in photo etching, a screen used in printing, etc. can be a simple repeating pattern,
The conductor pattern 8 can be easily formed.
そして、最後に第１図（ｆ）の破線に沿って絶縁体フレ
ーム５を切断することにより、チップ４単位に分割され
た半導体キャリアを得る。フレーム５の切断の手段とし
ては、半導体チップを切断するのに通常使用される自動
送り切断機を用いることができる。即ち、個々のチップ
４間の間隙はフレーム５によって規定されているため、
フレーム５を自動送り切断機により一定ピッチでＸ、Ｙ
方向に送りながら切断することが可能である。Finally, by cutting the insulator frame 5 along the broken line in FIG. 1(f), a semiconductor carrier divided into four chips is obtained. As a means for cutting the frame 5, an automatic feed cutter commonly used for cutting semiconductor chips can be used. That is, since the gaps between the individual chips 4 are defined by the frame 5,
Frame 5 is cut at a constant pitch in X and Y using an automatic feed cutting machine.
It is possible to cut while feeding in the direction.
以上の工程により、第１図（ｋ）に示すような、チップ
４の側面がフレーム５の構成部材、上面が絶縁層６でそ
れぞれ覆われ、且つ導体パターン８の端部を入出力端子
とする半導体キャリア９を同時に多数個得ることができ
る。導体パターン８の端部に形成された入出力端子は、
例えば半導体キャリア８を基板等に実装する場合のワイ
ヤボンディングとして用いられる。Through the above steps, the side surfaces of the chip 4 are covered with the constituent members of the frame 5, and the top surface is covered with the insulating layer 6, as shown in FIG. 1(k), and the ends of the conductive patterns 8 are used as input/output terminals. A large number of semiconductor carriers 9 can be obtained at the same time. The input/output terminals formed at the ends of the conductor pattern 8 are
For example, it is used as wire bonding when mounting the semiconductor carrier 8 on a substrate or the like.
次に、第２図を参照して本発明の第２の実施例を説明す
る。第２図（ａ）〜（ｇ）はそれぞれ第１図の（ｅ）〜
（ｋ）に対応する工程を示している。この実施例では第
２図（ａ）に示すように、絶縁体フレーム５に予め金属
ピン１０を挿入しておく。そして、以後は第２図（ｂ）
〜（ｆ）に示すように第１図（ｆ）〜（ｊ）と同様の工
程を行なえば、導体パターン８と金属ピン１０とが接触
されることにより、第２図（ｇ）に示すような、チップ
４の側面がフレーム５の構成部材、上面が絶縁層６でそ
れぞれ覆われ、且つ導体パターン８の端部に接続された
金属ピン１０を入出力端子とする半導体キャリア１１が
得られる。Next, a second embodiment of the present invention will be described with reference to FIG. Figure 2 (a) to (g) are respectively (e) to (e) in Figure 1.
The process corresponding to (k) is shown. In this embodiment, as shown in FIG. 2(a), a metal pin 10 is inserted into the insulator frame 5 in advance. From then on, see Figure 2(b)
1 (f) to (j) as shown in FIG. 1 (f), the conductor pattern 8 and the metal pin 10 are brought into contact, and as shown in FIG. 2 (g). A semiconductor carrier 11 is obtained in which the side surfaces of the chip 4 are covered with the constituent members of the frame 5, and the top surface is covered with the insulating layer 6, and the metal pins 10 connected to the ends of the conductive patterns 8 serve as input/output terminals.
第３図に本発明の第３の実施例を示す。第３図（ａ）〜
（ｇ）は第１図（ｅ）〜（ｋ）に対応する工程を示して
いる。この実施例において第３図（ａ）（ｂ）までの工
程は第１図の実施例と同様であり、第３図（ｃ）（ｄ）
の工程において絶縁層６に電極パッド４ａ上の開口部７
を形成する際、同時に絶縁体フレーム５にこれらの開口
部７にそれぞれ対応した開口部１２を形成する。そして
、第３図（ｅ）（ｆ）の工程において導体バ′ターン８
を形成する際、同時にフレーム５の開口部１２に導体１
３を充填する。この後、先と同様に絶縁体フレーム５を
切断すれば、第３図（ｇ）に示すような、チップ４の側
面がフレーム５の構成部材、上面が絶縁層６でそれぞれ
覆われ、且つ導体パターン８の端部に接続された導体１
３が側面に入出力端子として露出した半導体キャリア１
４を得ることができる。FIG. 3 shows a third embodiment of the present invention. Figure 3(a)~
(g) shows the steps corresponding to FIGS. 1(e) to (k). In this embodiment, the steps up to FIGS. 3(a) and 3(b) are the same as the embodiment shown in FIG.
In the process, an opening 7 above the electrode pad 4a is formed in the insulating layer 6.
At the same time, openings 12 corresponding to these openings 7 are formed in the insulator frame 5. Then, in the steps shown in FIGS. 3(e) and 3(f), the conductor pattern 8 is
When forming the conductor 1, the conductor 1 is placed in the opening 12 of the frame 5 at the same time.
Fill 3. After that, if the insulating frame 5 is cut in the same manner as before, the side surfaces of the chip 4 are covered with the constituent members of the frame 5, the top surface is covered with the insulating layer 6, and the conductor is covered with the constituent members of the frame 5, as shown in FIG. 3(g). Conductor 1 connected to the end of pattern 8
Semiconductor carrier 1 with 3 exposed as input/output terminals on the side
You can get 4.
なお゛、本発明は上記した実施例に限定されるものでは
なく、その要旨を逸脱しない範囲で種々変形して実施す
ることができる。例えば実施例では絶縁体フレーム５を
樹脂の成型品として説明したが、第１図（Ｃ）の工程後
、チップ４間の間隙に紫外線硬化性樹脂または熱硬化性
樹脂を充填し、それを硬化させてもよい。このチップ間
間隙への樹脂の充填を、絶縁層６となる樹脂の充填と同
時に行なうことも可能であり、その場合、例えば紫外線
硬化性樹脂を充填後、チップ４をマスクとして下側から
紫外線を照射し、いわゆるセルフアライメントによりチ
ップ４間の領域のみを先に硬化させて絶縁体フレームを
形成し、その後に絶縁層６となる領域を硬化させればよ
い。Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof. For example, in the embodiment, the insulator frame 5 was explained as a resin molded product, but after the process shown in FIG. You may let them. It is also possible to fill the gap between the chips with resin at the same time as filling the resin that will become the insulating layer 6. In that case, for example, after filling the ultraviolet curable resin, ultraviolet rays are applied from below using the chips 4 as a mask. It is sufficient to irradiate and harden only the area between the chips 4 first by so-called self-alignment to form an insulator frame, and then harden the area that will become the insulating layer 6.
第１図（ａ）〜（ｋ）は本発明の第１の実施例に係る半
導体キャリアの製造工程を説明するための図、第２図（
ａ）〜（ｇ）は本発明の第２の実施例に係る製造工程の
第１図と異なる部分を説明するための図、第３図（ａ）
〜（ｇ）は本発明の第３の実施例に係る製造工程の第１
図と異なる部分を説明するための図である。
１・・・半導体ウェハ、２・・・切れ目、３・・・可撓
性シート、４・・・半導体チップ、５・・・絶縁体フレ
ーム、６・・・絶縁層、７・・・開口部、８・・・導体
パターン、９・・・半導体キャリア、１０・・・金属ピ
ン、１１・・・半導体キャリア、１２・・・開口部、１
３・・・導体、１４・・・半導体キャリア。1(a) to (k) are diagrams for explaining the manufacturing process of a semiconductor carrier according to the first embodiment of the present invention, and FIG.
a) to (g) are diagrams for explaining the different parts from FIG. 1 of the manufacturing process according to the second embodiment of the present invention, and FIG. 3(a)
~(g) is the first manufacturing process according to the third embodiment of the present invention.
FIG. 3 is a diagram for explaining parts different from the figures. DESCRIPTION OF SYMBOLS 1... Semiconductor wafer, 2... Cut, 3... Flexible sheet, 4... Semiconductor chip, 5... Insulator frame, 6... Insulating layer, 7... Opening part , 8... Conductor pattern, 9... Semiconductor carrier, 10... Metal pin, 11... Semiconductor carrier, 12... Opening, 1
3...Conductor, 14...Semiconductor carrier.
Claims (7)
ェハを可撓性支持シート上で個々のチップに切断し、該
シートを伸長させてそのチップ間間隙を拡大する工程と
、 前記シート上で該チップ間間隙を埋める絶縁体フレーム
を装着する工程と、 この絶縁体フレームが装着された状態で前記チップ上に
絶縁層を形成する工程と、 この絶縁層の前記電極パッド上方に開口部を形成する工
程と、 この開口部を通して前記電極パッドと接続される導体パ
ターンを前記絶縁体フレームおよび前記絶縁層の表面に
形成する工程と、 この導体パターンの形成後、前記チップの相互間で前記
絶縁体フレームを切断することにより、チップ単位に分
割された半導体キャリアを得る工程とを備えたことを特
徴とする半導体キャリアの製造方法。(1) cutting a semiconductor wafer on which elements are formed and having electrode pads into individual chips on a flexible support sheet, and stretching the sheet to enlarge the inter-chip gap; a step of mounting an insulator frame that fills the gap between chips; a step of forming an insulating layer on the chip with the insulator frame mounted; and forming an opening above the electrode pad in the insulating layer. forming a conductive pattern on the surface of the insulating frame and the insulating layer to be connected to the electrode pad through the opening; and after forming the conductive pattern, connecting the insulating frame between the chips; A method for manufacturing a semiconductor carrier, comprising: obtaining a semiconductor carrier divided into chips by cutting the semiconductor carrier.
徴とする特許請求の範囲第１項記載の半導体キャリアの
製造方法。(2) The method for manufacturing a semiconductor carrier according to claim 1, wherein the insulator frame is a resin molded product.
ものであることを特徴とする特許請求の範囲第１項記載
の半導体キャリアの製造方法。(3) The method for manufacturing a semiconductor carrier according to claim 1, wherein the insulator frame is made of an ultraviolet curable resin.
る位置に半導体キャリアの入出力端子となる金属ピンが
挿入されたものであることを特徴とする特許請求の範囲
第１項〜第３項のいずれかに記載の半導体キャリアの製
造方法。(4) The insulator frame has metal pins inserted therein to serve as input/output terminals of the semiconductor carrier at positions in contact with the conductor pattern. A method for manufacturing a semiconductor carrier according to any one of the above.
に前記導体パターンと接続され、且つ前記絶縁体フレー
ムの切断によって半導体キャリアの側面上に半導体キャ
リアの入出力端子として露出する導体が充填されること
を特徴とする特許請求の範囲第１項〜第３項のいずれか
に記載の半導体キャリアの製造方法。(5) The insulator frame has an opening, and a conductor is connected to the conductor pattern in the opening and is exposed on the side surface of the semiconductor carrier as an input/output terminal of the semiconductor carrier by cutting the insulator frame. A method for manufacturing a semiconductor carrier according to any one of claims 1 to 3, characterized in that the semiconductor carrier is filled.
を前記導体パターンの形成と同時に行なうことを特徴と
する特許請求の範囲第５項記載の半導体キャリアの製造
方法。(6) The method for manufacturing a semiconductor carrier according to claim 5, characterized in that the opening of the insulator frame is filled with a conductor at the same time as the conductor pattern is formed.
脂からなるものであり、前記開口部を形成する工程は該
樹脂からなる絶縁層を選択的に溶解することにより開口
部を形成することを特徴とする特許請求の範囲第１項記
載の半導体キャリアの製造方法。(7) The insulating layer is made of an ultraviolet curable resin or a thermosetting resin, and the step of forming the opening includes forming the opening by selectively dissolving the insulating layer made of the resin. A method for manufacturing a semiconductor carrier according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60143734A JPS624351A (en) | 1985-06-29 | 1985-06-29 | Manufacture of semiconductor carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60143734A JPS624351A (en) | 1985-06-29 | 1985-06-29 | Manufacture of semiconductor carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS624351A true JPS624351A (en) | 1987-01-10 |
Family
ID=15345766
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60143734A Pending JPS624351A (en) | 1985-06-29 | 1985-06-29 | Manufacture of semiconductor carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS624351A (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4815208A (en) * | 1987-05-22 | 1989-03-28 | Texas Instruments Incorporated | Method of joining substrates for planar electrical interconnections of hybrid circuits |
| JPH0727345U (en) * | 1993-10-30 | 1995-05-23 | 共栄工業株式会社 | Storage |
| JP2003511869A (en) * | 1999-10-08 | 2003-03-25 | プレットナー アンドレアス | Method for producing non-contact chip card and method for producing electric unit comprising chip having contact element |
| WO2002095822A3 (en) * | 2001-05-21 | 2003-07-10 | Intel Corp | Method for packaging a microelectronic device using on-die bond pad expansion |
| WO2002047162A3 (en) * | 2000-12-08 | 2003-08-07 | Intel Corp | Microelectronic package having an integrated heat sink and build-up layers |
| WO2002021595A3 (en) * | 2000-09-08 | 2003-08-14 | Intel Corp | Integrated core microelectronic package |
| WO2002078078A3 (en) * | 2001-03-26 | 2003-12-18 | Intel Corp | Dispensing process for fabrication of microelectronic packages |
| WO2004040661A3 (en) * | 2002-10-30 | 2004-09-10 | Osram Opto Semiconductors Gmbh | Method for producing a light source provided with electroluminescent diodes and comprising a luminescence conversion element |
| US6888240B2 (en) | 2001-04-30 | 2005-05-03 | Intel Corporation | High performance, low cost microelectronic circuit package with interposer |
| US6894399B2 (en) | 2001-04-30 | 2005-05-17 | Intel Corporation | Microelectronic device having signal distribution functionality on an interfacial layer thereof |
| US7078788B2 (en) | 2000-08-16 | 2006-07-18 | Intel Corporation | Microelectronic substrates with integrated devices |
| US7183658B2 (en) | 2001-09-05 | 2007-02-27 | Intel Corporation | Low cost microelectronic circuit package |
| JP2007324429A (en) * | 2006-06-02 | 2007-12-13 | Murata Mfg Co Ltd | Module component and manufacturing method therefor |
| WO2008012481A1 (en) * | 2006-07-28 | 2008-01-31 | Microcomposants De Haute Sécurité Mhs | Process for fabricating an encapsulated integrated circuit and associated encapsulated integrated circuit |
| JP2010091562A (en) * | 2008-10-10 | 2010-04-22 | ３Ｄ−マイクロマック アーゲー | Method and device for producing sample for transmission electron microscopy |
-
1985
- 1985-06-29 JP JP60143734A patent/JPS624351A/en active Pending
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4815208A (en) * | 1987-05-22 | 1989-03-28 | Texas Instruments Incorporated | Method of joining substrates for planar electrical interconnections of hybrid circuits |
| JPH0727345U (en) * | 1993-10-30 | 1995-05-23 | 共栄工業株式会社 | Storage |
| JP2003511869A (en) * | 1999-10-08 | 2003-03-25 | プレットナー アンドレアス | Method for producing non-contact chip card and method for producing electric unit comprising chip having contact element |
| JP4733327B2 (en) * | 1999-10-08 | 2011-07-27 | プレットナー アンドレアス | Non-contact chip card manufacturing method and electric unit manufacturing method including chip having contact element |
| US7078788B2 (en) | 2000-08-16 | 2006-07-18 | Intel Corporation | Microelectronic substrates with integrated devices |
| CN100336220C (en) * | 2000-09-08 | 2007-09-05 | 英特尔公司 | Integrated core microelectronic package |
| EP2760043A1 (en) * | 2000-09-08 | 2014-07-30 | Intel Corporation | Integrated core microelectronic package |
| US6825063B2 (en) | 2000-09-08 | 2004-11-30 | Intel Corporation | Integrated core microelectronic package |
| WO2002021595A3 (en) * | 2000-09-08 | 2003-08-14 | Intel Corp | Integrated core microelectronic package |
| WO2002047162A3 (en) * | 2000-12-08 | 2003-08-07 | Intel Corp | Microelectronic package having an integrated heat sink and build-up layers |
| US6706553B2 (en) | 2001-03-26 | 2004-03-16 | Intel Corporation | Dispensing process for fabrication of microelectronic packages |
| WO2002078078A3 (en) * | 2001-03-26 | 2003-12-18 | Intel Corp | Dispensing process for fabrication of microelectronic packages |
| US6888240B2 (en) | 2001-04-30 | 2005-05-03 | Intel Corporation | High performance, low cost microelectronic circuit package with interposer |
| US6894399B2 (en) | 2001-04-30 | 2005-05-17 | Intel Corporation | Microelectronic device having signal distribution functionality on an interfacial layer thereof |
| WO2002095822A3 (en) * | 2001-05-21 | 2003-07-10 | Intel Corp | Method for packaging a microelectronic device using on-die bond pad expansion |
| US7071024B2 (en) | 2001-05-21 | 2006-07-04 | Intel Corporation | Method for packaging a microelectronic device using on-die bond pad expansion |
| US7183658B2 (en) | 2001-09-05 | 2007-02-27 | Intel Corporation | Low cost microelectronic circuit package |
| US7824941B2 (en) | 2002-10-30 | 2010-11-02 | Osram Opto Semiconductors Gmbh | Method for producing an LED light source comprising a luminescence conversion element |
| WO2004040661A3 (en) * | 2002-10-30 | 2004-09-10 | Osram Opto Semiconductors Gmbh | Method for producing a light source provided with electroluminescent diodes and comprising a luminescence conversion element |
| JP2007324429A (en) * | 2006-06-02 | 2007-12-13 | Murata Mfg Co Ltd | Module component and manufacturing method therefor |
| WO2008012481A1 (en) * | 2006-07-28 | 2008-01-31 | Microcomposants De Haute Sécurité Mhs | Process for fabricating an encapsulated integrated circuit and associated encapsulated integrated circuit |
| FR2904472A1 (en) * | 2006-07-28 | 2008-02-01 | Microcomposants De Haute Secur | METHOD FOR MANUFACTURING ENCAPSULE INTEGRATED CIRCUIT AND INTEGRATED ENCAPSULE INTEGRATED CIRCUIT |
| JP2010091562A (en) * | 2008-10-10 | 2010-04-22 | ３Ｄ−マイクロマック アーゲー | Method and device for producing sample for transmission electron microscopy |
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