CN1202727A - 制造半导体器件的方法 - Google Patents
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Abstract
一种半导体器件的制造方法,首先在衬底上形成隔离多个半导体元件的隔离沟槽,然后在沟槽侧壁上形成热氧化膜,再利用化学汽相淀积在衬底上形成硅氧化膜。最后在高压环境中对整个衬底退火。
Description
本发明涉及制造半导体器件的方法,特别涉及制造在衬底上具有电路元件隔离(isolatior)沟槽的半导体器件的方法。
近来,随着半导体器件的集成化和工作速度的增长,各种各样的技术已显著发展,用于使负载在每个半导体器件上的分立电路元件小型化,并且使用硅氮化膜用于电隔离分立电路元件的LOCOS(硅局部氧化)隔离的应用越来越受限制了。
因而,已经发展了利用沟槽的新的元件隔离技术。例如,日本专利特许公开No.shobo-124840提出了一种形成沟槽、在沟槽中填入绝缘膜并在等于或低于衬底熔点的温度退火的技术。
另外解决方法由Han Sim Lee等人在关于VLSI技术汇编技术文章1996学术讨论会公开的“An optimized Densification of the Filled oxidefor Quarter Micron shallow Trench Isolation”中提出了。下面参照本说明书附图的图4说明此项技术。
如图4所示,在硅衬底101上形成多个预定沟槽104,然后在沟槽104的侧壁上形成热氧化膜102,再利用低压化学汽相淀积(以下也称LP-CVD)法在沟槽104中填满硅氧化膜105,并利用化学和机械抛光(这以下称CMP处理)使其平整。
在Lee等人的文章中,公开了硅氧化膜的致密化,即抗湿腐蚀能通过在水蒸汽气氛中在低温下退火实现。
Lee等人指出,由于沟槽的侧壁被氧化,因此沟槽中产生的应力导致晶体缺陷。
但是,在这个常规技术中,由于通过CVD填满沟槽的硅氧化膜不够致密,因此湿腐蚀速度很快。因而,如图4所示,在通过CMP方法抛平后,在填满沟槽的膜中产生凹痕106,或者在单个沟槽中心产生狭缝(未示出)。
同时,为了改进前述的不便,作为一个例子,需要在等于或高于1200℃高温下通过退火使硅氧化膜致密化。但是如果采用这项技术,则在衬底中产生的大的热应力将引起晶体滑移或错位。
然而在此常规技术中,由于通过退火的致密化是在低温下进行的,因此沟槽内壁被氧化,以致于在沟槽中产生大的应力,由此引起衬底中的缺陷。
因此,本发明的目的是提供制造半导体器件的方法,该方法利用高压环境在低温下充分使沟槽一成型膜致密化,并能减少可能产生的凹痕,同时,还能有效地使分立电路元件彼此隔离。
根据本发明第一方案,上述目的是通过下述制造半导体器件的方法实现的,该方法包括下列步骤:在衬底上形成隔离沟槽,用于隔离多个半导体电路元件;在沟槽成型步骤中所形成的隔离沟槽的侧壁上形成热氧化膜;通过化学汽相淀积(CVD)在衬底上形成硅氧化膜;在高压环境中,对衬底和硅氧化膜同时退火。
最好是,在高压环境中进行CVD硅氧化膜和衬底的退火,以使硅氧化膜在与常压环境相比的较低温度下致密化。
根据本发明的第二方案,上述目的还通过另一种制造半导体器件的方法实现,该方法包括下列步骤:在半导体衬底上形成用于隔离多个半导体电路元件的隔离沟槽;在沟槽成型步骤中所形成的隔离沟槽的侧壁上形成热氧化膜;在衬底上形成硅氮化膜;在衬底上利用化学汽相淀积(CVD)形成硅氧化膜,以及在高压环境中,对所述硅氧化膜和衬底同时退火。
在本发明第二方案中,象本发明第一方案一样,硅氧化膜和衬底的退火是最好是在高压环境中进行,以使硅氧化膜在与常压环境相比的较低温度下致密化。而且最好是,高压环境含有水蒸汽。
根据本发明第三方案,上述目的还通过再一种制造半导体器件的方法实现,该方法包括下列步骤:在衬底形成用于隔离多个半导体电路元件的隔离沟槽;在沟槽成型步骤中所形成的隔离沟槽的侧壁上形成热氧化膜;利用化学汽相淀积(CVD)在衬底上形成硅氧化膜;在高压环境中对整个衬底退火。
在本发明第三方案中,象本发明第二方案一样,硅氧化膜和衬底的退火最好是在高压环境中进行,以使硅氧化膜在与常压环境相比的较低温度下致密化。而且最好是,高压环境含有水蒸汽。
通过下面参照附图的描述,使本发明的上述和其它目的、特点和优点更明显,其中:
图1(a)到1(d)是表示根据本发明第一实施例的半导体器件制造方法的连续工艺步骤截面示意图;
图2(a)到2(d)是表示根据本发明第二实施例的半导体器件制造方法的连续工艺步骤的截面示意图;
图3是表示硅氧化膜的粘度随膜中水含量变化的特性曲线;
图4表示根据常规技术利用沟槽使电路元件彼此隔离的方法。
本发明的原理特别适用于制造半导体器件的方法,下面参照附图描述本发明的两个优选实施例。
在本发明的优选实施例中,利用在衬底上形成和构图的硅氧化和氮化膜作为掩模,在电路元件之间形成沟槽,然后在衬底上利用CVD形成硅氧化膜。
然后,通过在高压环境中退火使硅氧化膜结构致密化,再通过CMP处理整平所得到的硅氧化膜,以使最后得到的硅氧化膜只在沟槽中。
在沟槽侧壁上没有硅氮化膜的情况下,所用的环境最好是水蒸汽、氧气、氮气、氢气和N2O中的任何一种或者它们的组合。
图1(a)到1(d)是表示根据本发明第一实施例的半导体器件的制造方法的连续工艺步骤的截面示意图。
在该制造方法中,经过热氧化膜2在衬底上形成硅氮化膜3。利用光刻和干腐蚀以沟槽的所要求图形构图硅氮化膜3和热氧化膜2。
然后用硅氮化膜3作为掩模,干腐蚀衬底的硅以形成所要求形状的沟槽4。形成这些沟槽4之后,在沟槽4的侧壁上形成保护沟槽4的热氧化膜1A(图1(a))。
然后利用低压CVD在衬底上形成填满沟槽4的硅氧化膜5(图1(b))。
接着,为使其结构紧密,在没有水蒸汽或氧气的高压环境中退火硅氧化膜5。
在这些环境中的退火过程中,硅氧化膜一般是很粘稠的液体,但在温度很低时如室温,它呈现固态。当温度上升时,粘度下降,大约在达到它的熔点时,硅氧化膜能象液体一样完全可流动的。
这种粘度的下降还会发生在相对低温时;例如,在1000℃时粘度近似小于1012泊。此时,如果压力作用于硅氧化膜的表面上,则其结构将重新排列。
然后在常压下,没有从外界施加作用力,因此其结构将不会重新排列,直到温度升高为止。因而,可以通过在高压环境中对硅氧化膜进行退火而使小量硅氧化膜结构紧密。
而且由于高压退火是在没有水蒸汽或氧气的环境中进行的,因此沟槽中的硅不会被氧化,从而由于沟槽侧壁上的硅氧化膜的生长而防止了沟槽内部的应力的增加。
通过在高压环境中退火而进行结构致密化之后,利用CMP处理进行整平。此时,硅氮化膜3作为抗化学和机械抛光的阻挡层,从而保证最佳抛光(1(c))。
这个利用CMP处理的整平是在使用含有氟酸的溶液的清洗步骤中进行的。因此被充分致密化的硅氧化膜5将不会减少其质量并不会产生凹痕。
然后通过湿法或使用等离子体的干法腐蚀去掉用作阻挡层的硅氮化膜3,并也去掉热氧化层2(图1(d))。
接着,也是在形成栅极氧化膜时用含有氟酸的溶液清洗过程中,这个被充分致密化的硅氧化膜5将不会减少其质量,从而变水平或平坦。实施例2
图2(a)到2(f)是表示根据第二实施例半导体器件制造方法的连续步骤的截面图。
在此制造方法中,象图1的第一实施例的方法一样,经过第一热氧化膜12在片状衬底11上形成第一硅氮化膜13,其厚度为100埃。
然后利用光刻或干法腐蚀以所要求的图形构图第一硅氮化膜13和第一热氧化膜12。再用第一硅氮化膜13作为掩模,干法腐蚀衬底11的硅,从而形成所要求形状的沟槽14。形成这些沟槽14之后,在沟槽14内壁上形成保护沟槽14的第二热氧化3膜11A(图2(a))。
然后利用低压CVD在衬底11上形成第二硅氮化膜16,从而覆盖第一硅氮化膜13和第二热氧化膜11A(图2(b))。此时,如果其厚度太厚,则第二硅氮化膜16将被过腐蚀,从而在化学和机械抛光之后产生凹痕,如果太薄,则第二硅氮化膜16在退火过程中将具有较小的抗氧化性。因此,第二硅氮化膜16的厚度最好大约在50到100埃范围内。
如图2(c)所示,用如下方式腐蚀第二硅氮化膜16,即:其剩余未腐蚀部分只覆盖沟槽14的内壁。这将减小作用到第二硅氮化膜16上的应力。接着利用低压CVD在衬底11上形成CVD硅氧化膜17,从而填满沟槽14(图2(d))。
然后,为使其结构致密,在含有水蒸汽的高压环境中对硅氧化膜17退火。
在含水蒸汽环境中退火过程中,大量水渗入硅氧化膜17中。硅氧化膜17的水含量和其粘度的关系如图3所示曲线。从图3的曲线中看出,随着水含量的增加,硅氧化膜17粘度急剧下降。
这样,在含水蒸汽环境中,硅氧化膜17能在低温被软化。通过在被限制到相对低范围的温度下加高压,可以使硅氧化膜17充分致密化。
此时,沟槽14内壁上的第二硅氮化膜16用于防止衬底11的硅氧化,从而由于沟槽内壁硅的氧化,而使沟槽内部应力不会增加。
接着,通过退火致密化之后,利用CMP处理修平或整平硅氧化膜17。此时,在化学和机械抛光(CMP)处理过程中第一硅氮化膜13是作为阻挡层,结果,能够实现最佳抛光(图2(e))。
这种情况下,在化学和机械抛光之后用含有氟酸的溶液清洗过程中,硅氧化膜17由于退火已经被充分致密化了并且其质量没有减少也没有产生凹痕。
再利用湿法或使用等离子体的干法腐蚀去掉用作阻挡层的第一硅氮化膜13,并去掉第一热氧化膜12(图2(f))。
在形成栅极氧化膜的下一工序过程中用含氟酸的溶液清洗时,被充分致密化的硅氧化膜17不会使其质量减少,结果得到平滑表面。
根据本发明的半导体器件,由于在通过CVD形成沟槽中所使用的硅氧化膜在高压环境中通过退火被充分致密化了,因此可以完全消除了凹痕,这凹痕在根据常规技术整平之后会产生在沟槽成型膜的两相反端上。因此可以减少衬底中产生的缺陷,同时,确实可靠地隔离衬底上的分立电路元件。
另外,给出的在沟槽的内壁上形成硅氮化膜,可以更有效地防止沟槽侧壁硅的氧化。因此可以避免任何可能的应力,这应力随着时间的推移有产生在沟槽中的趋势,这样就提高了整个器件的耐用性。
显然,本发明不限于所述的实施例,在不脱离本发明范围和精神的情况下,各种修改和改变都是可以做出的。
Claims (20)
1.一种制造半导体器件的方法,包括下列步骤:
(a)在衬底上形成用于隔离多个半导体电路元件的隔离沟槽;
(b)在所述沟槽成型步骤中所形成的所述隔离沟槽的侧壁上形成热氧化膜;
(c)利用化学汽相淀积(CVD)在衬底上形成硅氧化膜;和
(d)在高压环境中对整个衬底退火。
2.如权利要求1的方法,其中所述退火使硅氧化膜致密化。
3.如权利要求2的方法,其中所述退火之后,通过如下方式利用化学和机械抛光(CMP)整平被致密化的硅氧化膜,该方式为:部分硅氧化膜只残留在沟槽中。
4.如权利要求1的方法,其中所述高压环境不含有水蒸汽。
5.如权利要求4的方法,其中所述高压环境是氮气、氢气、惰性气体中的任何一种或者它们的组合的环境。
6.一种制造半导体器件的方法,包括下列步骤:
(a)在衬底上形成用于隔离多个半导体电路元件的隔离沟槽图形;
(b)在所述隔离沟槽侧壁上形成热氧化膜;
(c)在衬底上形成硅氮化膜;
(d)利用化学汽相淀积(CVD)在衬底上形成硅氧化膜;和
(e)在高压环境中对整个衬底退火。
7.如权利要求6的方法,其中所述退火使硅氧化膜致密化。
8.如权利要求7的方法,其中所述退火之后,以如下方式利用化学和机械抛光(CMP)平整被致密化的硅氧化膜,该方式为:部分硅氧化膜只残留在沟槽部。
9.如权利要求6的方法,其中所述高压环境不含有水蒸汽或氧气。
10.如权利要求5的方法,其中所述高压环境是氮气、氢气、惰性气体中的任何一种或者其组合的环境。
11.如权利要求8的方法,其中在所述平整过程中,硅氮化膜用作为阻挡层。
12.如权利要求11的方法,还包括用含有氟酸的溶液清洗整个衬底的步骤,在该步骤过程中,利用化学和机械抛光(CMP)进行所述平整。
13.如权利要求12的方法,其中在所述清洗之后,作为阻挡层的硅氮化膜与热氧化膜同时利用湿法腐蚀或使用等离子体的干法腐蚀被去掉。
14.一种制造半导体器件的方法,包括下列步骤:
(a)在衬底上形成用于隔离多个半导体电路元件的隔离沟槽图形;
(b)在所述隔离沟槽的侧壁上形成热氧化膜;
(c)在所述沟槽的所述侧壁上所形成的所述热氧化膜上形成硅氮化膜;
(d)利用化学汽相淀积(CVD)在衬底上形成硅氧化膜;和
(e)在高压环境中对整个衬底退火,以使硅氧化膜致密化。
15.如权利要求14的方法,其中利用低压化学汽相淀积(LP-CVD)在衬底上形成所述硅氧化膜。
16.如权利要求14的方法,其中所述硅氮化膜的厚度大约50到100埃。
17.如权利要求15的方法,其中所述形成硅氮化膜的步骤包括腐蚀硅氮化膜,使其未腐蚀部分只覆盖沟槽的侧壁。
18.如权利要求14的方法,其中在所述退火之后,以如下方式利用化学和机械抛光(CMP)整平硅氧化膜,该方式为:部分硅氧化膜只残留在沟槽中。
19.如权利要求15的方法,其中所述高压环境含有水蒸汽。
20.如权利要求18的方法,还包括在所述平整之后用含有氟酸的溶液清洗整个衬底的步骤。
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JP9156256A JPH113936A (ja) | 1997-06-13 | 1997-06-13 | 半導体装置の製造方法 |
JP156256/97 | 1997-06-13 | ||
JP156256/1997 | 1997-06-13 |
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CN1202727A true CN1202727A (zh) | 1998-12-23 |
CN1105400C CN1105400C (zh) | 2003-04-09 |
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US (1) | US6277706B1 (zh) |
JP (1) | JPH113936A (zh) |
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CN1311539C (zh) * | 2003-11-06 | 2007-04-18 | 株式会社瑞萨科技 | 半导体装置的制造方法 |
CN103258777A (zh) * | 2012-02-17 | 2013-08-21 | 格罗方德半导体公司 | 用于制造具有均匀梯状高度的隔离区的半导体装置的方法 |
CN103258777B (zh) * | 2012-02-17 | 2015-08-19 | 格罗方德半导体公司 | 用于制造具有均匀梯状高度的隔离区的半导体装置的方法 |
CN107768308A (zh) * | 2016-08-23 | 2018-03-06 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
CN107768308B (zh) * | 2016-08-23 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
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CN1105400C (zh) | 2003-04-09 |
JPH113936A (ja) | 1999-01-06 |
KR19990006961A (ko) | 1999-01-25 |
US6277706B1 (en) | 2001-08-21 |
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