CN2751439Y - 隔离沟槽的结构 - Google Patents
隔离沟槽的结构 Download PDFInfo
- Publication number
- CN2751439Y CN2751439Y CNU2004200772526U CN200420077252U CN2751439Y CN 2751439 Y CN2751439 Y CN 2751439Y CN U2004200772526 U CNU2004200772526 U CN U2004200772526U CN 200420077252 U CN200420077252 U CN 200420077252U CN 2751439 Y CN2751439 Y CN 2751439Y
- Authority
- CN
- China
- Prior art keywords
- nitrogen
- isolated groove
- groove
- containing liner
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
- 230000002262 irrigation Effects 0.000 claims description 3
- 238000003973 irrigation Methods 0.000 claims description 3
- 238000012856 packing Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract description 12
- 239000003989 dielectric material Substances 0.000 abstract description 8
- 230000000712 assembly Effects 0.000 abstract 1
- 238000000429 assembly Methods 0.000 abstract 1
- 230000002349 favourable effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 56
- 238000012545 processing Methods 0.000 description 24
- 230000003647 oxidation Effects 0.000 description 16
- 238000007254 oxidation reaction Methods 0.000 description 16
- 230000008569 process Effects 0.000 description 16
- 238000005229 chemical vapour deposition Methods 0.000 description 15
- 238000005530 etching Methods 0.000 description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 12
- 150000004767 nitrides Chemical class 0.000 description 12
- 235000012239 silicon dioxide Nutrition 0.000 description 10
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 8
- 230000010415 tropism Effects 0.000 description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 230000006835 compression Effects 0.000 description 6
- 238000007906 compression Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 238000006396 nitration reaction Methods 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 230000002950 deficient Effects 0.000 description 4
- 238000010790 dilution Methods 0.000 description 4
- 239000012895 dilution Substances 0.000 description 4
- 238000005121 nitriding Methods 0.000 description 4
- 239000002002 slurry Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000005012 migration Effects 0.000 description 3
- 238000013508 migration Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910000420 cerium oxide Inorganic materials 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 244000208734 Pisonia aculeata Species 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000002485 combustion reaction Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000002715 modification method Methods 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000001698 pyrogenic effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
一种半导体沟槽隔离结构含有一基底以及一沟槽形成其中。此沟槽中内衬有一含氮(nitrogen-containing)内衬层并以一介电材料填入其中。该含氮内衬层较佳与邻接沟槽的有源区上的组件(例如晶体管)接触。
Description
技术领域
本实用新型是有关于一种半导体组件,且特别有关于一种以含氮内衬层的隔离结构。
背景技术
对于集成电路,尤其是线宽0.25微米以下的集成电路,对作为与有源区隔绝的隔离技术而言,一般皆使用浅沟槽隔离(STI)制程。一现有的浅沟槽隔离结构如图1所示,其中一晶片100含有一基底110,其上有一隔离沟槽112形成于该基底110,该基底110一般是一硅基底。该隔离沟槽112一般是填入一介电材料,例如一氧化硅或其它氧化物,而将相邻的二个有源区116隔离之。
在形成隔离沟槽的过程中,隔离沟槽的侧壁114是可能因后续的制程步骤而发生氧化(oxidation),其结果造成隔离沟槽硅基底的体积膨胀,因而引发相邻的二个有源区116上产生压缩应力(compressive stress)。造成压缩应力的原因为在一局限的空间内产生了体积膨胀。
为解决上述问题,许多于沟槽隔离结构中形成氮化物内衬层的方法已被提出。一般而言,这些方法是利用一氮化物内衬层以阻止或降低沟槽因后续充填介电材料,产生氧化并引发应力。例如美国专利号5447884Fahey et al已描述了一浅隔离沟槽使用一薄氮化物内衬层;美国专利号6461937Kim et al亦描述了形成一氮化硅层于沟槽隔离结构以解除应力;美国专利号6251746Hong et al叙述了于沟槽隔离区形成消除应力的氮化层;以及美国专利号6461937,6251746叙述了沉积氮化层于一典型的升温加热所形成的氧化硅层上。
当氮化物内衬层阻止了后续沟槽侧壁的氧化,其结果是降低了压缩应力。然而,一般形成的氮化物内衬层带有内应力;而且,由于此内应力而导致有源区于脆弱处形成缺陷(defects)甚或裂缝(cracks),该脆弱处例如隔离沟槽顶部的一尖角处(sharp corners)。
此外,形成一氧化物内衬层于氮化物内衬层下面,以降低氮化物内衬层对于有源区的影响的诸多方法亦被提出,但使用了上述的氧化物内衬层却会有引发高热预算(thermal budget)的问题。
因此,业者需要一种隔离沟槽的改良方法,来阻止或降低此隔离沟槽侧壁的氧化效应。
发明内容
本实用新型的目的在于解决隔离沟槽的侧壁因后续的制程步骤而发生氧化(oxidat ion),造成隔离沟槽硅基底的体积膨胀,引发相邻的二个有源区产生压缩应力(compressive stress)的问题。
本实用新型的另一目的在于解决因现有的氮化物内衬层本身带有内应力,而导致有源区易于脆弱处形成缺陷(defects)甚或裂缝(cracks)的问题。
为达上述目的,本实用新型提供一含氮内衬层的隔离沟槽结构,藉由一含氮内衬层及一介电材料填入该沟槽,以使该含氮内衬层以接触或近接(close proximity)的方式于该邻接隔离沟槽的有源区上形成,辅以在隔离沟槽顶部及底部处提供一圆角(round corner)以解决隔离沟槽的尖角处(sharpcorners)由于应力而形成一脆弱点。
附图说明
图1为一现有的隔离沟槽剖面图。
图2a~图2m为用于本实用新型的第一实施例中,形成隔离沟槽制程的一系列剖面图。
图3a~图3g为用于本实用新型的第二实施例中,形成隔离沟槽制程的一系列剖面图。
图4a~图4d为用于本实用新型的第三实施例中,形成隔离沟槽制程的一系列剖面图。
符号说明:
晶片~100、200、300、400;基底~110、210、310、410;隔离沟渠~112;隔离沟渠的侧壁~114;有源区~116;硬掩膜层~212层;掩膜层~312层;氧化层~214;氧化硅层~414;氮化层~216;掩膜图案~218;暴露的基底表面~219;隔离沟渠~220、314、412;含氮内衬层~222、316、416;沟渠填充材料~224、318、418;栅极电极~226、320、420;栅极介电层~228、322、422;源极~230、324、424;漏极~232、326、426;圆角径度~R;内层介电层(ILD)~234、328、428;金属联机~236、330、430。
具体实施方式
为让本实用新型的上述和其它目的、特征、和优点能更明显易懂,下文特举出较佳实施例,并配合所附图式,作详细说明如下:
第一实施例:
首先,请参阅图2a,提供一晶片200具有一基底210,其上形成一硬掩膜212。该基底210可以是一硅或玻璃基底,较佳为硅基底。
该硬掩膜212较佳形成方式,由下而上是由一氧化层214及一氮化层216所组成。该氧化层214较佳为例如一二氧化硅层(SiO2)以例如氧化加热法(thermal oxidation)或化学气相沉积法(CVD)形成,该CVD法是藉由一四乙氧基硅烷(TEOS)及O2当先驱物质(precursor)以进行沉积。而沉积于该氧化层214上的氮化层216较佳为一氮化硅层(Si3N4),该氮化硅层(Si3N4)是以例如化学气相沉积法(CVD),利用硅烷(silane)及氨气当作先驱物质以进行沉积,沉积温度介于约550℃至900℃之间。一图案掩膜218,例如一光阻层掩膜,是以微影的方式形成于该硬掩膜212层上,用以定义欲去除的硬掩膜部分。
接下来,请参阅图2b,以该光阻层图案为掩膜,将未覆盖光阻层的硬掩膜212层部分蚀刻去除,而形成一暴露的基底表面219,以备后续的隔离沟槽制程。该蚀刻制程较佳为例如一非等向性干蚀刻,亦可以是一湿式等向性蚀刻制程。之后再将该图案掩膜218去除。
请参阅图2c,以硬掩膜212层作为一蚀刻掩膜,蚀刻该基底210以形成一沟槽,该沟槽的较佳深度约介于2000至6000埃之间,但其深度不在此限,可依不同的应用而变换深浅度。
之后,请参阅图2d,以一回缩制程(pull back)将一部分硬掩膜层212,包含氮化硅层(Si3N4)以及二氧化硅层(SiO2)蚀刻去除,而形成硬掩膜212层由隔离沟槽220边缘往后缩(retreat)些,该后缩量较佳为介于约10至50nm之间,但其后缩量不在此限,可依不同集成电路的设计而增减。此回缩制程(pullback)可例如为一湿式等向性蚀刻制程,于介于约100℃至180℃之间的温度,30至2000秒之间的蚀刻时间以热磷酸将氮化层216(Si3N4)蚀刻去除;之后再以另一种等向性湿蚀刻法,以例如稀释的氢氟酸于约介于10℃至40℃之间,约2至200秒间的蚀刻时间将氧化层214(SiO2)蚀刻去除。上述该回缩制程(pull back)亦可变换为先以非等向性干蚀刻方式进行,例如藉以一氟化学气体来蚀刻氮化层216,接着以一等向性湿蚀刻法,例如以稀释的氢氟酸于约10℃至40℃之间,约2至200秒间的蚀刻时间将氧化层214(SiO2)蚀刻去除。
后续,请参阅图2e,将该隔离沟槽施行一圆角化制程(corner roundingprocess),较佳为一退火制程,其温度约介于700℃至1000℃之间,以促使沟槽尖角处的硅原子产生迁移(si1icon atom migration)。该退火制程可藉由置于一例如含氢、氮、氦、氖、氩、氙,及其组合气体所组成的族群的环境下,以约1至1000Torr之间的压力施行;该退火环境较佳为一含氢,于约1至1000Torr间的压力以及约700至950℃间的退火温度。一般而言,一高温低压的环境较可促使硅原子产生迁移而形成圆角(round corners)。俟圆角化制程一完成,圆角径度(如图2e示的“R”)较佳为介于约5至50nm之间。
接着,请参阅图2f,于隔离沟槽220及硬掩膜212层上形成一含氮内衬层222(nitrogen-containing liner),较佳的形成方式为例如一熟知的化学气相沉积法(CVD)技艺。该含氮内衬层222例如为一氮化硅层、一氮氧化硅层(SiOxNy)或一氮掺杂(nitrogen-doped)的氧化硅材料,该含氮内衬层的氮原子百分比约为百分之5至百分之60间。
请参阅图2g,该含氮内衬层222的厚度(TN)较佳为介于约0.5至20nm之间,但并不在此限,其厚度可依照制程所需变薄或加厚。该含氮内衬层222较佳为含约-1至+2GPa间的内应力(intrinsic stress),其中负值表示一压缩应力(compressive stress),正值表示一伸张应力(tensile stress)。含氮内衬层222较佳为一具高伸张应力的顺应性沉积氮化层。
依照本实施例,该含氮内衬层222的内应力对于有源区的硅晶格(siliconlattice)的影响是可藉由一含氮内衬层222直接接触该沟槽侧壁而更加扩大。该含氮内衬层222并可避免沟槽侧壁于后续制程步骤的氧化。如上所述,因为该含氮内衬层222为一具高伸张应力的顺应性沉积氮化层,其施加了一显著的反向应力于该有源区的硅晶格上,而压制了因氧化而造成隔离沟槽硅基底的体积膨胀,引发相邻的二个有源区产生压缩应力的问题。此外,利用本实施例,亦避免了脆弱区的发生而不会产生潜在性例如裂隙或差排(dislocation)等缺陷。尖角处即是脆弱区的一例,其中应力会集中在该脆弱区而使该处产生缺陷。因此,较佳的方式为先形成圆角处于该沟槽的上部及底部,然后再形成含氮内衬层222。
后续,请参阅图2h,沉积一沟槽填充材料224填入该沟槽,该沟槽填充材料224为一介电材料,较佳为例如一氧化硅。该沟槽填充材料亦可以是一沟槽填充组合材料,例如以CVD法沉积的氧化硅及以CVD法沉积的多晶硅的组合材料。沉积之后,该沟槽填充材料可以藉由一于约800℃的氢氧燃烧氧化热退火(pyrogenic oxidation anneal)方式或现有的1000℃热退火制程以使该沟槽填充材料更致密化。
之后,施行一平坦化步骤于该沟槽填充材料表面,以使该沟槽填充材料的表面平坦之。该平坦化步骤例如是一现有的化学机械研磨(CMP)制程,该沟槽填充材料可因研磨而停留在含氮内衬层222或氮化硅层216的表面。
接下来,请参阅图2i,以一蚀刻制程将氮化硅层216上的含氮内衬层222及氮化硅层216去除,该蚀刻法例如先以一热磷酸,之后再以一稀释氢氟酸的等向性湿式蚀刻法。
之后,于图2j及图2k所示,再以一蚀刻制程将二氧化硅层214去除,该去除二氧化硅层214的方式较佳为以稀释的氢氟酸等向性湿式蚀刻法。
请参阅图21,于有源区上形成一晶体管。该晶体管包含一栅极电极226,一栅极介电层228,一源极230及一漏极232。当完成该晶体管后,沉积一内层介电层(ILD)234于该晶体管上。该有一平坦表面的内层介电层(ILD)234是包括一氧化硅层,以例如CVD法沉积形成。之后,形成一金属联机236于该平坦的内层介电层(ILD)234上。该金属联机236包含高导电金属例如铝、铜及钨。
之后,通常形成一接触插塞(contact plug)(未显示),是至少与一源极230、漏极232与栅极电极226与金属联机236之间连接。例如可藉由沉积钨金属层并经回蚀(etch back)或化学机械研磨(CMP)制程以形成一钨金属接触插塞。
第二实施例:
首先,请参阅图3a,提供一晶片300具有一基底310,其上形成一掩膜312图案。该基底310例如是一硅或玻璃基底,但较佳为一硅基底。该掩膜312可包括一般的掩膜材料,例如二氧化硅,氮化硅,一氮化硅于一二氧化硅上的迭层、或光阻层,较佳为一光阻层。
接着,请参阅图3b,蚀刻该硅基底以形成一沟槽314,较佳为例如一非等向性干蚀刻方式,较佳的沟槽蚀刻深度约2000至6000埃。
后续,请参阅图3c,将该掩膜312去除以暴露出该有源区。去除该掩膜312可例如先以一热磷酸,之后再以一稀释氢氟酸的等向性湿式蚀刻法施行。
然后,请参阅图3d,如前述第一实施例所述(请参阅图2e),将该隔离沟槽上部及底部的尖角施行一圆角化制程(corner rounding process)。
接着,于图3e中,将一含氮内衬层316及一沟槽填充材料318先后填入该沟槽。该含氮内衬层316例如是一氮化硅层、一氮氧化硅层(Si3N4)或一氮掺杂(nitrogen-doped)的氧化硅材料,该含氮内衬层的氮原子百分比较佳约介于百分之5至百分之60之间。形成方式为例如一化学气相沉积法(CVD)法、热氧化法(thermal oxidation)加上氮化(nitridation)法、或一氮化法。氮化法是藉由将沟槽暴露于一含氮的环境中,例如一含氮电浆(nitrogen-containing plasma)以引进氮原子而进行氮化制程。
请参阅图3f,藉由一高选择比的平坦化制程,一部分的沟槽填充材料318被去除而停留在有源区上的含氮内衬层表面。该高选择比的平坦化制程例如一CMP制程,其藉由一包括氧化铈(CeO2)的研磨浆(slurry)以施行研磨。之后,该有源区上的含氮内衬层藉由一蚀刻制程而去除,该蚀刻制程例如为一含氟酸溶液的等向性湿蚀刻制程,或为一产生电浆蚀刻的非等向性干蚀刻制程。
后续,请参阅图3g,于有源区上形成一晶体管。该晶体管包含一栅极电极320,一栅极介电层322,一源极324及一漏极326。当完成该晶体管后,沉积一内层介电层(ILD)328于该晶体管上。该有一平坦表面的内层介电层(ILD)328是包括一氧化硅层,以例如CVD法沉积形成。之后,形成一金属联机330于该平坦的内层介电层(ILD)328上。该金属联机330包含高导电金属例如铝、铜及钨。
第三实施例:
首先,请参阅图4a,提供一晶片400具有一基底410,其中形成一沟槽412。该形成沟槽的制程请参考如图3a至图3c所示。该基底410例如是一硅或玻璃基底,但较佳为一硅基底。此外,该沟槽412边角(corner)较佳是一圆角,例如图3d所示,或亦可为一非圆角,即使初始的材料即为圆角,最好之后仍进一步圆角化。之后,依序沉积一二氧化硅内衬层414、一含氮内衬层416及一沟渠填充材料418于该沟槽410上。形成一二氧化物内衬层414于氮化物内衬层416下面,其用意在于降低氮化物内衬层的内应力对于有源区的影响。形成该二氧化硅内衬层414可藉由例如一湿式或干式氧化法于约500℃至1000℃间的温度范围。之后,形成一含氮内衬层416于该二氧化硅内衬层414上,可藉由例如一CVD法或氮化法(nitridation)。当施行氮化法时,氮气将会被引入下面的氧化硅层。之后,再沉积沟槽填充材料418。
接着,请参阅图4b,施行一高选择比的平坦化制程以去除一部分的含氮内衬层416及沟槽填充材料418,而停留在该有源区上的含氮内衬层416上。该高选择比的平坦化制程例如一CMP制程,其藉由一包括氧化铈(CeO2)的研磨浆(s1urry)以施行研磨。之后,该有源区上的含氮内衬层藉由一蚀刻制程而去除,该蚀刻制程例如为一含氟酸溶液的等向性湿蚀刻制程,或为一电浆蚀刻的非等向性干蚀刻制程。
后续,请参阅图4c,部分覆盖住有源区上的二氧化硅内衬层414是藉由一蚀刻制程予以去除,例如一稀释的氢氟酸等向性湿式蚀刻法。
然后,请参阅图4d,于有源区上形成一晶体管。该晶体管包含一栅极电极420,一栅极介电层422,一源极424及一漏极426。当完成该晶体管后,沉积一内层介电层(ILD)428于该晶体管上。该有一平坦表面的内层介电层(ILD)428是包括一氧化硅层,以例如CVD法沉积形成。之后,形成一金属联机430于该平坦的内层介电层(ILD)428上。该金属联机430是包含高导电金属例如铝、铜及钨。
虽然本实用新型已以较佳实施例揭露如上,然其并非用以限定本实用新型,任何熟习此技艺者,在不脱离本实用新型的精神和范围内,当可作些许的更动与润饰,因此本实用新型的保护范围当视所附的权利要求范围所界定者为准。
Claims (13)
1.一种隔离沟槽的结构,其特征在于,包括:
一基底其上含有侧壁表面的一沟槽,该沟槽至少含有一上部及一底部的圆角处;
一含氮内衬层与上述沟槽中至少一上部及一底部的圆角处形成接触;以及
一沟槽填充材料于该沟槽内。
2.根据权利要求1所述的隔离沟槽的结构,其特征在于,该圆角的圆弧径度范围是介于5~50nm之间。
3.根据权利要求1所述的隔离沟槽的结构,其特征在于,该沟槽的深度范围为介于2000~6000埃之间。
4.根据权利要求1所述的隔离沟槽的结构,其特征在于,该含氮内衬层的厚度是介于5~200埃之间。
5.根据权利要求1所述的隔离沟槽的结构,其特征在于,该沟槽填充材料包括氧化硅或多晶硅。
6.根据权利要求1所述的隔离沟槽的结构,其特征在于,该含氮内衬层包括氮化硅层或氮氧化硅层。
7.根据权利要求1所述的隔离沟槽的结构,其特征在于,该含氮内衬层的氮含量范围为介于百分之5~60之间。
8.一种隔离沟槽的结构,其特征在于,包括:
一半导体基底其上含有侧壁表面的一沟槽;
一含氮内衬层与上述沟槽侧壁表面形成接触;
一沟渠填充材料于该沟槽内;
一半导体基底中的一有源区,该有源区上至少形成一晶体管组件;
一内层介电层于该半导体基底上;
一金属联机于该内层介电层上;以及
一导电接触插塞连接该金属联机与有源区。
9.根据权利要求8所述的隔离沟槽的结构,其特征在于,该沟槽的深度范围为介于2000~6000埃之间。
10.根据权利要求8所述的隔离沟槽的结构,其特征在于,该含氮内衬层的厚度是介于5~200埃之间。
11.根据权利要求8所述的隔离沟槽的结构,其特征在于,该沟槽填充材料包括氧化硅或多晶硅。
12.根据权利要求8所述的隔离沟槽的结构,其特征在于,该含氮内衬层包括氮化硅层或氮氧化硅层。
13.根据权利要求8所述的隔离沟槽的结构,其特征在于,该含氮内衬层的氮含量范围为介于百分之5~60之间。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US49531603P | 2003-08-15 | 2003-08-15 | |
US60/495,316 | 2003-08-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN2751439Y true CN2751439Y (zh) | 2006-01-11 |
Family
ID=34619289
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNU2004200772526U Expired - Lifetime CN2751439Y (zh) | 2003-08-15 | 2004-08-12 | 隔离沟槽的结构 |
CN200410055181.4A Pending CN1591817A (zh) | 2003-08-15 | 2004-08-12 | 隔离沟槽的结构及其制造方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200410055181.4A Pending CN1591817A (zh) | 2003-08-15 | 2004-08-12 | 隔离沟槽的结构及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US6974755B2 (zh) |
CN (2) | CN2751439Y (zh) |
SG (1) | SG120145A1 (zh) |
TW (1) | TWI239050B (zh) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4659329B2 (ja) * | 2000-06-26 | 2011-03-30 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US6657276B1 (en) * | 2001-12-10 | 2003-12-02 | Advanced Micro Devices, Inc. | Shallow trench isolation (STI) region with high-K liner and method of formation |
US7045836B2 (en) * | 2003-07-31 | 2006-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having a strained region and a method of fabricating same |
US7495267B2 (en) * | 2003-09-08 | 2009-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having a strained region and a method of fabricating same |
KR100545175B1 (ko) * | 2003-12-27 | 2006-01-24 | 동부아남반도체 주식회사 | 플래시 메모리 소자의 트랜치 아이솔레이션 형성방법 |
KR100567752B1 (ko) * | 2003-12-31 | 2006-04-05 | 동부아남반도체 주식회사 | 반도체 소자 형성 방법 |
US7528051B2 (en) * | 2004-05-14 | 2009-05-05 | Applied Materials, Inc. | Method of inducing stresses in the channel region of a transistor |
US20060134881A1 (en) * | 2004-12-17 | 2006-06-22 | Been-Jon Woo | Method of forming trench isolation device capable of reducing corner recess |
US7238564B2 (en) * | 2005-03-10 | 2007-07-03 | Taiwan Semiconductor Manufacturing Company | Method of forming a shallow trench isolation structure |
JP2006278754A (ja) | 2005-03-29 | 2006-10-12 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US20060231908A1 (en) * | 2005-04-13 | 2006-10-19 | Xerox Corporation | Multilayer gate dielectric |
CN100463144C (zh) * | 2005-09-20 | 2009-02-18 | 力晶半导体股份有限公司 | 非挥发性存储器及其制造方法 |
KR100856315B1 (ko) * | 2007-06-22 | 2008-09-03 | 주식회사 동부하이텍 | 반도체 소자의 제조 방법 |
US8183160B2 (en) * | 2007-10-09 | 2012-05-22 | Freescale Semiconductor, Inc. | Method for manufacturing a semiconductor device and semiconductor device obtainable with such a method |
US7892929B2 (en) * | 2008-07-15 | 2011-02-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Shallow trench isolation corner rounding |
CN102468214A (zh) * | 2010-11-19 | 2012-05-23 | 中芯国际集成电路制造(北京)有限公司 | 浅沟槽隔离结构及其形成方法 |
US9318370B2 (en) * | 2011-08-04 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-k dielectric liners in shallow trench isolations |
CN104638012A (zh) * | 2015-01-30 | 2015-05-20 | 矽力杰半导体技术(杭州)有限公司 | 一种沟槽隔离式的半导体结构及其制造方法 |
US9871100B2 (en) * | 2015-07-29 | 2018-01-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Trench structure of semiconductor device having uneven nitrogen distribution liner |
CN108682675A (zh) * | 2017-03-31 | 2018-10-19 | 上海格易电子有限公司 | 一种闪存及其制造方法 |
US10515845B2 (en) | 2017-11-09 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure including isolations and method for manufacturing the same |
TWI755545B (zh) * | 2017-11-09 | 2022-02-21 | 台灣積體電路製造股份有限公司 | 包含隔離結構之半導體結構及其製作方法 |
DE102020119738B4 (de) * | 2020-07-27 | 2022-02-03 | Infineon Technologies Dresden GmbH & Co. KG | Verfahren zur Herstellung eines Halbleiterbauelements und Halbleiterbauelement mit tiefen Gräben |
Family Cites Families (59)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS551103A (en) * | 1978-06-06 | 1980-01-07 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor resistor |
US4631803A (en) | 1985-02-14 | 1986-12-30 | Texas Instruments Incorporated | Method of fabricating defect free trench isolation devices |
JPS63234534A (ja) * | 1987-03-24 | 1988-09-29 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
US4946799A (en) * | 1988-07-08 | 1990-08-07 | Texas Instruments, Incorporated | Process for making high performance silicon-on-insulator transistor with body node to source node connection |
US4952524A (en) * | 1989-05-05 | 1990-08-28 | At&T Bell Laboratories | Semiconductor device manufacture including trench formation |
US5112772A (en) * | 1991-09-27 | 1992-05-12 | Motorola, Inc. | Method of fabricating a trench structure |
US5244827A (en) * | 1991-10-31 | 1993-09-14 | Sgs-Thomson Microelectronics, Inc. | Method for planarized isolation for cmos devices |
US5461250A (en) * | 1992-08-10 | 1995-10-24 | International Business Machines Corporation | SiGe thin film or SOI MOSFET and method for making the same |
US5534713A (en) * | 1994-05-20 | 1996-07-09 | International Business Machines Corporation | Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers |
US5447884A (en) | 1994-06-29 | 1995-09-05 | International Business Machines Corporation | Shallow trench isolation with thin nitride liner |
US5521422A (en) * | 1994-12-02 | 1996-05-28 | International Business Machines Corporation | Corner protected shallow trench isolation device |
US5629544A (en) * | 1995-04-25 | 1997-05-13 | International Business Machines Corporation | Semiconductor diode with silicide films and trench isolation |
US5811347A (en) | 1996-04-29 | 1998-09-22 | Advanced Micro Devices, Inc. | Nitrogenated trench liner for improved shallow trench isolation |
US5830797A (en) * | 1996-06-20 | 1998-11-03 | Cypress Semiconductor Corporation | Interconnect methods and apparatus |
US5763315A (en) | 1997-01-28 | 1998-06-09 | International Business Machines Corporation | Shallow trench isolation with oxide-nitride/oxynitride liner |
US5714777A (en) * | 1997-02-19 | 1998-02-03 | International Business Machines Corporation | Si/SiGe vertical junction field effect transistor |
US5906951A (en) * | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
JP3535527B2 (ja) | 1997-06-24 | 2004-06-07 | マサチューセッツ インスティテュート オブ テクノロジー | 傾斜GeSi層と平坦化を用いたゲルマニウム・オン・シリコンの貫通転位の制御 |
EP0923116A1 (en) * | 1997-12-12 | 1999-06-16 | STMicroelectronics S.r.l. | Process for manufacturing integrated multi-crystal silicon resistors in MOS technology and integrated MOS device comprising multi-crystal silicon resistors |
US6020621A (en) | 1998-01-28 | 2000-02-01 | Texas Instruments - Acer Incorporated | Stress-free shallow trench isolation |
JP3265569B2 (ja) * | 1998-04-15 | 2002-03-11 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US6558998B2 (en) * | 1998-06-15 | 2003-05-06 | Marc Belleville | SOI type integrated circuit with a decoupling capacity and process for embodiment of such a circuit |
US6008095A (en) * | 1998-08-07 | 1999-12-28 | Advanced Micro Devices, Inc. | Process for formation of isolation trenches with high-K gate dielectrics |
US6387739B1 (en) * | 1998-08-07 | 2002-05-14 | International Business Machines Corporation | Method and improved SOI body contact structure for transistors |
US6015993A (en) * | 1998-08-31 | 2000-01-18 | International Business Machines Corporation | Semiconductor diode with depleted polysilicon gate structure and method |
KR100292616B1 (ko) | 1998-10-09 | 2001-07-12 | 윤종용 | 트렌치격리의제조방법 |
KR100322531B1 (ko) | 1999-01-11 | 2002-03-18 | 윤종용 | 파임방지막을 이용하는 반도체소자의 트랜치 소자분리방법 및이를 이용한 반도체소자 |
US6258664B1 (en) * | 1999-02-16 | 2001-07-10 | Micron Technology, Inc. | Methods of forming silicon-comprising materials having roughened outer surfaces, and methods of forming capacitor constructions |
US6358791B1 (en) * | 1999-06-04 | 2002-03-19 | International Business Machines Corporation | Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby |
US6255164B1 (en) * | 1999-08-03 | 2001-07-03 | Worldwide Semiconductor Manufacturing Corp. | EPROM cell structure and a method for forming the EPROM cell structure |
US6323106B1 (en) * | 1999-09-02 | 2001-11-27 | Lsi Logic Corporation | Dual nitrogen implantation techniques for oxynitride formation in semiconductor devices |
US6228727B1 (en) * | 1999-09-27 | 2001-05-08 | Chartered Semiconductor Manufacturing, Ltd. | Method to form shallow trench isolations with rounded corners and reduced trench oxide recess |
JP2001144170A (ja) | 1999-11-11 | 2001-05-25 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US7391087B2 (en) * | 1999-12-30 | 2008-06-24 | Intel Corporation | MOS transistor structure and method of fabrication |
TW503439B (en) * | 2000-01-21 | 2002-09-21 | United Microelectronics Corp | Combination structure of passive element and logic circuit on silicon on insulator wafer |
US6391729B1 (en) | 2000-03-09 | 2002-05-21 | Advanced Micro Devices, Inc. | Shallow trench isolation formation to eliminate poly stringer with controlled step height and corner rounding |
US6475838B1 (en) * | 2000-03-14 | 2002-11-05 | International Business Machines Corporation | Methods for forming decoupling capacitors |
AU2001263211A1 (en) * | 2000-05-26 | 2001-12-11 | Amberwave Systems Corporation | Buried channel strained silicon fet using an ion implanted doped layer |
TW461025B (en) | 2000-06-09 | 2001-10-21 | Nanya Technology Corp | Method for rounding corner of shallow trench isolation |
JP3843708B2 (ja) * | 2000-07-14 | 2006-11-08 | 日本電気株式会社 | 半導体装置およびその製造方法ならびに薄膜コンデンサ |
US6429061B1 (en) | 2000-07-26 | 2002-08-06 | International Business Machines Corporation | Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation |
FR2812764B1 (fr) * | 2000-08-02 | 2003-01-24 | St Microelectronics Sa | Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu |
US6468853B1 (en) | 2000-08-18 | 2002-10-22 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating a shallow trench isolation structure with reduced local oxide recess near corner |
JP2002076287A (ja) * | 2000-08-28 | 2002-03-15 | Nec Kansai Ltd | 半導体装置およびその製造方法 |
US6488853B1 (en) * | 2000-10-04 | 2002-12-03 | Great Circle Technologies, Inc. | Process and apparatus for treating wastewater |
US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
US6417070B1 (en) | 2000-12-13 | 2002-07-09 | International Business Machines Corporation | Method for forming a liner in a trench |
US6265317B1 (en) | 2001-01-09 | 2001-07-24 | Taiwan Semiconductor Manufacturing Company | Top corner rounding for shallow trench isolation |
US6414355B1 (en) * | 2001-01-26 | 2002-07-02 | Advanced Micro Devices, Inc. | Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness |
US6894324B2 (en) * | 2001-02-15 | 2005-05-17 | United Microelectronics Corp. | Silicon-on-insulator diodes and ESD protection circuits |
JP2002313905A (ja) | 2001-04-12 | 2002-10-25 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US6593181B2 (en) * | 2001-04-20 | 2003-07-15 | International Business Machines Corporation | Tailored insulator properties for devices |
US6952040B2 (en) * | 2001-06-29 | 2005-10-04 | Intel Corporation | Transistor structure and method of fabrication |
AU2002331077A1 (en) * | 2001-08-13 | 2003-03-03 | Amberwave Systems Corporation | Dram trench capacitor and method of making the same |
US6621131B2 (en) * | 2001-11-01 | 2003-09-16 | Intel Corporation | Semiconductor transistor having a stressed channel |
US6657276B1 (en) * | 2001-12-10 | 2003-12-02 | Advanced Micro Devices, Inc. | Shallow trench isolation (STI) region with high-K liner and method of formation |
US6461936B1 (en) | 2002-01-04 | 2002-10-08 | Infineon Technologies Ag | Double pullback method of filling an isolation trench |
AU2003238963A1 (en) * | 2002-06-07 | 2003-12-22 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
KR100473731B1 (ko) * | 2002-10-14 | 2005-03-10 | 매그나칩 반도체 유한회사 | 반도체 소자의 제조 방법 |
-
2003
- 2003-10-16 US US10/687,377 patent/US6974755B2/en not_active Expired - Fee Related
-
2004
- 2004-02-19 SG SG200400779A patent/SG120145A1/en unknown
- 2004-02-24 TW TW093104556A patent/TWI239050B/zh not_active IP Right Cessation
- 2004-08-12 CN CNU2004200772526U patent/CN2751439Y/zh not_active Expired - Lifetime
- 2004-08-12 CN CN200410055181.4A patent/CN1591817A/zh active Pending
-
2005
- 2005-06-07 US US11/146,661 patent/US20050224907A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
TW200507098A (en) | 2005-02-16 |
CN1591817A (zh) | 2005-03-09 |
TWI239050B (en) | 2005-09-01 |
SG120145A1 (en) | 2006-03-28 |
US20050224907A1 (en) | 2005-10-13 |
US6974755B2 (en) | 2005-12-13 |
US20050035426A1 (en) | 2005-02-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN2751439Y (zh) | 隔离沟槽的结构 | |
KR100866143B1 (ko) | 반도체 소자의 소자분리막 형성방법 | |
TWI400755B (zh) | 用於由下而上間隙充填的介電質沈積與回蝕處理 | |
US7442620B2 (en) | Methods for forming a trench isolation structure with rounded corners in a silicon substrate | |
CN1779944A (zh) | 浅沟槽隔离结构及形成浅沟槽隔离结构的方法 | |
KR100438772B1 (ko) | 버블 디펙트를 방지할 수 있는 반도체 소자의 제조방법 | |
US6777336B2 (en) | Method of forming a shallow trench isolation structure | |
US20070022941A1 (en) | Method of forming a layer and method of manufacturing a semiconductor device using the same | |
US6784075B2 (en) | Method of forming shallow trench isolation with silicon oxynitride barrier film | |
TW200421525A (en) | Method of forming shallow trench isolation(STI) with chamfered corner | |
US6720235B2 (en) | Method of forming shallow trench isolation in a semiconductor substrate | |
CN1531057A (zh) | 制造浅沟槽隔离结构(sti)的方法 | |
CN1519910A (zh) | 半导体装置的制造方法 | |
CN1278406C (zh) | Ic浅沟渠隔绝的方法 | |
CN1444264A (zh) | 微浅绝缘沟槽结构制备法 | |
KR100492790B1 (ko) | 반도체소자의소자분리절연막형성방법 | |
CN1501470A (zh) | 在半导体基底之中形成浅沟槽隔离物的方法 | |
CN1180467C (zh) | 一种后浅槽隔离工艺方法 | |
US20200219761A1 (en) | Method of forming semiconductor structure | |
CN1392603A (zh) | 改善浅沟槽隔离区的漏电流和崩溃电压的方法 | |
KR100590391B1 (ko) | 플래쉬 메모리 소자의 제조 방법 | |
CN1237602C (zh) | 形成沟槽隔离结构的方法 | |
KR100505427B1 (ko) | 반도체 소자의 소자분리막 형성방법 | |
KR100437541B1 (ko) | 반도체소자의소자분리절연막형성방법 | |
KR100513367B1 (ko) | 반도체 소자의 층간 절연막 형성 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CX01 | Expiry of patent term |
Expiration termination date: 20140812 Granted publication date: 20060111 |