US20030001216A1 - Semiconductor component and method of manufacturing - Google Patents
Semiconductor component and method of manufacturing Download PDFInfo
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- US20030001216A1 US20030001216A1 US09/893,025 US89302501A US2003001216A1 US 20030001216 A1 US20030001216 A1 US 20030001216A1 US 89302501 A US89302501 A US 89302501A US 2003001216 A1 US2003001216 A1 US 2003001216A1
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/772—Field effect transistors
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
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- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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Abstract
A semiconductor component includes a substrate (110) having a surface, a channel region (120, 220) located in the substrate, a non-electrically conductive region (130) substantially located below a substantially planar plane defined by the surface of the substrate, a drift region (140, 240) located in the substrate and between the channel region and the non-electrically conductive region, and an electrically floating region (150, 350, 450, 550) located in the substrate and contiguous with the non-electrically conductive region.
Description
- This invention relates to electronics, in general, and to semiconductor components and methods of manufacturing, in particular.
- Semiconductor components used in automotive applications typically have semiconductor devices with high breakdown voltages of greater than forty volts. These semiconductor devices occasionally use a REduced SURface Field (RESURF) technique, a trench drift structure, or both. Examples of these semiconductor devices are described in U.S. Pat. No. 5,539,238 and in German Patent Application Publication Number DE 195 35 140 A1. When these semiconductor devices are used in high voltage applications, however, these semiconductor devices have a high drain-to-source on-resistance and a low current drive capability.
- Accordingly, a need exists for a semiconductor component and method of manufacturing that has a high breakdown voltage, a low drain-to-source on-resistance, and a high current drive capability.
- The invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures in which:
- FIG. 1 illustrates a cross-sectional view of a portion of a semiconductor component in accordance with an embodiment of the invention;
- FIG. 2 illustrates a cross-sectional view of a portion of a different semiconductor component in accordance with an embodiment of the invention;
- FIG. 3 illustrates a cross-sectional view of a portion of another semiconductor component in accordance with an embodiment of the invention;
- FIG. 4 illustrates a cross-sectional view of a portion of yet another semiconductor component in accordance with an embodiment of the invention;
- FIG. 5 illustrates a cross-sectional view of a portion of still another semiconductor component in accordance with an embodiment of the invention;
- FIG. 6 illustrates a cross-sectional view of a portion of a further semiconductor component in accordance with an embodiment of the invention; and
- FIG. 7 illustrates a flowchart for a method of manufacturing a semiconductor component in accordance with an embodiment of the invention.
- For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques are omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale, and the same reference numerals in different figures denote the same elements.
- Furthermore, the terms first, second, third, fourth, and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is further understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
- Moreover, the terms front, back, top, bottom, over, under, and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.
- A semiconductor component includes a trench drift structure in combination with a double RESURF structure. The semiconductor component can be a single or discrete semiconductor device, or the semiconductor component can be an integrated circuit having a plurality of semiconductor devices. In the preferred embodiment, the semiconductor device is an Ultra-High Voltage (UHV) or power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) having a lateral structure.
- Also in the preferred embodiment, the trench drift structure is located adjacent to a drain region of the semiconductor device. Further in the preferred embodiment, the trench drift structure is integrated in deep submicron technology using Shallow Trench Isolation (STI). Accordingly, the trench in the trench drift structure is preferably manufactured at the same time as the other STI structures in the device.
- The trench in the trench drift structure is at least partially surrounded by an electrically floating ring or region that forms an upper RESURF layer in the double RESURF structure. A portion of the semiconductor substrate in which the device is located forms a lower RESURF layer in the double RESURF structure. A portion of a drift region in the trench drift structure is located between and is deflected by the upper and lower RESURF layers.
- The combination of the trench drift structure and the double RESURF structure provides many advantages. For example, the combined structure increases the breakdown voltage for the semiconductor device. Additionally, the combined structure permits a doubling of the electrical charge within the drift region of the trench drift structure to lower the drift region resistance and the drain-to-source on-resistance of the semiconductor device. The higher electrical charge or higher doping concentration within the drift region also improves the high side operation of the semiconductor device by preventing premature punch-through in the drift region.
- Furthermore, the use of the upper RESURF layer improves the robustness of the semiconductor device by reducing the sensitivity of the semiconductor device to semiconductor substrate surface charges. The upper RESURF layer also prevents depletion effects, which originate from within the semiconductor substrate, from reaching the surface of the semiconductor substrate.
- FIG. 1 illustrates a cross-sectional view of a portion of a
semiconductor component 100. As explained in more detail hereinafter, the portion ofsemiconductor component 100 illustrated in FIG. 1 can represent portions of a single transistor or two transistors depending upon the specific configurations of various doped regions and electrical contacts and electrodes. -
Component 100 comprises asubstrate 110 having asurface 111. Prior to formingcomponent 100 insubstrate 110,surface 111 ofsubstrate 110 preferably forms a substantially planar plane. In the preferred embodiment,substrate 110 is comprised of a semiconductor material. Accordingly,substrate 110 is also referred to as a semiconductor substrate. - As an example,
substrate 110 can comprise asupport substrate 113 supporting an overlyingepitaxial layer 112. In a different embodiment,substrate 110 can consist only of a single semiconductor substrate or a single semiconductor layer. Also as an example,substrate 113 can be comprised of single crystal silicon having a first conductivity type, andlayer 112 can be comprised of epitaxial silicon also having the first conductivity type. In other embodiments,substrate 110 can be comprised of other semiconductor materials such as, for example, germanium, silicon germanium, or gallium arsenide. Furthermore,substrate 113 can have a very high doping level or concentration, andlayer 112 can be grown to have a low doping level or concentration. In the preferred embodiment,substrate 113 can be considered P++, andlayer 112 can be considered P−. -
Semiconductor component 100 also comprises achannel region 120 located insubstrate 110. In particular,channel region 120 is illustrated in FIG. 1 to be located withinlayer 112 ofsubstrate 110. At least a portion ofchannel region 120 is located atsurface 111 ofsubstrate 110. As an example,channel region 120 can have the first doping type, similar tolayer 112 andsubstrate 113. Accordingly, in the preferred embodiment, the MOSFET ofsemiconductor component 100 is an n-channel device.Channel region 120 also has a predetermined doping level or concentration. -
Semiconductor component 100 additionally comprises a non-electricallyconductive region 130. In the preferred embodiment, non-electricallyconductive region 130 is substantially located below the substantially planar plane defined by the original surface, orsurface 111, ofsubstrate 110. Non-electricallyconductive region 130 can be a single continuous region encircling orcircumscribing channel region 120. In a different embodiment, non-electricallyconductive region 130 can be comprised of two separate regions. In the preferred embodiment, non-electricallyconductive region 130 extends only partially intolayer 112 ofsubstrate 110 and does not extend intosubstrate 113 ofsubstrate 110. At least a portion of non-electricallyconductive region 130 is located atsurface 111 ofsubstrate 110. - Non-electrically
conductive region 130 can be either electrically insulative or electrically semi-insulative. As an example, non-electricallyconductive region 130 can be formed by etching a trench intosurface 111 ofsubstrate 110 and filling the trench with a semi-insulative or dielectric material such as silicon dioxide, silicon nitride, gallium arsenide, or a combination of such materials. In a different embodiment, non-electricallyconductive region 130 can be formed by implanting a high dose of oxygen atoms intosurface 111 ofsubstrate 110. In the preferred embodiment, non-electricallyconductive region 130 is not formed using a LOCal Oxidation of Silicon (LOCOS) process. -
Semiconductor component 100 further comprises a dopedregion 140 located insubstrate 110. In particular, dopedregion 140 is illustrated in FIG. 1 to be located withinlayer 112 ofsubstrate 110. At least a portion of dopedregion 140 is located underchannel region 120.Doped region 140 has a second doping type different from the first doping type ofchannel region 120 andsubstrate 110. As an example, dopedregion 140 can have an n-type conductivity. - A
drift region 141 is located within dopedregion 140. Non-electricallyconductive region 130 and driftregion 141 form a trench drift structure. At least a portion ofdrift region 141 is located under non-electricallyconductive region 130. Additionally, at least a portion ofdrift region 141 is located betweenchannel region 120 and non-electricallyconductive region 130, and at least a portion ofdrift region 141 is located atsurface 111 ofsubstrate 110. -
Semiconductor component 100 still further comprises an electrically floatingregion 150 located insubstrate 110. In particular, electrically floatingregion 150 is illustrated in FIG. 1 to be located inlayer 112 ofsubstrate 110. Electrically floatingregion 150 is preferably located only between non-electricallyconductive region 130 and driftregion 141. As illustrated in FIG. 1, electrically floatingregion 150 is contiguous with both non-electricallyconductive region 130 and driftregion 141. At least a portion of electrically floatingregion 150 is located between non-electricallyconductive region 130 andchannel region 120, and at least a portion of electrically floatingregion 150 is located underneath non-electricallyconductive region 130. Electrically floatingregion 150 can be a single region encircling or circumscribingchannel region 120. In a different embodiment, electrically floatingregion 150 can be comprised of two or several separate regions. - At least a portion of electrically floating
region 150 is located atsurface 111 ofsubstrate 110. In particular, a portion of electrically floatingregion 150 atsurface 111 ofsubstrate 110 is located between a portion ofdrift region 141 atsurface 111 ofsubstrate 110 and a portion of non-electricallyconductive region 130 atsurface 111 ofsubstrate 110. Accordingly, a portion of electrically floatingregion 150 is located at a corner or edge of non-electricallyconductive region 130 atsurface 111 ofsubstrate 110. This configuration of electrically floatingregion 150 eliminates or at least reduces any leakage currents emanating from or originating at the corner or edge of non-electricallyconductive region 130. - Electrically floating
region 150 preferably has the first doping type ofchannel region 120 andsubstrate 110. The doping level or concentration within electrically floatingregion 150 can be different from or the same as the doping level or concentration withinchannel region 120. As an example, the doping concentration within electrically floatingregion 150 can be greater than or less than the doping concentration withinchannel region 120. In the preferred embodiment, however, the doping concentration within electrically floatingregion 150 is twenty-five to fifty percent of the doping concentration withinchannel region 120. Also in the preferred embodiment, electrically floatingregion 150 has a maximum doping concentration of approximately 1×1017 atoms per centimeter-cubed. -
Semiconductor component 100 further comprises adrain region 160 insubstrate 110. In particular,drain region 160 is illustrated in FIG. 1 to be located withinlayer 112 ofsubstrate 110. Non-electricallyconductive region 130 is located betweendrain region 160 andchannel region 120. Electrically floatingregion 150 is also located betweendrain region 160 andchannel region 120.Drain region 160 can be a single region encircling or circumscribingchannel region 120, non-electricallyconductive region 130, and electrically floatingregion 150. In a different embodiment, drainregion 160 can be comprised of two separate regions. - As illustrated in FIG. 1, drain
region 160 is located insubstrate 110 adjacent to and contiguous with a side of non-electricallyconductive region 130 facing away fromchannel region 120 and electrically floatingregion 150. At least a portion ofdrain region 160 is located atsurface 111 ofsubstrate 110.Drain region 160 has the second doping type of dopedregion 140. As an example, drainregion 160 can have a high doping concentration and can be considered N+. -
Semiconductor component 100 also comprises asource region 162 insubstrate 110. In particular,source region 162 is illustrated in FIG. 1 to be located withinlayer 112 ofsubstrate 110.Channel region 120 is located betweensource region 162 and driftregion 141.Channel region 120 is also located betweensource region 162 and electrically floatingregion 150.Channel region 120 is further located betweensource region 162 and non-electricallyconductive region 130. At least a portion ofsource region 162 is located atsurface 111 ofsubstrate 110. Similar to drainregion 160,source region 162 has the second doping type, has a high doping concentration, and can be considered N+. -
Semiconductor component 100 further comprises adrain contact 161 and asource contact 163.Drain contact 161 is located oversurface 111 ofsubstrate 110 and drainregion 160.Drain contact 161 is electrically coupled to drainregion 160.Source contact 163 is located oversurface 111 ofsubstrate 110 andsource region 162.Source contact 163 is electrically coupled to sourceregion 162. -
Semiconductor component 100 additionally comprises aportion 170 ofsubstrate 110.Portion 170 is located underchannel region 120, non-electricallyconductive region 130, dopedregion 140, driftregion 141, electrically floatingregion 150,drain region 160, andsource region 162. A portion ofdrift region 141 is located between electrically floatingregion 150 andportion 170.Portion 170 has the first doping type ofchannel region 120 and electrically floatingregion 150. As illustrated in FIG. 1,channel region 120 is electrically isolated fromportion 170 by dopedregion 140. -
Semiconductor component 100 also comprises abody region 171 located insubstrate 110. In particular,body region 171 is illustrated in FIG. 1 to be located withinlayer 112 ofsubstrate 110.Body region 171 is located overportion 170 oflayer 112.Channel region 120 is located withinbody region 171. Accordingly,body region 171 has the first doping type. As illustrated in FIG. 1,body region 171 is electrically isolated fromportion 170 by dopedregion 140. - A
portion 173 ofbody region 171 has a high doping concentration to lower the contact resistance between abody contact 172 ofcomponent 100 andbody region 171.Portion 173 ofbody region 171 can be considered P+.Body contact 172 is located oversurface 111 ofsubstrate 110 to be electrically coupled tobody region 171 throughportion 173.Source region 162 can be a single region encircling or circumscribingportion 173 ofbody region 171. In a different embodiment,source region 162 can be comprised of two separate regions. -
Semiconductor component 100 additionally comprises agate electrode 180 located oversurface 111 ofsubstrate 110.Gate electrode 180 is preferably located over at least a portion ofchannel region 120, non-electricallyconductive region 130, driftregion 141, electrically floatingregion 150,portion 170 oflayer 112, andbody region 171.Gate electrode 180 is also preferably located over at least a portion ofsource region 162, but is preferably not located over any portion ofdrain region 160. In an alternative embodiment,gate electrode 180 can be located over a portion ofdrain region 160. The location ofgate electrode 180 over the edge or corner of electrically floatingregion 130 and also over the portion of electrically floatingregion 150 atsurface 111 ofsubstrate 110 adjacent to the edge or corner of electrically floatingregion 130 both (a) reduces or at least eliminates the leakage current at the edge or corner of non-electricallyconductive region 130 and (b) improves the drain-to-source sustaining voltage of the MOSFET insemiconductor component 100. - In the preferred embodiment,
gate electrode 180 is comprised of a dielectric layer underneath an electrically conductive layer.Gate electrode 180 can also comprise spacers located around a periphery of the electrically conductive layer. In a different embodiment,gate electrode 180 can be devoid of the dielectric material. In this embodiment, the semiconductor device insemiconductor component 100 can be a MEtal-Semiconductor Field Effect Transistor (MESFET). -
Semiconductor component 100 also comprises non-electricallyconductive regions regions channel region 120, non-electricallyconductive region 130, dopedregion 140, driftregion 141, electrically floatingregion 150,drain region 160,source region 162,body region 171, andportion 170 oflayer 112. Non-electricallyconductive regions Drain region 160 is located between non-electricallyconductive regions -
Semiconductor component 100 additionally comprises dopedregions regions channel region 120, non-electricallyconductive regions region 140, driftregion 141, electrically floatingregion 150,drain region 160,source region 162,portion 170 oflayer 112, andbody region 171. - Doped
regions substrate contact 197 tosubstrate 113 and toportion 170 oflayer 112.Doped region 165 has a high doping concentration and is more heavily doped than dopedregion 191.Doped region 165 can be formed simultaneously withportion 173 ofbody region 171 and can be considered P+.Doped regions conductive regions - Doped
regions Doped regions doped regions Doped regions doped regions - Doped
regions contact 196, form an electrically-biased isolation ring around the semiconductor device.Doped region 164 has a high doping concentration and is more heavily doped than dopedregion 195.Doped region 164 can be formed simultaneously withdrain region 160 andsource region 162 and can be considered N+.Doped regions conductive regions - In summary,
semiconductor component 100 in FIG. 1 illustrates a single semiconductor device having a trench drift structure in combination with a double RESURF structure. Non-electricallyconductive region 130 and driftregion 141 form the trench drift structure, and electrically floatingregion 150 andportion 170 oflayer 112 form the double RESURF structure. The use of the trench drift structure and the double RESURF structure enables the use of a higher doping concentration in dopedregion 140 to lower the drift region resistance and the drain-to-source on-resistance. As an example, the drain-to-source on-resistance ofsemiconductor component 100 can be at least as low as 0.5 milliohms-cm2 for an n-channel MOSFET device with a sustaining voltage of 45 volts. - FIG. 2 illustrates a cross-sectional view of a
semiconductor component 200, which is different embodiment ofsemiconductor component 100 in FIG. 1.Semiconductor component 200 in FIG. 2 is a bi-directional device and is symmetric about a line drawn through the center of the channel.Semiconductor component 100 in FIG. 1 is an uni-directional device and is symmetrical about a line drawn through a center ofportion 173 inbody region 171. -
Semiconductor component 200 in FIG. 2 is similar tosemiconductor component 100 in FIG. 1.Semiconductor component 200 in FIG. 2, however, has a different drift region, a different body region, and a different channel region. The drift, body, and channel regions are mainly different only in structure and/or location, but not in function. At least the drift region is also different in doping. In particular,semiconductor component 200 comprises a dopedregion 240 that has an opening in the middle in which abody region 271 is located. Adrift region 241 is located indoped region 240, and achannel region 220 is located inbody region 271.Doped region 240, non-electricallyconductive region 130, and electrically floatingregion 150 can each be a single region encircling or circumscribingbody region 271. In a different embodiment, dopedregion 241, non-electricallyconductive region 130, and electrically floatingregion 150 can each be comprised of two separate regions. Furthermore,semiconductor component 200 comprises aportion 270 oflayer 112, which is electrically coupled tochannel region 220.Doped region 240 does not electrically isolatechannel region 220 fromportion 270 oflayer 112. As a consequence,semiconductor component 200 does not include a separate top side body contact. -
Semiconductor component 200 also comprises adrain region 260, a drain contact 261, asource region 262, and asource contact 263.Drain region 160, drain contact 261,source region 262, andsource contact 263 in FIG. 2 are mainly different fromdrain region 160,drain contact 161,source region 162, andsource contact 163, respectively, in FIG. 1 only in structure and/or location, but not in function. For example, drainregion 260 andsource region 262 in FIG. 2 do not encircle or circumscribe any portions of the semiconductor device. In an embodiment wheredrain region 160 in FIG. 1 has a stripe configuration,drain region 260 in FIG. 2 can be identical to drainregion 160. -
Semiconductor component 200 further comprises agate electrode 280, which is mainly different fromgate electrode 180 in FIG. 1 only in structure and/or location, but not in function. For example, unlikegate electrode 180 in FIG. 1,gate electrode 280 in FIG. 2 does not have a hole in which a source contact or top-side body contact is located.Gate electrode 280 does not overliedrain region 260 orsource region 262, but does overlie at least portions of electrically floatingregion 150, driftregion 241, and non-electricallyconductive region 130. - FIG. 3 illustrates a cross-sectional view of a portion of a
semiconductor component 300, which is also a different embodiment ofsemiconductor component 100 in FIG. 1.Semiconductor component 300 in FIG. 3 has an electrically floatingregion 350, which is mainly different from electrically floatingregion 150 in FIG. 1 only in doping and structure and/or location, but not in function. For example, electrically floatingregion 350 is located mainly only underneath non-electricallyconductive region 130. Electrically floatingregion 350 is contiguous with non-electricallyconductive region 130. - Electrically floating
region 350 is not located atsurface 111 ofsubstrate 110. In particular, electrically floatingregion 350 is not located adjacent to a corner or edge of non-electricallyconductive region 130 atsurface 111 ofsubstrate 110. Accordingly,semiconductor component 300 in FIG. 3 may have a higher magnitude leakage current thansemiconductor component 100 in FIG. 1. - FIG. 4 illustrates a cross-sectional view of a portion of a
semiconductor component 400, which is a different embodiment ofsemiconductor component 100 in FIG. 1.Semiconductor component 400 in FIG. 4 has an electrically floatingregion 450, which is mainly different from electrically floatingregion 150 in FIG. 1 only in doping and structure and/or location, but not in function. For example, electrically floatingregion 450 surrounds non-electricallyconductive region 130 withinsubstrate 110. Electrically floatingregion 450 is located between non-electricallyconductive region 130 and drainregion 160. Electrically floatingregion 450 is also located between non-electricallyconductive region 130 andchannel region 120. - In the preferred embodiment of
semiconductor component 400, electrically floatingregion 450 does not contactdrain region 160. In particular, a portion ofdrift region 141 is located between electrically floatingregion 450 and drainregion 160. Therefore,semiconductor component 400 in FIG. 4 is a larger device thansemiconductor component 100 in FIG. 1, andsemiconductor component 400 in FIG. 4 has a higher drain-to-source on-resistance thansemiconductor component 100 in FIG. 1. In an alternative embodiment ofsemiconductor component 400, electrically floatingregion 450 can contactdrain region 160, but even this embodiment ofsemiconductor component 400 is larger than and has a higher drain-to-source on-resistance thansemiconductor component 100 in FIG. 1. - FIG. 5 illustrates a cross-sectional view of a portion of a
semiconductor component 500, which is a different embodiment ofsemiconductor component 100 in FIG. 1.Semiconductor component 500 in FIG. 5 has an electrically floatingregion 550, which is mainly different from electrically floatingregion 150 in FIG. 1 only in doping and structure and/or location, but not in doping or function. For example, electrically floatingregion 550 is located between non-electricallyconductive region 130 and drainregion 160 and is not located between non-electricallyconductive region 130 andchannel region 120.Semiconductor component 500 in FIG. 5 may have a higher magnitude leakage current thansemiconductor component 100 in FIG. 1. A portion of electrically floatingregion 550 is still located underneath non-electricallyconductive region 130. - FIG. 6 illustrates a cross-sectional view of a portion of a
semiconductor component 600, which is a different embodiment ofsemiconductor component 100 in FIG. 1.Semiconductor component 600 in FIG. 6 has an electrically floating region, which is mainly different from electrically floatingregion 150 in FIG. 1 only in doping and structure and/or location, but not in function. The electrically floating region ofsemiconductor component 500 is comprised of twoseparate portions Portion 650 can be similar to electrically floatingregion 350 ofcomponent 300 in FIG. 3. The addition ofportion 651 incomponent 600 of FIG. 6 eliminates the potential leakage current disadvantage ofcomponent 300 in FIG. 3.Portion 651 incomponent 600 of FIG. 6 can also be added tocomponent 500 of FIG. 5 for the same reason. - FIG. 7 illustrates a
flowchart 700 for a method of manufacturing a semiconductor component. As an example, the semiconductor component can be similar tosemiconductor components step 705 offlowchart 700, a substrate having a surface is provided. As an example, the substrate and the surface ofstep 705 can be similar tosubstrate 110 andsurface 111, respectively, in FIGS. 1, 2, 3, 4, 5, and 6. When the substrate ofstep 705 comprises an epitaxial layer, the dopant in the epitaxial layer forms a portion of the semiconductor device. This portion of the semiconductor device is similar toportion 170 in FIGS. 1, 3, 4, 5, and 6 and is also similar toportion 270 in FIG. 2. - Next, at a
step 710 offlowchart 700 in FIG. 7, a non-electrically conductive region is formed to be substantially located below a substantially planar plane defined by the surface of the substrate. As an example, the non-electrically conductive region ofstep 710 can be similar to non-electricallyconductive region 130 in FIGS. 1, 2, 3, 4, 5, and 6. Step 710 also simultaneously forms non-electricallyconductive regions conductive region 130. - In the preferred embodiment,
step 710 is performed using a STI process. For example, trenches can be etched intosurface 111 ofsubstrate 110, and then a thermal liner oxide layer can be formed along the walls of the trenches. Subsequently, silicon dioxide can be deposited to fill the trenches, and then the silicon dioxide can be densified and planarized. Other techniques can also be used to form the non-electrically conductive regions ofstep 710. The non-electrically conductive region ofstep 710, however, is preferably not formed by using a LOCOS process. - Then, at a
step 715 offlowchart 700 in FIG. 7, a doped region is formed in the substrate. A drift region is located in the doped region. As an example, the doped region ofstep 715 can be similar to dopedregion 140 in FIGS. 1, 3, 4, 5, and 6, and can also be similar to dopedregion 240 in FIG. 2. Step 715 can be performed by, for example, forming an implant mask over the surface of the substrate and implanting a dopant into the substrate. A single implant or a plurality of implants with varying implant doses and energies can be used with the implant mask to form the drift region. - At a
step 720 offlowchart 700, a body region is formed in the substrate. A channel region is located in the body region. The drift region can be located between the channel region and the non-electrically conductive region. As an example, the body region ofstep 720 can be similar tobody region 171 in FIGS. 1, 3, 4, 5, and 6, and can also be similar tobody region 271 in FIG. 2. Step 720 can be performed by, for example, forming an implant mask over the surface of the substrate and implanting a dopant into the substrate. A single implant or a plurality of implants at different implant doses and different implant energies can be performed with the implant mask to form the channel region. - Next, at a step725 of
flowchart 700 in FIG. 7, an electrically floating region is formed in the substrate. The electrically floating region is preferably contiguous with the non-electrically conductive region ofstep 710. As an example, the electrically floating region of step 725 can be similar to electrically floatingregion 150 in FIGS. 1 and 2, electrically floatingregion 350 in FIG. 3, electrically floatingregion 450 in FIG. 4, electrically floatingregion 550 in FIG. 5, orportions - In one embodiment, steps720 and 725 are performed simultaneously with each other. Accordingly, the body region and the electrically floating region can be formed simultaneously with each other. Therefore, a single implant mask can be used to define the body region and the electrically floating region. Similarly, the same implant or a single set of implants can be used to form the body region and the electrically floating region.
- Then, at a
step 730 offlowchart 700 in FIG. 7, additional doped regions are formed in the substrate. Examples of these additional doped regions can includeregions regions regions Regions Regions region 195, which can be formed before or afterregions - At a
step 735 offlowchart 700 in FIG. 7, a gate electrode is formed over the surface of the substrate. As an example, the gate electrode ofstep 735 can be similar togate electrode 180 in FIGS. 1, 3, 4, 5, and 6, and can also be similar togate electrode 280 in FIG. 2. Step 735 can be performed by, for example, forming a gate oxide layer over the surface of the substrate and forming a doped polysilicon layer over the gate oxide layer. Next, this structure can be etched, and then spacers can be formed around the etched structure. - At a
step 740 offlowchart 700 in FIG. 7, source and drain regions are formed in the substrate. The gate electrode can also be implanted simultaneously with the source and drain regions instep 740. As an example, the source region and the drain region instep 740 can be similar tosource region 162 and drainregion 160, respectively, in FIGS. 1, 3, 4, 5, and 6, and can also be similar tosource region 262 and drainregion 260, respectively, in FIG. 2. Step 740 can be performed by, for example, forming an implant mask over the surface of the substrate and the gate electrode and implanting a dopant into the substrate and the gate electrode. In the preferred embodiment, the source and drain regions are simultaneously formed with each other and with the doping of the gate electrode such that a single implant mask and a single implant can be used to simultaneously form the source and drain regions and dope the gate electrode. Also in the preferred embodiment,region 164 in FIGS. 1 and 2 is simultaneously formed with the source and drain regions and with the doping of the gate electrode. A different implant mask and implant process is used to simultaneously formregions - Subsequently, at a
step 745 offlowchart 700 in FIG. 7, additional electrical contacts are formed over the surface of the substrate. As an example, the electrical contacts ofstep 745 can includedrain contact 161 and source contact 163 of FIGS. 1, 3, 4, 5, and 6 can also include drain contact 261 and source contact 263 of FIG. 2, and can further include gate contacts located over the gate electrodes in FIGS. 1, 2, 3, 4, 5, and 6. The electrical contacts ofstep 745 can further includebody contact 172 in FIG. 1 and contact 196 andsubstrate contact 197 in FIGS. 1 and 2. Step 745 can be performed by, for example, performing a self-aligned silicide, or salicide, process. In the preferred embodiment, each of the electrical contacts ofstep 745 are formed simultaneously with each other. - Next, at a
step 750 offlowchart 700 in FIG. 7, an interconnect system is formed over the semiconductor device and also over the surface of the substrate. The interconnect system ofstep 750 can be a single-layered interconnect system or a multi-level interconnect system. Both types of interconnect systems are known in the art. - Next, at a
step 755 offlowchart 700 in FIG. 7, an opposite surface or back surface of the substrate is processed. As an example, the back surface of the substrate can be thinned, and then a metal layer can be formed over the back surface of the substrate. This metal layer can serve as a back metal for mounting the semiconductor component onto, for example, a lead frame. - Although the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made without departing from the spirit or scope of the invention. For instance, the numerous details set forth herein such as, for example, the doping types, the doping concentrations, and the material compositions are provided to facilitate the understanding of the invention and are not provided to limit the scope of the invention. For example, the doping types of the various regions within
substrate 110 in FIG. 1 can be reversed where the first doping type is changed to the second doping type and where the second doping type is changed to the first doping type. Additionally, a single semiconductor component can have both types of semiconductor devices. As an additional example, the modifications tosemiconductor component 100 in FIG. 1 that are described in FIGS. 3, 4, 5, and 6 can also be made tosemiconductor component 200 in FIG. 2. Accordingly, the disclosure of embodiments of the invention is intended to be illustrative of the scope of the invention and is not intended to be limiting. It is intended that the scope of the invention shall be limited only to the extent required by the appended claims.
Claims (35)
1. A semiconductor component comprising:
a substrate having a surface;
a channel region located in the substrate;
a non-electrically conductive region substantially located below a substantially planar plane defined by the surface of the substrate;
a drift region located in the substrate and between the channel region and the non-electrically conductive region; and
an electrically floating region located in the substrate and contiguous with the non-electrically conductive region.
2. The semiconductor component of claim 1 wherein the channel region, the non-electrically conductive region, the drift region, and the electrically floating region are located at the surface of the substrate.
3. The semiconductor component of claim 1 wherein the electrically floating region is located between the drift region and the non-electrically conductive region.
4. The semiconductor component of claim 3 wherein the channel region, the non-electrically conductive region, the drift region, and the electrically floating region are located at the surface of the substrate.
5. The semiconductor component of claim 4 wherein a portion of the electrically floating region at the surface of the substrate is located between a portion of the drift region at the surface of the substrate and a portion of the non-electrically conductive region at the surface of the substrate.
6. The semiconductor component of claim 3 wherein the electrically floating region is located only between the drift region and the non-electrically conductive region.
7. The semiconductor component of claim 1 wherein the electrically floating region is located underneath the non-electrically conductive region.
8. The semiconductor component of claim 7 wherein the electrically floating region is located only underneath the non-electrically conductive region.
9. The semiconductor component of claim 1 further comprising:
a drain region in the substrate;
wherein:
the non-electrically conductive region is located between the drain region and the channel region; and
the electrically floating region is located between the non-electrically conductive region and the drain region.
10. The semiconductor component of claim 9 wherein the channel region, the non-electrically conductive region, the drift region, the electrically floating region, and the drain region are located at the surface of the substrate.
11. The semiconductor component of claim 1 wherein the electrically floating region is located between the non-electrically conductive region and the channel region and is located underneath the non-electrically conductive region.
12. The semiconductor component of claim 11 wherein the channel region, the non-electrically conductive region, the drift region, and the electrically floating region are located at the surface of the substrate.
13. The semiconductor component of claim 1 wherein the channel region is electrically isolated from a portion of the substrate located underneath the channel region.
14. The semiconductor component of claim 1 wherein the channel region is electrically coupled to a portion of the substrate located underneath the channel region.
15. The semiconductor component of claim 1 wherein the non-electrically conductive region comprises a trench in the substrate.
16. The semiconductor component of claim 15 wherein the non-electrically conductive region comprises a dielectric material in the trench.
17. The semiconductor component of claim 1 further comprising:
a gate electrode over the surface of the substrate,
wherein:
the channel region is located at least partially under the gate electrode;
the drift region is located under the gate electrode; and
the electrically floating region is located under the gate electrode.
18. The semiconductor component of claim 17 wherein:
the electrically floating region has a doping type;
the drift region has an other doping type different from the doping type of the electrically floating region and is located under the electrically floating region, and
a portion of the substrate has the doping type of the electrically floating region and is located under the drift region and under the electrically floating region.
19. The semiconductor component of claim 18 wherein the electrically floating region is located under the non-electrically conductive region.
20. The semiconductor component of claim 18 wherein the non-electrically conductive region is located under the gate electrode.
21. The semiconductor component of claim 1 wherein:
the electrically floating region has a doping type;
the drift region has an other doping type different from the doping type of the electrically floating region and is located under the electrically floating region, and
a portion of the substrate has the doping type of the electrically floating region and is located under the drift region and under the electrically floating region.
22. The semiconductor component of claim 1 wherein:
the electrically floating region comprises a first portion and a second portion;
the first portion of the electrically floating region is located underneath the non-electrically conductive region; and
the second portion of the electrically floating region is located at the surface of the substrate between a portion of the drift region at the surface of the substrate and a portion of the non-electrically conductive region at the surface of the substrate.
23. The semiconductor component of claim 22 wherein the first portion of the electrically floating region is separate from the second portion of the electrically floating region.
24. An integrated circuit comprising:
a semiconductor substrate having a surface, a portion of the semiconductor substrate having a first doping type;
a channel region located in the semiconductor substrate, having the first doping type, and located over the portion of the semiconductor substrate;
a non-electrically conductive region substantially located below a substantially planar plane defined by the surface of the semiconductor substrate and located over the portion of the semiconductor substrate;
a drift region located in the substrate, located between the channel region and the non-electrically conductive region, located between the portion of the semiconductor substrate and the non-electrically conductive region, and having a second doping type different from the first doping type; and
an electrically floating region located in the substrate, located between the non-electrically conductive region and the drift region, located between the non-electrically conductive region and the channel region, located over the portion of the semiconductor substrate and the drift region, and having the first doping type.
25. The integrated circuit of claim 24 further comprising a gate electrode located over the portion of the semiconductor substrate, the channel region, the non-electrically conductive region, the drift region, and the electrically floating region.
26. The integrated circuit of claim 25 further comprising:
a drain region located in the semiconductor substrate,
wherein:
the non-electrically conductive region is located between the drain region and the channel region.
27. The integrated circuit of claim 26 wherein the channel region, the non-electrically conductive region, the drift region, and the electrically floating region are located at the surface of the semiconductor substrate.
28. The integrated circuit of claim 27 wherein a portion of the electrically floating region at the surface of the semiconductor substrate is located between a portion of the drift region at the surface of the semiconductor substrate and a portion of the non-electrically conductive region at the surface of the semiconductor substrate.
29. The integrated circuit of claim 28 wherein:
the channel region has a first doping concentration; and
the electrically floating region has a second doping concentration less than the first doping concentration.
30. The integrated circuit of claim 28 wherein the channel region is electrically isolated from the portion of the semiconductor substrate.
31. The integrated circuit of claim 28 wherein the channel region is electrically coupled to the portion of the semiconductor substrate.
32. The integrated circuit of claim 28 wherein the non-electrically conductive region comprises a trench in the substrate and a dielectric material in the trench.
33. The integrated circuit of claim 24 wherein the portion of the semiconductor substrate and the electrically floating region provide a double reduced surface field effect.
34. A method of manufacturing a semiconductor component comprising:
providing a substrate having a surface;
forming a non-electrically conductive region substantially located below a substantially planar plane defined by the surface of the substrate;
forming a drift region in the substrate;
forming a channel region in the substrate, the drift region located between the channel region and the non-electrically conductive region; and
forming an electrically floating region in the substrate and contiguous with the non-electrically conductive region.
35. The method of claim 34 wherein forming the channel region and forming the electrically floating region occur simultaneously with each other.
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AU2002315026A AU2002315026A1 (en) | 2001-06-27 | 2002-05-15 | Field-effect transistor and method of making the same |
TW091111283A TW541696B (en) | 2001-06-27 | 2002-05-28 | Semiconductor component and method of manufacturing |
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- 2002-05-15 WO PCT/US2002/018353 patent/WO2003003452A2/en not_active Application Discontinuation
- 2002-05-28 TW TW091111283A patent/TW541696B/en not_active IP Right Cessation
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- 2003-07-07 US US10/614,553 patent/US7074681B2/en not_active Expired - Lifetime
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Also Published As
Publication number | Publication date |
---|---|
AU2002315026A1 (en) | 2003-03-03 |
US20040097019A1 (en) | 2004-05-20 |
TW541696B (en) | 2003-07-11 |
WO2003003452A3 (en) | 2003-08-21 |
US7074681B2 (en) | 2006-07-11 |
WO2003003452A2 (en) | 2003-01-09 |
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