CN111354798A - Bidirectional asymmetric double-channel switch device and manufacturing method thereof - Google Patents

Bidirectional asymmetric double-channel switch device and manufacturing method thereof Download PDF

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CN111354798A
CN111354798A CN202010181568.3A CN202010181568A CN111354798A CN 111354798 A CN111354798 A CN 111354798A CN 202010181568 A CN202010181568 A CN 202010181568A CN 111354798 A CN111354798 A CN 111354798A
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doped region
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CN111354798B (en
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吴健
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Shanghai Bright Power Semiconductor Co Ltd
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

The invention relates to a bidirectional asymmetric double-channel switch device and a manufacturing method thereof, and belongs to the technical field of semiconductors. In the device, the breakdown voltage between the anode and the cathode (BV1) is determined by the parasitic diode D1 on the anode side, and the breakdown voltage between the cathode and the anode (BV2) is determined by the parasitic diode D2 on the cathode side; breakdown voltage BV1 is independent of and not inherently associated with breakdown voltage BV2, thereby providing bi-directionally adjustable protection. On the other hand, in the manufacturing method of the device, the second side wall layer is formed on the outer side of the first side wall layer, and the source electrode P + doping injection can be realized through self-alignment of the second side wall layer, so that the manufacturing process is simpler and more convenient. Meanwhile, the bidirectional asymmetric double-channel switch device is simple in structure, capable of adopting a general process and quite wide in application range.

Description

Bidirectional asymmetric double-channel switch device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to the technical field of FETs (field effect transistors), and particularly relates to a bidirectional asymmetric double-channel switch device and a manufacturing method thereof.
Background
In the double-channel switch device in the prior art, forward breakdown voltage and reverse breakdown voltage between an anode and a cathode are correlated, so that double-channel bidirectional adjustment cannot be realized. In addition, the process of the dual channel switch device in the prior art is relatively complex, and particularly, the accuracy requirement of the source region for the etching process is higher.
Therefore, how to provide a dual-channel switch device with bidirectional adjustability and simple and convenient manufacturing process becomes a problem to be solved in the field.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned disadvantages of the prior art, and provides a bi-directionally adjustable, simple and convenient to manufacture, bi-directionally asymmetric dual channel switch device and a method for manufacturing the same.
In order to achieve the above object, the bidirectional asymmetric dual channel switching device of the present invention includes:
a substrate;
the first shallow trench isolation is positioned on two sides of the top of the substrate;
the first N-type drift drain region and the second N-type drift drain region are both arranged in a region between the first shallow trench isolations on the top of the substrate;
the P-body region is arranged at the top of the substrate and is positioned between the first N-type drift drain region and the second N-type drift drain region;
a first N + doped region formed in a portion of the top of the first N-type drift drain region as a drain of the first channel and an anode of the switching device;
the P + doping region and the second N + doping regions positioned at two sides of the P + doping region are formed in a part of region at the top of the P-body region and are used as dual-channel source regions;
a third N + doped region formed in a portion of the top of the second N-drift drain region as a drain of the second channel and a cathode of the switching device;
the high-voltage oxide layer covers a part of the first N-type drift drain region;
a gate oxide layer including a first gate oxide layer covering another part of the first N-type drift drain region and a part of the P-body region, and a second gate oxide layer covering another part of the P-body region and the second N-type drift drain region;
the polycrystalline silicon deposition layer comprises a first polycrystalline silicon deposition layer covering the high-voltage oxidation layer and the first grid oxidation layer and a second polycrystalline silicon deposition layer covering the second grid oxidation layer, the first polycrystalline silicon deposition layer is used as a grid of the first channel, and the second polycrystalline silicon deposition layer is used as a grid of the second channel;
and the first side wall layers are arranged on two sides of the first polycrystalline silicon deposition layer and two sides of the second polycrystalline silicon deposition layer.
The lightly doped region is arranged below the first side wall layer and comprises: a first lightly doped region and a second lightly doped region located between the second N + doped region and the P-body region, and a third lightly doped region located between the third N + doped region and the second N-type drift drain region.
The bidirectional asymmetric dual-channel switching device further comprises:
the silicification layer comprises a first silicification layer covering the first N + doping region; a second silicide layer covering the first polysilicon deposition layer; a third silicide layer overlying the source region; a fourth silicide layer covering the second polysilicon deposition layer; and a fifth silicide layer covering the third N + doped region;
and the connecting wires are respectively arranged on the first silicification layer, the third silicification layer and the fifth silicification layer.
In the bidirectional asymmetric two-channel switch device, a shallow groove is arranged at the top of the P-body region, and the P + doped region is formed at the bottom of the shallow groove.
The bidirectional asymmetric dual-channel switch device does not comprise the third silicification layer;
the connecting lines are respectively arranged on the first silicification layer, the fifth silicification layer and the P + doped region.
In the bidirectional asymmetric double-channel switch device, a silicon local oxide layer or a second shallow trench isolation is adopted to replace the high-voltage oxide layer.
The bidirectional asymmetric double-channel switch device does not comprise the high-voltage oxide layer;
the first grid oxide layer covers the first N-type drift drain region and part of the P-body region;
the lightly doped region further comprises: a fourth lightly doped region located between the first N + doped region and the first N-type drift drain region.
The invention also provides a manufacturing method of the bidirectional asymmetric double-channel switch device, which comprises the following steps:
forming first shallow trench isolations on two sides of the top of the substrate;
forming a first N-type drift drain region and a second N-type drift drain region between the first shallow trench isolations on the top of the substrate;
forming a high-voltage oxide layer on a partial region of the first N-type drift drain region;
forming a first gate oxide layer on another partial region of the first N-type drift drain region, and forming a second gate oxide layer on a partial region of the second N-type drift drain region;
forming a first polysilicon deposition layer on the high-voltage oxidation layer and the first grid oxidation layer to be used as a grid of a first channel; forming a second polysilicon deposition layer on the second gate oxide layer to serve as a gate of a second channel;
forming a P-body region between the first N-type drift drain region and the second N-type drift drain region and a lightly doped region self-aligned to the first polysilicon deposition layer and the second polysilicon deposition layer on top of the substrate, comprising: a first lightly doped region in the top of the P-body region on one side of the first polysilicon deposition layer, a second lightly doped region in the top of the P-body region on one side of the second polysilicon deposition layer, and a third lightly doped region in the top of the second N-type drift drain region on the other side of the second polysilicon deposition layer;
arranging first side wall layers on two sides of the first polycrystalline silicon deposition layer and two sides of the second polycrystalline silicon deposition layer;
forming an N + doped region comprising: a first N + doped region formed in a portion of the top of the first N-type drift drain region, serving as a drain of the first channel and an anode of the switching device; the second N + doping area is formed in a part of area at the top of the P-body area and is used as a double-channel source area; and a third N + doped region formed in a portion of the top of the second N-type drift drain region, as a drain for the second channel and a cathode for the switching device;
forming a second side wall layer on the outer side of the first side wall layer;
forming a P + doped region in the middle of the second N + doped region;
and removing the second side wall layer.
The manufacturing method of the bidirectional asymmetric double-channel switch device further comprises the following steps:
forming a silicide layer comprising a first silicide layer overlying the first N + doped region; a second silicide layer covering the first polysilicon deposition layer; a third silicide layer overlying the source region; a fourth silicide layer covering the second polysilicon deposition layer; and a fifth silicide layer covering the third N + doped region;
and connecting wires are respectively arranged on the first silicification layer, the third silicification layer and the fifth silicification layer.
In the manufacturing method of the bidirectional asymmetric two-channel switch device, the P + doped region is formed in the middle of the second N + doped region, and the method specifically comprises the following steps:
and a shallow groove with the bottom reaching the P-body region is formed in the middle of the second N + doped region, and a P + doped region is formed at the bottom of the shallow groove.
In the manufacturing method of the bidirectional asymmetric dual-channel switch device, the silicified layer does not comprise the third silicified layer; the connecting lines are respectively arranged on the first silicification layer, the fifth silicification layer and the P + doped region.
In the manufacturing method of the bidirectional asymmetric two-channel switch device,
the step of forming the high-voltage oxide layer on the partial region of the first N-type drift drain region is replaced by:
forming a silicon local oxide layer on top of the partial region of the first N-type drift drain region, or
Forming a second shallow trench isolation on the top of the partial region of the first N-type drift drain region;
and is
And forming a first polysilicon deposition layer on the high-voltage oxide layer and the first grid oxide layer, and replacing the first polysilicon deposition layer with:
forming a first polysilicon deposition layer on the silicon local oxide layer and the first gate oxide layer, or
And forming a first polysilicon deposition layer on the second shallow trench isolation and the first grid oxide layer.
In the manufacturing method of the bidirectional asymmetric two-channel switch device,
the step of forming the high-voltage oxide layer on the partial region of the first N-type drift drain region is omitted,
the step of forming a lightly doped region under the first sidewall layer further comprises
The lightly doped region further comprises: and forming a fourth lightly doped region between the first N + doped region and the first N-type drift drain region.
By adopting the bidirectional asymmetric double-channel switching device and the manufacturing method thereof, the breakdown voltage (BV1) between the anode and the cathode depends on the parasitic diode D1 on the anode side, and the breakdown voltage (BV2) between the cathode and the anode depends on the parasitic diode D2 on the cathode side; breakdown voltage BV1 is independent of and not inherently associated with breakdown voltage BV2, thereby providing bi-directionally adjustable protection. On the other hand, in the manufacturing method of the device, the second side wall layer is formed on the outer side of the first side wall layer, and the source electrode P + doping injection can be realized through self-alignment of the second side wall layer, so that the manufacturing process is simpler and more convenient. Meanwhile, the bidirectional asymmetric double-channel switch device is simple in structure, capable of adopting a general process and quite wide in application range.
Drawings
Fig. 1 is a schematic structural diagram of a bidirectional asymmetric dual-channel switching device according to the present invention.
Fig. 2A is a schematic structural diagram of a first alternative of the bidirectional asymmetric dual channel switching device of the present invention.
Fig. 2B is a schematic diagram of a second alternative of the bidirectional asymmetric dual channel switching device of the present invention.
Fig. 3 is a schematic diagram of a first step of a method for manufacturing a bidirectional asymmetric dual-channel switching device according to the present invention.
Fig. 4 is a schematic diagram of a second step of the manufacturing method of the bidirectional asymmetric dual-channel switching device of the present invention.
Fig. 5 is a schematic diagram of a third step of the manufacturing method of the bidirectional asymmetric dual-channel switching device of the present invention.
Fig. 6 is a schematic diagram of a fourth step of the manufacturing method of the bidirectional asymmetric dual-channel switching device according to the present invention.
Fig. 7 is a five-step schematic diagram of a manufacturing method of the bidirectional asymmetric dual-channel switching device according to the present invention.
Fig. 8 is a schematic diagram of a third alternative of the bidirectional asymmetric dual channel switching device of the present invention.
Fig. 9 is a schematic diagram of a fourth alternative of the bidirectional asymmetric dual channel switching device of the present invention.
Fig. 10 is a schematic diagram of a fifth alternative of the bidirectional asymmetric dual channel switching device of the present invention.
Detailed Description
In order to clearly understand the technical contents of the present invention, the following examples are given in detail.
In the drawings, "N" or "P" is a doping type, and "-" or "+" immediately after the doping type indicates a relative doping concentration. For example, "N +" means a doping concentration higher than that of the "N" doped region, and correspondingly "N-" means a doping concentration lower than that of the "N" doped region. Doped regions having the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "N +" doped regions may have the same or different doping concentrations.
Fig. 1 is a schematic structural diagram of a bidirectional asymmetric dual-channel switching device according to the present invention.
In one embodiment, the bidirectional asymmetric dual channel switching device 100 includes:
a P-substrate (P-SUB) 101;
first Shallow Trench Isolations (STIs) 110 on both sides of the top of the substrate 101;
a first N-type drift drain (NDD) region 102 and a second N-type drift drain region 104, both disposed in a region between the first shallow trench isolations 110 on top of the substrate 101;
a P-Body (P-Body)103 disposed on top of the substrate 101 and between the first N-type drift drain region 102 and the second N-type drift drain region 104;
a first N + doped region 105 formed in a portion of the top of the first N-drift drain region 102 as a drain of the first channel and an anode of the switching device 100;
a P + doped region 107 and second N + doped regions 106 and 108 located at both sides of the P + doped region are formed in a part of the top region of the P-body 103 as a dual-channel source region;
a third N + doped region 109 formed in a portion of the top of the second N-drift drain region 104 as a drain of the second channel and a cathode of the switching device 100;
a high voltage Oxide (HV-Oxide) layer 115 covering a portion of the first N-type drift drain region 102;
a gate oxide layer including a first gate oxide layer 117a covering another part of the first N-type drift drain region 102 and a part of the P-body region 103, and a second gate oxide layer 117b covering another part of the P-body region 103 and the second N-type drift drain region 104;
a polysilicon deposition layer including a first polysilicon deposition layer 111 covering the high voltage oxide layer 115 and the first gate oxide layer 117a, and a second polysilicon deposition layer 112 covering the second gate oxide layer 117b, wherein the first polysilicon deposition layer 111 serves as a gate of the first channel, and the second polysilicon deposition layer 112 serves as a gate of the second channel;
the first sidewall layers 116a, 116b, 116c, 116d are disposed on two sides of the first polysilicon deposition layer 111 and two sides of the second polysilicon deposition layer 112.
The lightly doped region is disposed below the first sidewall layers 116b, 116c, and 116d, and includes: a first lightly doped region 118a and a second lightly doped region 118b between the second N + doped regions 106, 108 and the P-body region 103, and a third lightly doped region 118c between the third N + doped region 109 and the second N-type drift drain region 104.
In addition, the bidirectional asymmetric dual-channel switching device 100 further includes:
a silicide layer including a first silicide layer 113a overlying the first N + doped region 105; a second silicide layer 113b overlying the first polysilicon deposition layer 111; a third silicide layer 113c overlying the source region; a fourth silicide layer 113d overlying the second polysilicon deposition layer 112; and a fifth silicide layer 113e overlying the third N + doped region 109;
the connecting lines 114a, 114b, 114c are respectively disposed on the first silicide layer 113a, the third silicide layer 113c and the fifth silicide layer 113 e.
As shown in fig. 1, the anode-to-cathode breakdown voltage (BV1) of the device 100 is determined by the anode-side parasitic diode D1, and the cathode-to-anode breakdown voltage (BV2) is determined by the cathode-side parasitic diode D2; breakdown voltage BV1 is independent of and not inherently associated with breakdown voltage BV2, thereby providing bi-directionally adjustable protection.
In an alternative embodiment, as shown in fig. 2A, the device 200A differs from the device 100 in that the top of the P-body region 203 is provided with a shallow trench, and the P + doped region 207 is formed at the bottom of the shallow trench. The source region does not include the third silicide layer, and the source region interconnect 220 is disposed over the P + doped region 207.
As another alternative, as shown in fig. 2B, the device 200B is the same as the device 200A, and the top of the P-body region 203 is also provided with a shallow trench, and the P + doped region 207 is formed at the bottom of the shallow trench. The difference is that the source region is covered with a third silicide layer 213c, and the connection line 214b of the source region is disposed on the third silicide layer 213c, which is the same as the device 100. The connection performance of the source region is improved by providing the third silicide layer 213 c.
Hereinafter, a method for manufacturing a bidirectional asymmetric dual channel switching device according to the present invention will be described with reference to fig. 3 to 7, taking the device 200B as an example. The method comprises the following steps:
first, as shown in fig. 3, first shallow trench isolations 210 are formed on both sides of the top of the substrate 201;
forming a first N-type drift drain region 202 and a second N-type drift drain region 204 between the first shallow trench isolations 210 on top of the substrate 201;
forming a high-voltage oxide layer 217 on a partial region of the first N-type drift drain region 202;
forming a first gate oxide layer 215a over another portion of the first N-drift drain region 202 and a second gate oxide layer 215b over a portion of the second N-drift drain region 204;
forming a first polysilicon deposition layer 211 over the high voltage oxide layer 217 and the first gate oxide layer 215a as a gate of a first channel; forming a second polysilicon deposition layer 212 over the second gate oxide layer 215b as a gate of a second channel;
forming a P-body region 203 between the first N-type drift drain region 202 and the second N-type drift drain region 204 and a lightly doped region self-aligned to the first poly deposition layer 211 and the second poly deposition layer 212 on top of the substrate 201, including: a first lightly doped region 218a in the top of the P-body region 203 on one side of the first poly deposition layer 211, a second lightly doped region 218b in the top of the P-body region 203 on one side of the second poly deposition layer 212, and a third lightly doped region 218c in the top of the second N-drift drain region 204 on the other side of the second poly deposition layer 212;
first sidewall layers 216a and 216b are disposed on both sides of the first polysilicon deposition layer 211, and first sidewall layers 216c and 216d are disposed on both sides of the second polysilicon deposition layer 212;
a first N + doped region 205 formed in a portion of the top of the first N-type drift drain region 202, serving as a drain of the first channel and an anode of the switching device; forming a second N + doped region 206 in a portion of the top of the P-body region 203 as a dual-channel source region; and a third N + doped region 209 is formed in a portion of the top of the second N-drift drain region 204 to serve as the drain for the second channel and the cathode for the switching device, forming device 600.
Then, as shown in fig. 4, second sidewall layers 701a, 701b, 701c, 701d are formed outside the first sidewall layers 216a, 216b, 216c, 216d, so as to form the device 700.
Subsequently, as shown in fig. 5, masks 201a and 201b are set, and etching and implantation are performed by using a self-aligned technique, so as to form a P + doped region 207 located at the bottom of the shallow trench in the middle of the second N + doped region 206, thereby forming the device 800.
Thereafter, as shown in fig. 6, the second sidewall layer is removed to form the device 900.
Finally, as shown in fig. 7, a back-end process is used to form a silicide layer, including a first silicide layer 213a covering the first N + doped region 205; a second silicide layer 213b overlying the first polysilicon deposition layer 211; a third silicide layer 213c overlying the source region; a fourth silicide layer 213d overlying the second polysilicon deposition layer 212; and a fifth silicide layer 213e overlying the third N + doped region 209 to form a device 1000; and connection lines 214a, 214B, 214c as shown in fig. 2B may be disposed on the first, third and fifth silicide layers 213a, 213c and 213e, respectively, to finally form the device 200B.
Correspondingly, in the method for manufacturing the device 200A, according to the above method, after the second sidewall layer is removed to form the device 900 as shown in fig. 6, only the first silicide layer 213a, the second silicide layer 213b, the fourth silicide layer 213d, and the fifth silicide layer 213e are formed, and the third silicide layer 213c is not formed. And the source region connection line 220 is disposed above the P + doped region 207.
In the manufacturing method of the device 100, unlike the above method, the P + doped region 107 located between the second N + doped regions 106 and 108 is directly implanted without forming a shallow trench in the middle of the second N + doped region by etching. The subsequent process steps are similar to those of device 200B.
Other structures may be substituted for the high voltage oxide layer 115 or 217 to accommodate various process platforms.
In a first alternative, the high voltage oxide layer is replaced by a Local Oxidation of Silicon (LOCOS) 301, as shown in device 300 in fig. 8. The remainder of the device 300 is the same as the device 200B shown in fig. 2B.
Accordingly, in the device manufacturing method of this alternative, the step of forming the high-voltage oxide layer is replaced by forming the local silicon oxide layer 301 located above the partial region of the first N-type drift drain region 202 by using local silicon oxidation.
In a second alternative, the high voltage oxide layer is replaced by a first gate oxide layer 405 as shown in device 400 in fig. 9. The gate oxide layer 405 includes the first gate oxide layer 215a that would otherwise overlie another portion of the first N-drift drain region 202 and a portion of the P-body region 203 in the device 200B. And a first polysilicon deposition layer 401 overlies the first gate oxide layer 405.
Accordingly, in the device manufacturing method of this alternative, the step of forming the high-voltage oxide layer is omitted. Instead, a first gate oxide layer 405 is formed overlying a portion of the P-body region 203 and covering a majority of the first N-type drift drain region 202 as shown in fig. 9.
Meanwhile, in this alternative, the lightly doped region further includes a fourth lightly doped region 406 located between the first N + doped region 205 and the first N-type drift drain region 202.
In a third alternative, the high voltage oxide layer is replaced by a second shallow trench isolation 501 as shown in device 500 in fig. 10. In addition, similar to the second alternative, a first gate oxide layer 405 is formed overlying the second shallow trench isolation 501, and similarly, a first polysilicon deposition layer 401 is formed overlying the first gate oxide layer 405.
Accordingly, in the device manufacturing method of this alternative, the step of forming the high voltage oxide layer is replaced by forming the second shallow trench isolation 501 located in a part of the top region of the first N-type drift drain region 202.
In the three alternatives described above, the source region has the same structure as the device 200B in fig. 2B, and it is apparent that the source regions of these alternatives may also have the structure shown in the device in fig. 1.
The bidirectional asymmetric two-channel switching device formed by the above embodiment and the corresponding alternative has the advantages that as shown in fig. 1, the breakdown voltage (BV1) between the anode and the cathode is determined by the parasitic diode D1 on the anode side, and the breakdown voltage (BV2) from the cathode to the anode is determined by the parasitic diode D2 on the cathode side; breakdown voltage BV1 is independent of and not inherently associated with breakdown voltage BV2, thereby providing bi-directionally adjustable protection. On the other hand, in the manufacturing method of the device, the second side wall layer is formed on the outer side of the first side wall layer, and the source electrode P + doping injection can be realized through self-alignment of the second side wall layer, so that the manufacturing process is simpler and more convenient. Meanwhile, the bidirectional asymmetric double-channel switch device is simple in structure, capable of adopting a general process and quite wide in application range.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (12)

1. A bidirectional asymmetric dual channel switching device, comprising:
a substrate;
the first shallow trench isolation is positioned on two sides of the top of the substrate;
the first N-type drift drain region and the second N-type drift drain region are both arranged in a region between the first shallow trench isolations on the top of the substrate;
the P-body region is arranged at the top of the substrate and is positioned between the first N-type drift drain region and the second N-type drift drain region;
a first N + doped region formed in a portion of the top of the first N-type drift drain region as a drain of the first channel and an anode of the switching device;
the P + doping region and the second N + doping regions positioned at two sides of the P + doping region are formed in a part of region at the top of the P-body region and are used as dual-channel source regions;
a third N + doped region formed in a portion of the top of the second N-drift drain region as a drain of the second channel and a cathode of the switching device;
the high-voltage oxide layer covers a part of the first N-type drift drain region;
a gate oxide layer including a first gate oxide layer covering another part of the first N-type drift drain region and a part of the P-body region, and a second gate oxide layer covering another part of the P-body region and the second N-type drift drain region;
the polycrystalline silicon deposition layer comprises a first polycrystalline silicon deposition layer covering the high-voltage oxidation layer and the first grid oxidation layer and a second polycrystalline silicon deposition layer covering the second grid oxidation layer, the first polycrystalline silicon deposition layer is used as a grid of the first channel, and the second polycrystalline silicon deposition layer is used as a grid of the second channel;
and the first side wall layers are arranged on two sides of the first polycrystalline silicon deposition layer and two sides of the second polycrystalline silicon deposition layer.
The lightly doped region is arranged below the first side wall layer and comprises: a first lightly doped region and a second lightly doped region located between the second N + doped region and the P-body region, and a third lightly doped region located between the third N + doped region and the second N-type drift drain region.
2. The bidirectional asymmetric dual channel switching device of claim 1, further comprising:
the silicification layer comprises a first silicification layer covering the first N + doping region; a second silicide layer covering the first polysilicon deposition layer; a third silicide layer overlying the source region; a fourth silicide layer covering the second polysilicon deposition layer; and a fifth silicide layer covering the third N + doped region;
and the connecting wires are respectively arranged on the first silicification layer, the third silicification layer and the fifth silicification layer.
3. The bi-directional asymmetric dual channel switching device of claim 2,
the top of the P-body region is provided with a shallow groove, and the P + doped region is formed at the bottom of the shallow groove.
4. The bidirectional asymmetric dual channel switching device of claim 3,
excluding said third silicide layer;
the connecting lines are respectively arranged on the first silicification layer, the fifth silicification layer and the P + doped region.
5. The bidirectional asymmetric dual channel switching device of any one of claims 1 to 4,
and replacing the high-voltage oxide layer with a silicon local oxide layer or a second shallow trench isolation.
6. The bidirectional asymmetric dual channel switching device of any one of claims 1 to 4,
excluding the high voltage oxide layer;
the first grid oxide layer covers the first N-type drift drain region and part of the P-body region;
the lightly doped region further comprises: a fourth lightly doped region located between the first N + doped region and the first N-type drift drain region.
7. A method of fabricating a bidirectional asymmetric dual channel switching device, comprising:
forming first shallow trench isolations on two sides of the top of the substrate;
forming a first N-type drift drain region and a second N-type drift drain region between the first shallow trench isolations on the top of the substrate;
forming a high-voltage oxide layer on a partial region of the first N-type drift drain region;
forming a first gate oxide layer on another partial region of the first N-type drift drain region, and forming a second gate oxide layer on a partial region of the second N-type drift drain region;
forming a first polysilicon deposition layer on the high-voltage oxidation layer and the first grid oxidation layer to be used as a grid of a first channel; forming a second polysilicon deposition layer on the second gate oxide layer to serve as a gate of a second channel;
forming a P-body region between the first N-type drift drain region and the second N-type drift drain region and a lightly doped region self-aligned to the first polysilicon deposition layer and the second polysilicon deposition layer on top of the substrate, comprising: a first lightly doped region in the top of the P-body region on one side of the first polysilicon deposition layer, a second lightly doped region in the top of the P-body region on one side of the second polysilicon deposition layer, and a third lightly doped region in the top of the second N-type drift drain region on the other side of the second polysilicon deposition layer;
arranging first side wall layers on two sides of the first polycrystalline silicon deposition layer and two sides of the second polycrystalline silicon deposition layer;
forming an N + doped region comprising: a first N + doped region formed in a portion of the top of the first N-type drift drain region, serving as a drain of the first channel and an anode of the switching device; the second N + doping area is formed in a part of area at the top of the P-body area and is used as a double-channel source area; and a third N + doped region formed in a portion of the top of the second N-type drift drain region, as a drain for the second channel and a cathode for the switching device;
forming a second side wall layer on the outer side of the first side wall layer;
forming a P + doped region in the middle of the second N + doped region;
and removing the second side wall layer.
8. The method of manufacturing a bidirectional asymmetric dual channel switching device as recited in claim 7, further comprising:
forming a silicide layer comprising a first silicide layer overlying the first N + doped region; a second silicide layer covering the first polysilicon deposition layer; a third silicide layer overlying the source region; a fourth silicide layer covering the second polysilicon deposition layer; and a fifth silicide layer covering the third N + doped region;
and connecting wires are respectively arranged on the first silicification layer, the third silicification layer and the fifth silicification layer.
9. The method of manufacturing a bidirectional asymmetric dual channel switching device as recited in claim 8,
the P + doped region is formed in the middle of the second N + doped region, and specifically includes:
and a shallow groove with the bottom reaching the P-body region is formed in the middle of the second N + doped region, and a P + doped region is formed at the bottom of the shallow groove.
10. The method of manufacturing a bidirectional asymmetric dual channel switching device as recited in claim 9,
said silicide layer does not include said third silicide layer; the connecting lines are respectively arranged on the first silicification layer, the fifth silicification layer and the P + doped region.
11. The method of manufacturing a bidirectional asymmetric dual channel switching device as recited in any one of claims 7 to 10,
the step of forming the high-voltage oxide layer on the partial region of the first N-type drift drain region is replaced by:
forming a silicon local oxide layer on top of the partial region of the first N-type drift drain region, or
Forming a second shallow trench isolation on the top of the partial region of the first N-type drift drain region;
and is
And forming a first polysilicon deposition layer on the high-voltage oxide layer and the first grid oxide layer, and replacing the first polysilicon deposition layer with:
forming a first polysilicon deposition layer on the silicon local oxide layer and the first gate oxide layer, or
And forming a first polysilicon deposition layer on the second shallow trench isolation and the first grid oxide layer.
12. The method of manufacturing a bidirectional asymmetric dual channel switching device as recited in any one of claims 7 to 10,
the step of forming the high-voltage oxide layer on the partial region of the first N-type drift drain region is omitted,
the step of forming a lightly doped region under the first sidewall layer further comprises
The lightly doped region further comprises: and forming a fourth lightly doped region between the first N + doped region and the first N-type drift drain region.
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