CN101030601A

CN101030601A - High-voltage MOSFET device

Info

Publication number: CN101030601A
Application number: CN 200710021390
Authority: CN
Inventors: 韩小亮; 王非
Original assignee: Individual
Current assignee: Individual
Priority date: 2007-04-10
Filing date: 2007-04-10
Publication date: 2007-09-05

Abstract

The invention is concerned with high voltage MOSFET device. There is deep n-wells on P or N tape underlay, at least the first n-well, the second n-well and the first and second p-well, and n-well and p-well have n+ adulteration area or p+ adulteration area, and the source or drain is leading from n+ adulteration area or p+ adulteration area. Usually, grid is leading from poly Si gate covering the thin gate oxide area of n-well or p-well, and there is at least one STI low groove insulation coating between source and drain, while poly Si gate extends to STI area. There is a layer low impurity p type underlay between high voltage drain and the second p-well to prevent the possible breakdown. The high voltage MOSFET device isolated with low groove can combine the breakdown protection characteristics to normal submicron CMOS without changing existing CMOS process.

Description

High-voltage MOSFET device

Technical field

The present invention relates to high voltage transistor, especially with shallow trench isolation from high-voltage MOSFET (metal oxide semiconductor field-effect) device; Particularly a kind of new high pressure NMOS FET (metal oxide semiconductor field effect tube) structure that contains extended drain based on standard sub-micron CMOS technology.

Background technology

The present invention relates to high voltage transistor, new high pressure NMOS FET (metal oxide semiconductor field effect tube) structure that contains extended drain under particularly a kind of standard sub-micron CMOS technology and the new extended drain high voltage PMOS FET structure that contains.The objective of the invention is under the condition that does not change existing CMOS technology breakdown characteristics is attached among the standard sub-micron CMOS and (only take the mask control technology).New high pressure NMOS that contains extended drain and PMOS can be realized by standard sub-micron CMOS technology fully, can reach the effect of high-breakdown-voltage and low on-resistance respectively.Owing to all can use existing technology, containing the high pressure NMOS of extended drain and the realization of PMOS need not increase any production cost.Breakdown characteristics is attached to the range of application that can expand it in the standard sub-micron CMOS technology, is included in the high pressure input/output function on the same chip in high speed analog signal and the high-density digital signal processing circuit.

Low voltage CMOS technology common optimised realize high density of integration, low-power consumption and high-speed.But these low voltage CMOS technologies can not satisfy the demand of system for high tension apparatus and circuit usually.Most high tension apparatus and circuit are to be realized by the high-pressure process of particular design.These special high-pressure process have only a smaller number of manufacturer to provide, and some specific step in high-pressure process have increased producing cost.A common solution is by revising low voltage CMOS technology the high-pressure modular compatibility to be entered.But these methods need additional photoetching and ion implantation step usually, and these have all caused expensive and complicated technology.

RESURF (reduction surface field) technology is used for realizing high pressure and low resistance device widely.The structure that high tension apparatus adopts usually is laterally diffused MOS (LDMOS) device architecture.Traditional LDMOSFET structure can provide very short raceway groove and be easy to integrated.The special diffusion technology that adopts during but its raceway groove forms and the low voltage CMOS device of standard are incompatible.Provided the profile that has integrated high pressure N raceway groove LDMOSFET now among Fig. 3.High pressure N raceway groove LDMOS 10 is made on the p-type high resistant substrate.First N ⁺ Doped region 13 is injected on the p-type substrate.Source electrode 18 is connected to first N ⁺On the doped region.High pressure n-well 12 is injected on the p-substrate.Second N ⁺ Doped region 14 is injected among the high pressure n-well 12.High pressure drain electrode 20 is connected to second N ⁺On the doped region 14.In high pressure n-well and second N ⁺Make between doped region 14 and channel region by first LOCOS (oxygen is isolated, or claims an oxide isolation region, thick oxygen zone) 15 and realize isolating.Polysilicon gate 17 covers thin grid oxygen 16 and extends to thick oxygen zone 15, realizes that the field plate effect has reduced near the electric field density the grid edge.Gate electrode 19 is connected on the polysilicon gate 17.Thick oxygen of 21 and the 3rd LOCOS of second LOCOS isolation separate from 22 opens high-voltage LDMOS FET and near device isolation.Mark L represents the device channel length in 13 to the high pressure n-well districts 12 from the source region.Mark B represents the horizontal proliferation length of high pressure n-well district under polysilicon gate.What mark A represented is the development length of polysilicon gate in LOCOS isolation 15.Mark S represents the length from LOCOS 15 to drain contact district 20.In such high-voltage LDMOS FET, high pressure n-well 12 is used as the drain region of device.High pressure n-well 12 provides high breakdown characteristics.Puncture voltage is determined by the doping content of high pressure n-well 12 and p-substrate.

Along with constantly dwindling of device architecture and minimum feature size, the shallow trench isolation that adopts usually at advanced person's semiconductor technology is from the partition method of (claim STI, down with).It almost is fully smooth that STI isolates the meaning device.In common high tension apparatus, the field plate techniques of isolating based on LOCOS (oxygen isolate) is used to reduce the electric field leaking the drift region.Lack thick oxygen zone, field and mean that then this field plate techniques can not be used to reduce the electric field at grid edge.This just means that this adopts the high voltage transistor of LOCOS structural design can not directly transfer in the technology that adopts STI.

Summary of the invention

The objective of the invention is to propose a kind of structure and preparation of high-voltage MOSFET device, especially with shallow trench isolation from high-voltage MOSFET device; Under the condition that does not change existing CMOS technology, breakdown characteristics is attached among the standard sub-micron CMOS and (only takes mask process).Propose high pressure NMOS that contains extended drain and PMOS can realize by standard sub-micron CMOS technology fully, can reach the effect of high-breakdown-voltage and low-resistance coefficient.

The present invention seeks to realize like this: high-voltage MOSFET device, has dark n-well on P (or N) the type substrate, at least be provided with a n-well, the 2nd n-well and first and second p-well, n-well and p-well are provided with on n+ doped region or the p+ doped region, and on n+ doped region or p+ doped region, draw source electrode or drain electrode, grid generally is to draw from polysilicon gate, polysilicon gate is covered in n-well or p-well goes up thin grid oxygen district (46), is provided with a STI shallow trench isolation layer at least between grid and the drain electrode; Polysilicon gate extends in the STI district.Puncture voltage is by a n-well, the 2nd p-well, the impurity concentration decision of dark n-well and p type substrate.

Between high voltage drain and the 2nd p-well, there is one deck to hang down impurity p type substrate, prevents issuable puncture between the two.

Particularly: high-voltage MOSFET comprises: a p type impurity substrate; P type impurity substrate is provided with the p-well district that substrate is injected in a dark n-well district; Other is provided with a p+ doped region and a body electrode that links to each other with the p+ doped region that injects a p-well district; Be provided with the n+ doped region (source electrode) and a source electrode that links to each other with the n+ doped region that inject a p-well district; Be provided with a n-well and the passage between a source electrode and a n-well district of injecting substrate; Being provided with the 2nd p-well that injects substrate and one injects substrate and does not have the n type or p type doped region that the p type injects; Be provided with the 2nd n-well that injects substrate and the 2nd n+ doped region (drain electrode) and a drain electrode that links to each other with the 2nd n+ doped region that inject the 2nd p-well;

Be provided with the 2nd p+ doped region and a underlayer electrode that links to each other with the 2nd p+ doped region that inject substrate;

Be provided with the 3rd p+ doped region and a underlayer electrode that links to each other with the 3rd p+ doped region that inject substrate;

Be provided with first slider (STI) to small part and inject a n-well and extend to the 2nd n-well, be provided with, isolate a n-well and the 2nd n-well at the 2nd p-well and the insulating barrier above the p type substrate;

Be provided with a insulating barrier, extend to above-mentioned first insulator from a n+ doped region (source electrode) at p type substrate surface;

Be provided with second slider (the 2nd STI), inject p type substrate, be provided with the electric insulation material, isolate a p+ doped region and the 2nd p+ doped region; Be provided with the 3rd slider (Three S's TI), inject p type substrate, be provided with the electric insulation material, isolate the 3rd p+ district and the 2nd p+ district; Be provided with a grid, cover in the thin grid oxygen district and part first slider between the source-drain electrode.The preparation of N type impurity substrate is as the same.

Can be provided with second grid, cover second insulating barrier, part first slider and part second slider.

In order to realize the mixed-signal IC of high complexity, the technical solution used in the present invention is to realize the high tension apparatus of particular design in standard CMOS process, and this method with the modification standard CMOS process that adopts in the past is different.The following detailed description the implementation method of high pressure N-channel MOS FET and P channel mosfet.This novel high-pressure MOSFET adopts the sub-micron CMOS technology of standard to realize.Fig. 4 a) and b) provided the low pressure NMOS and the PMOS section of structure that adopt in the standard sub-micron CMOS technology respectively.The breakdown characteristics of low pressure MOS device is decided by near the avalanche breakdown of drain edge raceway groove.

The invention has the beneficial effects as follows: the high-voltage MOSFET device of production has high-breakdown-voltage; Low-resistance coefficient; Production cost is low; Process complexity is low; High-performance; Range of application widely.

Description of drawings

Fig. 1 is the high pressure NMOS part section of structure that the present invention is based on standard sub-micron CMOS technology

Fig. 2 is the cross-sectional view of HV PMOS of the present invention

It among Fig. 3 the profile that has integrated high pressure N raceway groove LDMOSFET now

Fig. 4 a) and 4b) be respectively low pressure NMOS and the PMOS section of structure that adopts in the standard sub-micron CMOS technology; The breakdown characteristics of low pressure MOS device is decided by near the avalanche breakdown of drain edge raceway groove.

Fig. 5 is Id-Vd of the present invention (leakage current-drain voltage) parametric plot, has shown leakage current and the puncture voltage of high pressure N-channel MOS FET under the multiple situation.

Fig. 6 is the curve chart of impedance Vg of the present invention, has shown impedance and the grid voltage of high pressure N-channel MOS FET under the multiple situation.

Fig. 7 is Id-Vd (leakage current-drain voltage) curve chart of another kind of MOSFET device, has shown the leakage current and the puncture voltage of high pressure P channel mosfet under the multiple situation.

Fig. 8 is the curve chart of the impedance Vg of another kind of MOSFET device, has shown impedance and the grid voltage of high pressure N-channel MOS FET under the multiple situation.

Embodiment

This new high pressure NMOS structure can be used standard sub-micron CMOS technology fully, does not need to change any existing processing step.Body punctures the puncture of replacement silicon face, breakdown characteristics and reliability and all obtains based on specially designed high-voltage device structure.The HV NMOS structure that proposes is used a n-well, dark n-well, and the 2nd n-well makes a buffer area between raceway groove and drain electrode.Puncture voltage is by a n-well, the 2nd p-well, the impurity concentration decision of dark n-well and p type substrate.The surface impurity concentration of the one n-well is lower than the n-LDD of low-voltage device.High-breakdown-voltage depends on the district extending transversely of a n-well under grid, shown in Lo.The 2nd p-well is infused in position near a n-well to reach charge compensation, and the length of compensating basin depends on the technological design standard of used technology.The p-well that injects, n-well, dark n-well and p type substrate are cancelled out each other and are reached effective charge compensation, obtain an optimum breakdown voltage value by one that is distributed in the drift region lower electric field.Between high voltage drain and the 2nd p-well, there is one deck to hang down impurity p type substrate, prevents issuable puncture between the two.Polysilicon gate covers thin grid oxygen district and extends on first STI, to reduce the electric field of drift region near gate edge.

High pressure NMOS part structrual description: fully as shown in Figure 1 based on the high pressure NMOS part of standard sub-micron CMOS technology.High pressure NMOS part is produced on the p-substrate.A dark n-well 32 is injected on the p-type substrate.First p-well 33 is injected on the p-substrate.First n+ district 41 is injected among first p-well 33 and first p-well 33 is also injected in first p+ district.Source electrode 50 is connected on first n+ doped region 41.Body electrode 49 is connected on first p+ doped region 40.First n-well 34 is injected on the p-type substrate.Second p-well 35 is injected on the p-substrate.P type island region 36 is parts of p-type substrate, injects without any n type or p type.Second n-well 37 is injected on the p-type substrate.First n-well 34, second p-well 35, p-type substrate 36 and second n-well 37 are positioned on the dark n-well 32, and first n-well 34 and second n-well 37 couple together the drain region that forms high pressure NMOS part by dark n-well 32.First STI district 42 is positioned on the p-type substrate 37.Second p-well district 35 is injected on the p-type substrate 31.First STI 42 extends on second n-well 37 from first n-well 34 districts.Second n+ district 43 is injected among second n-well37.Drain electrode 51 is connected to second n+ district 43.The polysilicon gate 47 of a n+ doping is covered in thin grid oxygen district 46 and extends in first STI district 42.Second STI district 39 and the 3rd STI district 44 are fabricated on the p-type substrate.Second p+ type doped region 38 and the 3rd p+ doped region 45 are fabricated on p-type substrate zone 31.First underlayer electrode 48 is connected to p+ type doped region 38.Second underlayer electrode 52 is connected to second p+ type doped region 45.Second STI 39 keeps apart first p+ doped region 40 and second p+ type doped region 38.The 3rd STI district 44 keeps apart second n+ type drain region 43 and the 3rd p+ type doped region 45.Mark Lc has represented the channel length of device.Mark Lo is the expansion area that is positioned at first n-well 34 under the polysilicon gate 47.Mark Lnw has represented the length in first n-well district 34.Mark Lpw has represented to be positioned at second p-well district 35 under first STI district 42.Mark Lps has represented to be positioned at the p-type substrate zone 36 under first STI district 42.Mark Ldn has represented the length in dark n-well district 32.Mark Lf is the development lengths of polysilicon gate 47 districts in first STI 42 districts.Wherein: the length of Lc is more than or equal to 2.0 microns; The length of Lo is more than or equal to 0.3 micron; The length of Lnw is more than or equal to 0.6 micron; The length of Lpw is more than or equal to 0.6 micron; The length of Lps is more than or equal to 0.6 micron; The length of Ldn is more than or equal to 3.0 microns; The length of Lf is more than or equal to 0.5 micron.

Especially the length of Lc equals the 2.0-6 micron; The length of Lo equals the 0.3-1 micron; The length of Lnw equals the 0.6-2 micron; The length of Lpw equals the 0.6-2 micron; The length of Lps equals the 0.6-2 micron; The length of Ldn equals the 3.0-15 micron; The length of Lf equals the 0.5-2 micron.For example get among the embodiment: 2.0 microns of the length of Lc; The length of Lo equals 0.3 micron; The length of Lnw equals 0.6 micron; The length of Lpw equals 0.6 micron; The length of Lps equals 0.6 micron; The length of Ldn equals 3.0 microns; The length of Lf equals 0.5 micron.The length of another example: Lc equals 5.0 microns; The length of Lo equals 1 micron; The length of Lnw equals 2 microns; The length of Lpw equals 2 microns; The length of Lps equals 2 microns; The length of Ldn equals 15 microns; The length of Lf equals 2 microns; Size than above-mentioned size big 10% still has effect same.

HV NOMS transistor design parameters must be improved to reach the optimum performance of puncture voltage and resistance coefficient.Fig. 5 is Id-Vd (leakage current-drain voltage) curve chart, has shown leakage current and the puncture voltage of high pressure N-channel MOS FET under the multiple situation.Fig. 6 is the curve chart of impedance Vg, has shown impedance and the grid voltage of high pressure N-channel MOS FET under the multiple situation.

The detailed description of HV PMOS device:

Fig. 2 is the cross section of HV PMOS of the present invention, as shown in the figure, processes on a p type substrate 61 based on the high pressure P channel mosfet that extended drain is arranged 60 of standard sub-micron CMOS technology, and a dark n-well 62 is infused on the p type substrate 61.The one n-well 63 is machined on the p type substrate 61.The one n+ doped region 71 and a p+ doped region 72 processing are on a n-well 63.The first body electrode 85 is connected with a n+ doped region 71.A source electrode 86 is connected with a p+ doped region 72.The one p-well 64 is infused on the p type substrate 61.The one p type district 65 is parts of p type substrate 61 and without any the injection of n type or p type.The 2nd p-well 66 is infused on the p type substrate 61.The 2nd p+ doped region 75 is infused on the 2nd p-well 66.A drain electrode is connected with the 2nd p+ doped region 75.The 2nd p type district 67 is parts of p type substrate 61 and without any the injection of n type or p type.The 2nd n-well 68 is infused on the p type substrate 61.The 2nd n+ doped region 77 is infused on the 2nd n-well 68.The second body electrode 88 is connected with the 2nd n+ doped region 77.The 3rd p+ doped region 69 and the 4th p+ doped region 79 also are infused on the p type substrate 61.First underlayer electrode 84 is connected with the 3rd p+ doped region 69, and second underlayer electrode 89 is connected with the 4th p+ doped region 79.A STI 73 who is positioned at above the p type district 65 is infused on the p type substrate 61, and isolates a p-well 64 and the 2nd p-well 65.The first thin oxygen insulating barrier 80 extends on the STI 73 from a p+ doped region 72.First polysilicon 81 covers first thin oxygen layer 80 and part the one STI 73.Second polysilicon 82 covers second thin oxygen layer 83, part the one STI 73 and part the 2nd STI 74.Three S's TI 76 isolates the 2nd p+ doped region 75 and the 2nd n+ doped region 77.The 4th STI 78 isolates the 2nd n+ doped region 77 and the 4th p+ doped region 79.The 5th STI 70 isolates the 3rd a p+ doped region 69 and a n+ doped region 71.Lc represents to extend to from a p+ doped region 72 length of the raceway groove of a p-well 64.Lo represents to be positioned at the length in the district extending transversely of the p-well 64 under the grid 81.Lpw1 is the length of a p-well 64.Lps represents to be positioned at the length in the p type district 65 below the STI 73, and p type district does not have n-well or p-well to inject.Lpw2 is the 2nd p-well 66 length.Lpn represents the length between the 2nd p-well 66 and the 2nd n-well 68.Lf is the length that extends to first polysilicon of a STI 73 from thin oxygen layer 80.

High voltage PMOS device is made under standard sub-micron CMOS technology, need not any additional step.Because it is interior rather than surperficial that maximum field occurs in device, HV PMOS can realize high-breakdown-voltage and good reliability.Because second multi-crystal silicon area is arranged, the impurity concentration of the 2nd p-well is higher than the p-well below the STI, and this just makes HV PMOS that lower impedance factor can be arranged.Different with HV NMOS structure is, a p-well, and a p type district and the 2nd p-well are as the extended drain drift region of device.Puncture voltage depends on a p-well, p type district, the impurity concentration of a dark n-well and a n-well.The surface impurity concentration of the one p-well is lower than the p-LDD in the low-voltage device, so the surface field reduction, can obtain higher puncture voltage.The high-breakdown-voltage value gives the credit to the district extending transversely that is positioned at the p-well below grid and the p type district, shown in Lo.P type impurity substrate in the drain-drift region has reduced doping content, so the electric field of drain-drift region has also reduced.Dark n-well couples together a n-well and the 2nd n-well, forms the main body of device, and dark n-well helps to reduce a n-well, and the electric charge load of p type district and the 2nd n-well realizes charge compensation.A lower electric field that is distributed in the drift region like this can produce an optimum breakdown voltage value.

Identical with the HV nmos device, HV PMOS transistor design parameters also must be perfect, to reach the optimum performance of puncture voltage and resistance coefficient.Fig. 7 is Id-Vd (leakage current-drain voltage) curve chart, has shown the leakage current and the puncture voltage of high pressure P channel mosfet under the multiple situation.Fig. 8 is the curve chart of impedance Vg, has shown impedance and the grid voltage of high pressure N-channel MOS FET under the multiple situation.

The invention provides a kind of new high pressure NMOS structure and high voltage PMOS structure of using standard sub-micron CMOS technology fully, two kinds have all substituted the LOCOS isolation structure with sti structure.The high pressure NMOS design is gone up with n-well and dark n-well and is formed extended drain, and other parts are all identical with low pressure NMOS.P-well is infused in to sentence near n-well and reaches charge compensation.In addition, the polysilicon gate extension ends at the electric field that STI reduces close gate edge in the extended drain.The high voltage PMOS of sti structure forms extended drain with p-well and p-substrate, other parts are all identical with low pressure PMOS, first polysilicon gate ends at STI to reduce the electric field of close gate edge in the extended drain, and second polysilicon gate is used for improving impurity concentration semiconductor and reduces resistance coefficient simultaneously.High-breakdown-voltage and Low ESR are obtained by the high tension apparatus of clearly design.This method can allow the designer will in/the high-pressure electronic combination of elements is applied in the standard sub-micron technology.Also can allow HV design engineer design HV MOSFET, reduce HV technology and the transistorized production cost of HV with the STI method.

Above-mentioned grid is n+ type impurity polysilicon.The insulating barrier material is silicon dioxide.Slider all uses the manufacturing of STI (shallow trench) technology.Lc length is more than or equal to 2.0 microns; Lo length is more than or equal to 0.3 micron; Lpw1 length is more than or equal to 0.6 micron; Lps length is more than or equal to 0.6 micron; Lpw2 length is more than or equal to 0.6 micron; Lpn length is more than or equal to 0.6 micron; Ldn length is more than or equal to 5.0 microns.Especially the length of Lc equals the 2.0-6 micron; Lo length equals the 0.3-1 micron; Lpw1 length equals the 0.6-2 micron; Lps length equals the 0.6-2 micron; Lpw2 length equals the 0.6-2 micron; Lpn length equals the 0.6-2 micron; Ldn length equals the 5.0-20 micron.Specific embodiment is: the length of Lc equals 2.0 microns; Lo length equals 0.3 micron; Lpw1 length equals 0.6 micron; Lps length equals 0.6 micron; Lpw2 length equals 0.6 micron; Lpn length equals 0.6 micron; Ldn length equals 5.0 microns.Another embodiment is that the length of Lc equals 6 microns; Lo length equals 1 micron; Lpw1 length equals 2 microns; Lps length equals 2 microns; Lpw2 length equals 2 microns; Lpn length equals 2 microns; Ldn length equals 20 microns.

Claims

1, high-voltage MOSFET device, on P or N type substrate, has dark n-well, at least be provided with a n-well, the 2nd n-well and first and second p-well, n-well and p-well are provided with on n+ doped region or the p+ doped region, and draw source electrode or drain electrode on n+ doped region or p+ doped region, and grid is to draw from polysilicon gate, it is characterized in that polysilicon gate is covered in n-well or p-well goes up thin grid oxygen district (46), be provided with a STI shallow trench isolation layer at least between grid and the drain electrode; Polysilicon gate extends in the STI district.

2, high-voltage MOSFET device according to claim 1 is characterized in that having between high voltage drain and the 2nd p-well one deck to hang down impurity p type substrate, prevents issuable puncture between the two.

3, high-voltage MOSFET device according to claim 1 is characterized in that on a p type impurity substrate, and p type impurity substrate is provided with a dark n-well district and injects a p-well district of substrate; Other is provided with a p+ doped region and a body electrode that links to each other with the p+ doped region that injects a p-well district; Be provided with the n+ doped region source electrode and a source electrode that links to each other with the n+ doped region that inject a p-well district; Be provided with a n-well and the passage between a source electrode and a n-well district of injecting substrate; Being provided with the 2nd p-well that injects substrate and one injects substrate and does not have the n type or p type doped region that the p type injects; Be provided with the 2nd n-well that injects substrate and the drain electrode of the 2nd n+ doped region and a drain electrode that links to each other with the 2nd n+ doped region of injecting the 2nd p-well;

Be provided with second slider (the 2nd STI), inject p type substrate, be provided with the electric insulation material, isolate a p+ doped region and the 2nd p+ doped region; Be provided with the 3rd slider (Three S's TI), inject p type substrate, be provided with the electric insulation material, isolate the 3rd p+ district and the 2nd p+ district; Be provided with a grid, cover in the thin grid oxygen district and part first slider between the source-drain electrode.

4, high-voltage MOSFET device according to claim 3 is characterized in that being provided with second grid, covers second insulating barrier and part first slider and part second slider.

5, high-voltage MOSFET device according to claim 3 is characterized in that Lo is the expansion area that is positioned at first n-well (34) under the polysilicon gate (47); Lnw has represented the length in first n-well district (34), and Lpw has represented to be positioned at second the p-well district (35) under first STI district (42), and Lps has represented to be positioned at the p-type substrate zone (36) under first STI district (42); Ldn has represented the length in dark n-well district (32), and Lf is the development length of polysilicon gate (47) district in first STI (42) district; The length of Lc is more than or equal to the 2.0-6 micron; The length of Lo is more than or equal to the 0.3-1 micron; The big son of the length of Lnw or equal the 0.6-2 micron; The length of Lpw is more than or equal to the 0.6-2 micron; The length of Lps is more than or equal to the 0.6-2 micron; The length of Ldn is more than or equal to the 3.0-15 micron; The length of Lf is more than or equal to the 0.5-2 micron.

6, high-voltage MOSFET device according to claim 1 is characterized in that high pressure p channel mosfet on a p type impurity substrate, comprising: a p type impurity substrate; Substrate is provided with a dark n-well district; Inject a n-well of substrate;

Inject a n+ doped region in a n-well district; The first body electrode that links to each other with a n+ doped region; Inject a p+ doped region in a n-well district; A source electrode that links to each other with a p+ doped region; Inject a p-well of p type substrate; Raceway groove between a source electrode and a n-well district; Inject a p doped region of substrate, doped region is without any the injection of p type or n type; Inject the 2nd p-well of p type doped substrate; Inject the 2nd p+ doped region of the 2nd p-well; A drain electrode that links to each other with the 2nd p+ doped region;

Inject the 2nd p doped region of substrate, doped region injects without any p type or n type; Inject the 2nd n-well of substrate; Inject the 2nd n+ doped region of the 2nd n-well; Inject the 3rd p+ doped region of p type substrate; First underlayer electrode that links to each other with the 3rd p+ doped region;

Inject the 4th p+ doped region of p type substrate; Second underlayer electrode that links to each other with the 4th p+ doped region; First slider (STI) injects a p-well and extends to the 2nd p-well to small part, is positioned on the substrate, comprises megohmite insulant, isolates a p-well and the 2nd p-well;

Second slider (the 2nd STI) injects the 2nd p-well;

The 3rd slider (Three S's TI) injects p type substrate, isolates p+ doped region (drain electrode) and the 2nd n+ doped region;

The 4th slider (the 4th STI) injects p type substrate, isolates a p+ doped region (substrate) and a n+ doped region;

The 5th slider (the 5th STI) injects p type substrate, isolates the 2nd p+ doped region (substrate) and the 2nd n+ doped region;

First insulating barrier covers p type substrate surface, extends to first slider from a n+ doped region (source electrode);

Second insulating barrier covers p type substrate surface, extends to second slider from first slider;

First grid covers first insulating barrier and part first slider;

Second grid covers second insulating barrier, part first slider and part second slider.

7, the high pressure P channel mosfet in the claim 6, wherein grid is p+ type impurity polysilicon; Lc length is more than or equal to the 2.0-6 micron; Lc is for extending to the length of the raceway groove of a p-well (64) from a p+ doped region (72); Lo is the length that is positioned at the district extending transversely of the p-well (64) under the grid (81); Lpwl is the length of a p-well (64); Lps is positioned at the length in the p type district (65) below the STI (73), and p type district does not have n-well or p-well to inject; Lpw2 is the 2nd p-well (a 66) length; Lpn represents the length between the 2nd p-well (66) and the 2nd n-well (68); Lf is the length that extends to first polysilicon of a STI (73) from thin oxygen layer (80); Lo length is more than or equal to the 0.3-1 micron; Lpw1 length is more than or equal to the 0.6-2 micron; Lps length is more than or equal to the 0.6-2 micron; Lpw2 length is more than or equal to the 0.6-2 micron; Lpn length is more than or equal to the 0.6-2 micron; Ldn length is more than or equal to the 5.0-20 micron.