CN1199250C - 对准管芯与柔性基板上的通孔掩模层的装置和方法 - Google Patents
对准管芯与柔性基板上的通孔掩模层的装置和方法 Download PDFInfo
- Publication number
- CN1199250C CN1199250C CNB001364499A CN00136449A CN1199250C CN 1199250 C CN1199250 C CN 1199250C CN B001364499 A CNB001364499 A CN B001364499A CN 00136449 A CN00136449 A CN 00136449A CN 1199250 C CN1199250 C CN 1199250C
- Authority
- CN
- China
- Prior art keywords
- die
- welding pad
- bonding welding
- hole
- flexible substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
- H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
- H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07321—Aligning
- H10W72/07327—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9413—Dispositions of bond pads on encapsulations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49131—Assembling to base an electrical component, e.g., capacitor, etc. by utilizing optical sighting device
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Laser Beam Processing (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Manufacturing Of Printed Wiring (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/469749 | 1999-12-22 | ||
| US09/469,749 US6475877B1 (en) | 1999-12-22 | 1999-12-22 | Method for aligning die to interconnect metal on flex substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1301039A CN1301039A (zh) | 2001-06-27 |
| CN1199250C true CN1199250C (zh) | 2005-04-27 |
Family
ID=23864927
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001364499A Expired - Lifetime CN1199250C (zh) | 1999-12-22 | 2000-12-22 | 对准管芯与柔性基板上的通孔掩模层的装置和方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US6475877B1 (https=) |
| EP (1) | EP1111662B1 (https=) |
| JP (1) | JP4931277B2 (https=) |
| CN (1) | CN1199250C (https=) |
| TW (1) | TW490716B (https=) |
Families Citing this family (65)
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| US6888240B2 (en) | 2001-04-30 | 2005-05-03 | Intel Corporation | High performance, low cost microelectronic circuit package with interposer |
| US6894399B2 (en) | 2001-04-30 | 2005-05-17 | Intel Corporation | Microelectronic device having signal distribution functionality on an interfacial layer thereof |
| US7071024B2 (en) | 2001-05-21 | 2006-07-04 | Intel Corporation | Method for packaging a microelectronic device using on-die bond pad expansion |
| US7183658B2 (en) * | 2001-09-05 | 2007-02-27 | Intel Corporation | Low cost microelectronic circuit package |
| JP3645511B2 (ja) * | 2001-10-09 | 2005-05-11 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
| US8455994B2 (en) * | 2002-01-31 | 2013-06-04 | Imbera Electronics Oy | Electronic module with feed through conductor between wiring patterns |
| FI119215B (fi) * | 2002-01-31 | 2008-08-29 | Imbera Electronics Oy | Menetelmä komponentin upottamiseksi alustaan ja elektroniikkamoduuli |
| FI115285B (fi) * | 2002-01-31 | 2005-03-31 | Imbera Electronics Oy | Menetelmä komponentin upottamiseksi alustaan ja kontaktin muodostamiseksi |
| US6964881B2 (en) * | 2002-08-27 | 2005-11-15 | Micron Technology, Inc. | Multi-chip wafer level system packages and methods of forming same |
| US6855953B2 (en) * | 2002-12-20 | 2005-02-15 | Itt Manufacturing Enterprises, Inc. | Electronic circuit assembly having high contrast fiducial |
| US7263677B1 (en) * | 2002-12-31 | 2007-08-28 | Cadence Design Systems, Inc. | Method and apparatus for creating efficient vias between metal layers in semiconductor designs and layouts |
| FI115601B (fi) * | 2003-04-01 | 2005-05-31 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli |
| US8704359B2 (en) | 2003-04-01 | 2014-04-22 | Ge Embedded Electronics Oy | Method for manufacturing an electronic module and an electronic module |
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| CN1302541C (zh) * | 2003-07-08 | 2007-02-28 | 敦南科技股份有限公司 | 具有柔性电路板的芯片封装基板及其制造方法 |
| FI20031201A7 (fi) * | 2003-08-26 | 2005-02-27 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli |
| FI20031341L (fi) | 2003-09-18 | 2005-03-19 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi |
| TWI237883B (en) * | 2004-05-11 | 2005-08-11 | Via Tech Inc | Chip embedded package structure and process thereof |
| FI117814B (fi) * | 2004-06-15 | 2007-02-28 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi |
| TWI250596B (en) * | 2004-07-23 | 2006-03-01 | Ind Tech Res Inst | Wafer-level chip scale packaging method |
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| JP5091600B2 (ja) * | 2006-09-29 | 2012-12-05 | 三洋電機株式会社 | 半導体モジュール、半導体モジュールの製造方法および携帯機器 |
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| US9610758B2 (en) * | 2007-06-21 | 2017-04-04 | General Electric Company | Method of making demountable interconnect structure |
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| US9953910B2 (en) * | 2007-06-21 | 2018-04-24 | General Electric Company | Demountable interconnect structure |
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| US20080313894A1 (en) * | 2007-06-21 | 2008-12-25 | General Electric Company | Method for making an interconnect structure and low-temperature interconnect component recovery process |
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| CN101373748B (zh) * | 2007-08-20 | 2011-06-15 | 宏茂微电子(上海)有限公司 | 晶圆级封装结构及其制作方法 |
| JP4966156B2 (ja) * | 2007-10-23 | 2012-07-04 | ソニーケミカル&インフォメーションデバイス株式会社 | 配線基板の受台及びこれを用いた配線基板の接続装置、接続方法 |
| US9010225B2 (en) * | 2007-12-21 | 2015-04-21 | Tokyo Seimitsu Co., Ltd. | Dicing apparatus and dicing method |
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| WO2011065062A1 (ja) * | 2009-11-30 | 2011-06-03 | シャープ株式会社 | フレキシブル回路基板およびその製造方法 |
| US8623689B2 (en) * | 2010-07-07 | 2014-01-07 | Ineffable Cellular Limited Liability Company | Package process of backside illumination image sensor |
| JP5399542B2 (ja) * | 2012-08-08 | 2014-01-29 | 富士通株式会社 | 半導体装置の製造方法 |
| JP5554380B2 (ja) * | 2012-08-08 | 2014-07-23 | 富士通株式会社 | 半導体装置 |
| WO2014097641A1 (ja) * | 2012-12-21 | 2014-06-26 | パナソニック株式会社 | 電子部品パッケージおよびその製造方法 |
| WO2014097644A1 (ja) * | 2012-12-21 | 2014-06-26 | パナソニック株式会社 | 電子部品パッケージおよびその製造方法 |
| JP5624699B1 (ja) * | 2012-12-21 | 2014-11-12 | パナソニック株式会社 | 電子部品パッケージおよびその製造方法 |
| US9449944B2 (en) | 2012-12-21 | 2016-09-20 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component package and method for manufacturing same |
| CN104584207A (zh) | 2012-12-21 | 2015-04-29 | 松下知识产权经营株式会社 | 电子部件封装以及其制造方法 |
| DE102015214219A1 (de) * | 2015-07-28 | 2017-02-02 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines Bauelements und ein Bauelement |
| JP2017073472A (ja) * | 2015-10-07 | 2017-04-13 | 株式会社ディスコ | 半導体装置の製造方法 |
| CN110024107B (zh) * | 2016-11-30 | 2023-11-10 | 深圳修远电子科技有限公司 | 集成电路封装方法以及集成封装电路 |
| EP3557608A1 (en) | 2018-04-19 | 2019-10-23 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Packaged integrated circuit with interposing functionality and method for manufacturing such a packaged integrated circuit |
| EP3833164A1 (en) | 2019-12-05 | 2021-06-09 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Compensating misalignment of component carrier feature by modifying target design concerning correlated component carrier feature |
| US20240145258A1 (en) * | 2022-10-27 | 2024-05-02 | Stmicroelectronics Pte Ltd | Panel level semiconductor package and method of manufacturing the same |
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| JP3919972B2 (ja) * | 1998-07-31 | 2007-05-30 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
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| US6242282B1 (en) * | 1999-10-04 | 2001-06-05 | General Electric Company | Circuit chip package and fabrication method |
| US6271469B1 (en) * | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
-
1999
- 1999-12-22 US US09/469,749 patent/US6475877B1/en not_active Expired - Lifetime
-
2000
- 2000-12-11 TW TW089126381A patent/TW490716B/zh not_active IP Right Cessation
- 2000-12-21 EP EP00311553A patent/EP1111662B1/en not_active Expired - Lifetime
- 2000-12-21 JP JP2000388006A patent/JP4931277B2/ja not_active Expired - Lifetime
- 2000-12-22 CN CNB001364499A patent/CN1199250C/zh not_active Expired - Lifetime
-
2002
- 2002-07-22 US US10/199,296 patent/US6790703B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP1111662B1 (en) | 2012-12-12 |
| JP4931277B2 (ja) | 2012-05-16 |
| EP1111662A2 (en) | 2001-06-27 |
| US20020197767A1 (en) | 2002-12-26 |
| US6475877B1 (en) | 2002-11-05 |
| TW490716B (en) | 2002-06-11 |
| EP1111662A3 (en) | 2003-10-01 |
| CN1301039A (zh) | 2001-06-27 |
| US6790703B2 (en) | 2004-09-14 |
| JP2001250888A (ja) | 2001-09-14 |
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