WO2005086553A1 - 多層基板の製造方法 - Google Patents
多層基板の製造方法 Download PDFInfo
- Publication number
- WO2005086553A1 WO2005086553A1 PCT/JP2005/003562 JP2005003562W WO2005086553A1 WO 2005086553 A1 WO2005086553 A1 WO 2005086553A1 JP 2005003562 W JP2005003562 W JP 2005003562W WO 2005086553 A1 WO2005086553 A1 WO 2005086553A1
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- WIPO (PCT)
- Prior art keywords
- confirmation
- hole
- manufacturing
- multilayer substrate
- wiring layer
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 59
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4679—Aligning added circuit layers or via connections relative to previous circuit layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0548—Masks
- H05K2203/0554—Metal used as mask for etching vias, e.g. by laser ablation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0008—Apparatus or processes for manufacturing printed circuits for aligning or positioning of tools relative to the circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the present invention relates to a method for manufacturing a multilayer substrate, and more particularly, to a method for manufacturing a multilayer substrate that can improve the accuracy of the position of each wiring layer.
- the first conductive foil 1001 A and the second conductive material are formed on the front and back surfaces of the base material 100 made of an insulating material such as a resin. Adhere foil 1 0 1 B closely.
- the first conductive foil 1001A and the second conductive foil 1001B are selectively etched, whereby the first conductive foil 1001A is selectively etched.
- a wiring layer 1 0 2 A and a second wiring layer 1 0 2 B are formed.
- a wiring layer is laminated through the insulating layer 103 A to realize a multilayer wiring structure as shown in FIG. 9 (C).
- the connecting portion 104 is a portion for electrically connecting the wiring layers.
- the method described above has a problem that an error occurs in the position between the wiring layers.
- demands for miniaturization and higher functionality are increasing, and the patterns are becoming increasingly finer.
- strict accuracy is required for the connection between layers and the positional accuracy of each wiring layer. Has been.
- the present invention has been made in view of the above-described problems, and the main object of the present invention is to suppress the displacement of the relative positions of the layers, and the position of the connection portion that electrically connects the layers. It is an object of the present invention to provide a method for manufacturing a multi-layer substrate that can accurately form the substrate. Disclosure of the invention
- the multilayer substrate manufacturing method of the present invention is a multilayer substrate manufacturing method in which a plurality of wiring layers composed of wiring and / or electrodes are formed via an insulating material, and a confirmation part is provided on the first wiring layer, When the second and subsequent wiring layers are formed, patterning is performed with reference to the confirmation portion of the first layer.
- the method for manufacturing a multilayer board according to the present invention provides a method for manufacturing a multilayer board in which a wiring layer made of wiring op- posite Z or an electrode is insulated and formed on both sides of a core part made of an insulating material.
- a confirmation part is provided in the first wiring layer formed on at least one side of the part, and when the second and subsequent wiring layers are formed, the confirmation part in the first layer is used as a reference. It is characterized by patterning.
- the multilayer substrate manufacturing method of the present invention is a method for manufacturing a multilayer substrate in which a wiring layer composed of wiring and / or electrodes is insulated and formed in a plurality of layers on both sides of a core portion composed of a sheet-like insulating material. A part of the first wiring layer formed on both surfaces of the core part is provided, a confirmation part penetrating perpendicularly to the core part is provided, and the second and subsequent wiring layers are formed when the second and subsequent wiring layers are formed. It is characterized by patterning based on the confirmation part of the first layer.
- the method for manufacturing a multilayer board according to the present invention is characterized in that when the confirmation part is used as a reference, the insulating material and the wiring layer formed on the upper part of the confirmation part are removed. .
- the method for manufacturing a multilayer board according to the present invention is characterized in that the confirmation portion is circular as viewed from above.
- the position of the wiring layer serving as a reference is It is characterized by recognition using X-rays.
- the method for manufacturing a multilayer substrate according to the present invention includes a step of preparing a sheet in which the first conductive film is laminated on both main surfaces of the first insulating film serving as a core, and a columnar shape penetrating the sheet. Forming a first confirmation hole, etching the first conductive film corresponding to the first connection portion on the basis of the confirmation hole, removing the exposed first insulating film, and removing the first insulation film.
- Forming the first wiring layer Forming the first wiring layer, forming the second conductive film on both sides of the sheet via the second insulating film, exposing the confirmation hole, and Etch the second conductive film corresponding to the connecting portion, and remove the exposed second insulating film.
- the method for manufacturing a multilayer substrate according to the present invention is characterized in that the confirmation hole located under the second conductive film is recognized using X-rays.
- the first wiring layer for forming the confirmation hole is formed in a bowl shape around the opening, and a laser is formed inside the bowl-shaped first wiring layer. And the second insulating film is removed.
- FIG. 1 (A) is a plan view showing a method for manufacturing a multilayer board of the present invention
- FIG. 1 (B) is a cross-sectional view showing a method for manufacturing a multilayer board of the present invention.
- (C) is a cross-sectional view showing a method for producing a multilayer substrate of the present invention
- FIG. 1 (D) is a cross-sectional view showing a method for producing a multilayer substrate of the present invention
- FIG. FIG. 1 (F) is a sectional view showing a method for producing a multilayer substrate of the present invention
- FIG. 2 (A) is a sectional view showing a method for producing a multilayer substrate of the present invention.
- FIG. 1 (A) is a plan view showing a method for manufacturing a multilayer board of the present invention
- FIG. 1 (B) is a cross-sectional view showing a method for manufacturing a multilayer board of the present invention.
- (C) is a cross-sectional view showing a
- FIG. 2 (B) is a cross-sectional view showing a method for producing a multilayer substrate of the present invention
- FIG. 2 (C) shows a method for producing a multilayer substrate of the present invention
- FIG. 2 (D) is a cross-sectional view showing a method for manufacturing a multilayer substrate of the present invention
- FIG. 3 (A) is a plan view showing a method for manufacturing the multilayer substrate of the present invention
- FIG. 3 (B) is a cross-sectional view showing a method for producing a multilayer substrate of the present invention
- FIG. 3 (C) is a cross-sectional view showing a method for producing a multilayer substrate of the present invention.
- FIG. 4 (D) is a cross-sectional view showing a method for manufacturing a multilayer substrate according to the present invention
- FIG. 4 (A) is a cross-sectional view showing a method for manufacturing a multilayer substrate according to the present invention
- FIG. 4 is a cross-sectional view showing a method for producing a multilayer board according to the present invention
- FIG. 4 (C) is a conceptual diagram showing a method for producing a multilayer board according to the present invention.
- FIG. 5 (A) is a plan view showing a method for manufacturing a multilayer board according to the present invention
- FIG. 5 (B) is a cross-sectional view showing a method for manufacturing the multilayer board according to the present invention.
- FIG. 5 (A) is a plan view showing a method for manufacturing a multilayer board according to the present invention
- FIG. 5 (B) is a cross-sectional view showing a method for manufacturing the multilayer board according to the present invention.
- FIG. 6 is a cross-sectional view showing a method for producing a multilayer substrate of the present invention
- FIG. 6 (A) is a cross-sectional view showing a method for producing a multilayer substrate of the present invention
- FIG. 6 (B) is a diagram showing the present invention
- FIG. 7 (A) is a plan view showing the method for manufacturing the multilayer substrate of the present invention
- FIG. 7 (B) is the multilayer substrate of the present invention
- FIG. 7 (C) is a cross-sectional view showing a method for producing a multilayer board of the present invention
- FIG. 7 (D) is a method for producing a multilayer tomb board of the present invention.
- FIG. 7 (A) is a plan view showing the method for manufacturing the multilayer substrate of the present invention
- FIG. 7 (B) is the multilayer substrate of the present invention
- FIG. 7 (C) is a cross-sectional view showing a method for producing a multilayer board of the present invention
- FIG. 7 (D)
- FIG. 8 (A) is a cross-sectional view illustrating a structure in which the multilayer substrate manufactured by the multilayer substrate manufacturing method of the present invention is employed.
- FIG. 8 (B) is a cross-sectional view illustrating a structure in which the multilayer substrate manufactured by the multilayer substrate manufacturing method of the present invention is employed, and
- FIG. 9 (A) is a conventional multilayer substrate.
- FIG. 9 (B) is a sectional view showing a conventional multilayer substrate manufacturing method
- FIG. 9 (C) is a sectional view showing a conventional multilayer substrate manufacturing method. It is sectional drawing shown. BEST MODE FOR CARRYING OUT THE INVENTION
- the wiring refers to a wiring structure having two or more layers, and corresponds to a board having a multilayer wiring or a multilayer board on which a circuit device is mounted for packaging.
- the multilayer substrate manufacturing method of this embodiment is a multilayer substrate manufacturing method in which the wiring layer 14 formed by patterning the conductive film 13 is stacked via the insulating film 1 2.
- a confirmation hole 14 is provided in the conductive film 13 to be formed, and after the position of the confirmation hole 14 is recognized, the patterning of the second and subsequent wiring layers 18 is performed. Furthermore, in this embodiment, the connection portion 16 that connects the wiring layers is formed using this confirmation portion. Details will be described below.
- FIG. 1 (A) is a plan view of the laminated sheet 10 in this process
- FIGS. 1 (B) to 1 (F) are sectional views of the laminated sheet 10 in each process. .
- the laminated sheet 10 is obtained by bringing the first and second conductive films 13 A and 13 B into close contact with both surfaces of the first insulating film 12 A serving as a core.
- the material of the first insulating film 12 A either thermoplastic resin or thermosetting resin is selected.
- inorganic fillers are mixed in the resin.
- the first insulating film 12 A may contain glass cloth, or may contain glass filler mixed with inorganic filler.
- the thickness of the first insulating film 12 A can be set to about 50 microns.
- a metal mainly composed of copper can be generally used as a material for the first and second conductive films 1 3 A and 1 3 B.
- a rolled copper foil is used as the material for the first and second conductive films 13 A and 13 B.
- the thickness of both conductive foils may be about 10 microns.
- the two conductive films are coated directly on the first insulating film 12 A by a plating method, a vapor deposition method or a sputtering method, or a metal foil formed by a rolling method is attached. Also good.
- the layer sheet 10 is formed with a plurality of units 11 which are regions constituting one multilayer substrate.
- units 11 are formed on a laminated sheet 10.
- Unit 1 1 has a rectangular planar shape, but it may be another shape of Unit 11.
- a confirmation hole 14 is provided so as to penetrate the laminated sheet 10.
- This confirmation hole 14 is a confirmation part for performing alignment when performing patterning for the second and subsequent layers.
- the confirmation hole 14 is also used when forming the connection portion 16 that electrically connects the wiring layers 13.
- the confirmation hole 14 can be formed by drilling with a drill. Further, after removing both conductive foils 13 in the formation region of the confirmation hole 14 by etching, the exposed insulating film may be removed by laser.
- the diameter of the confirmation hole 14 formed in this step is, for example, about 0.15 mm.
- a confirmation hole 14 is formed in the vicinity of the outside of each unit 11. Further, by providing a plurality of confirmation holes 14 for each unit 11, the alignment accuracy using the confirmation holes 14 can be further improved.
- four confirmation holes 14 are provided in the vicinity of the four corners of each unit 11.
- the number of 1 4 is arbitrary.
- two confirmation holes 14 may be formed for each unit 14.
- the number of confirmation holes 14 formed in one laminated sheet 10 can be changed within a range of about two hundred force and one hundred.
- the first conductive film 13 A is partially removed to form an exposed portion 15 where the first insulating film 12 A is exposed.
- the removal of the exposed portion 15 formed inside each of the notches 11 and 11 recognizes the outline of the confirmation hole 14 provided for each of the nuts 11 and then the position of the center point. To recognize. Since the shape of the confirmation hole 14 is a circle, the centers of the holes match even if the circles are different in size.
- through hole 15 A is formed by removing first insulating film 12 A exposed from protruding portion 15.
- the insulating film 1 2 A can be removed using a laser. This laser removal is only possible with through holes 1 5
- the laser used here is preferably a carbon dioxide laser.
- etch etching with sodium permanganate or ammonium persulfate to remove this residue.
- the first conductive film is obtained by performing a plating process.
- a first connection portion 16 A that electrically connects 1 3 A and the second conductive film 1 3 B is formed. More specifically, the first connection ⁇ 16 A is formed by forming a metal film on the entire surface of the first conductive film 13 A including the through hole 15 A. This plating film is formed by an electroless plating and an electrolytic plating. Here, the first conductive layer including a through hole 15 A at least about 2 m in the electroless plating is used. Film 14 Formed on the entire surface of 4 A. As a result, the first conductive film 13 A and the second conductive film 1 3 B are in electrical conduction, so that electrolysis is performed again using both conductive films as electrodes, and about 20 / xm.
- the through hole 15 A is filled with Cu, and the first connecting portion 16 A is formed. It is also possible to selectively embed only the through hole 15 A by performing so-called filling fitting.
- Cu is used here for the film, but Au, Ag, Pd, etc. may be used. Further, by performing partial masking using a mask, the masking film may be formed only in the portion of the through hole 15 A.
- a metal film 17 made of a plating film is also formed on the inner wall of the confirmation hole 14.
- the metal film 17 is formed with a uniform film thickness on the inner wall of the confirmation hole 14. Therefore, the adhesion of the metal film 17 reduces the cross-sectional area of the confirmation hole 14, but maintains the circular cross-sectional shape.
- FIG. 2 (A) is a plan view of the laminated sheet 10 in this process.
- FIGS. 2 (B) to 2 (D) are cross-sectional views of the laminated sheet 10 at each step.
- the first and second wiring layers 1 and 2 are etched by etching the first and second conductive films 1 3 A and 1 3 B, respectively. 8 A and 1 8 B are formed. This is done by selectively etching each conductive film using an etching resist. In this process, when the etching resist is exposed, the position of the confirmation hole 14 is recognized, and the relative alignment between the laminated sheet 10 and the exposure mask is performed. Even if the size of the check hole 14 is small, it is circular, so its center point matches the previous alignment, and the center point is recognized and aligned.
- the recognition part 20 for recognition by X-rays is also formed by etching.
- This recognition unit may be any shape such as a square, a circle, or a cross as long as it can be recognized by the X-ray recognition device. The location may be anywhere, but is generally around the unit.
- a conductive film is brought into close contact with both main surfaces of the laminated sheet 10 via an insulating film.
- the third conductive film 13 C is laminated on the surface of the laminated sheet 10 via the second insulating film 12 B.
- a fourth conductive film 13 D is laminated on the back surface of the laminated sheet 10 via a third insulating film 12 C.
- These conductive films 13 can be laminated by a vacuum press.
- the confirmation hole 14 is also filled with resin.
- a pre-predder can be used as both insulating layers.
- a pre-preder is a fabric made of glass fiber or the like impregnated with an epoxy resin or the like.
- the guide hole 19 is drilled so as to penetrate the laminated sheet 10.
- guide holes 19 are drilled at four force points near the four corners of the laminated sheet 10. Drilling of guide hole 19 can be done by a combination of etching and laser, or by drilling.
- the alignment for specifying the position of the drill hole 19 is shown in Fig. 2 (C). This is performed by recognizing the position of the confirmation unit 20 shown in FIG.
- the confirmation portion 20 is provided corresponding to a location where the guide hole 19 is formed. Further, the confirmation unit 20 is formed of a part of the second wiring layer 18 A.
- the diameter of the guide hole 19 may be in the range of several tens of microns to 2 mm.
- the recognition unit 20 since the recognition unit 20 is covered with the upper third conductive film 13 C, its position cannot be recognized with visible light. From this, the position of the recognition unit 20 is recognized by irradiating X-rays, etc., and the drill is aligned and opened. In addition, the alignment in this process can be performed based on the outer shape if the outer dimensions of the laminated sheet 10 satisfy the specified accuracy.
- FIG. 3 (A) is a plan view of the laminated sheet 10 in this process
- Fig. 3 (B) to Fig. 3 (D) are sectional views of the laminated sheet 10 at each step. is there.
- the exposed portion 2 2 is formed by partially removing the third conductive film 13 C after recognizing the position of the circular guide hole 19. . Specifically, using the position of the guide hole 19 as a reference, etching is performed by patterning an etching mask on the surface of the third conductive film 13 C to form the exposed portion 2 2. . In this step, the same process is performed for the fourth conductive film 13 D, so that the exposed portion 2 2 is also formed on the back surface of the laminated sheet 10.
- the planar size of the exposed portion 20 is formed larger than the cross section of the confirmation hole 14. Specifically, the planar size of the confirmation hole 14 is a circle having a diameter of 0.15 mm, whereas the planar size of the exposed portion 20 is a circle of about 1.5 mm. . In this step, the exposed portion 22 is formed so that the peripheral portion of the confirmation hole 14 is exposed.
- the confirmation hole 14 can be placed in the exposed portion 2 2. It can be located in the area where is formed.
- the position of the recognition unit 21 is recognized, Expose the check hole 1 4 by one. Specifically, first, by recognizing the position of the recognition unit 21, the relative position between the laser irradiator (not shown) and the confirmation hole 14 is adjusted, and then laser irradiation is performed. . Laser irradiation may be performed only from the surface of the stacked sheet 10 or from both surfaces.
- the protective hole 2 4 formed continuously with the confirmation hole 14 forms a bowl shape.
- a shield-like protective portion 24 made of a conductive film is formed around the confirmation hole 14.
- the protective portion 24 is formed by the metal film 17 attached to the side surface of the confirmation hole 14 and the metal film 1k. Since the protective part 24 is made of metal, the protective part is protected even if the laser is irradiated to this region.
- Laser 2 3 irradiates an area wider than the area of the confirmation hole 14. As a result, even when the surface of the laminated sheet 10 other than the region where the confirmation hole 14 is formed is irradiated with the laser 23, the region is prevented from being damaged by the laser 23. I can do it.
- the side of the confirmation hole 14 is protected by a metal film 17 made of a metal film. Therefore, even if the laser 23 is irradiated on the side wall of the confirmation hole 14, the metal film 1
- each confirmation hole is irradiated with laser 23.
- each wiring layer passes through the insulating layer 1 2.
- a new connecting portion 1 6 connecting the two is formed. Specifically, the third conductive film 13 C and the second insulating film 12 B in the region corresponding to the second connection portion 16 B to be formed are partially removed and removed. By forming a plating film in the region, A second connecting portion 16 B is formed. In addition, a second connection portion 12 B that penetrates the third insulating film 12 C is also formed by the same method.
- an etching resist 25 is applied so as to cover the third conductive film 13 C. Then, the resist 25 is exposed using the exposure mask 3 1.
- the exposure mask 3 1 has a light shielding pattern 3 2 on the surface of a transparent substrate such as glass.
- the shape of the light-shielding pattern 3 2 has a pattern shape that is reverse to that of the second connection portion 16 B to be formed.
- a positive type resist in which a portion not irradiated with the light beam 30 remains is adopted as the register 25.
- etching is performed through resist 25 patterned by the above-described exposure process, etc., so that it corresponds to the region of the second connecting portion 16 mm.
- the third conductive film 13 C to be removed is removed.
- the fourth conductive film 13 D corresponding to the region of the second connection portion 16 ⁇ is also removed.
- the alignment of the exposure mask 3 1 is performed with reference to the central portion of the confirmation hole 14.
- an imaging means such as a CCD camera
- observation points K 3 Observe 3 observation points K 3 and identify their planar coordinates. Furthermore, from the coordinate values of these points, the coordinates of the center point C of the confirmation hole 14 are calculated by the geometry theorem. Since the planar shape of the confirmation hole 14 is circular, the coordinates of the center point C can be easily calculated. Also, exposure mask with the center point as the reference
- the exposure for partially removing the fourth conductive film 1 3 D is also performed in the confirmation hole 1.
- the center position of 4 is used as a reference. Therefore, using the same confirmation hole 14, the resist 25 applied on the front and back surfaces of the laminated sheet 10 is exposed, so that the relative position where both are exposed is made accurate. be able to.
- FIG. 5A is a plan view of the laminated sheet 10
- FIGS. 5B and 5C are cross-sectional views of the laminated sheet 10.
- confirmation holes 14 are formed in the vicinity of the four corners of each unit 11. Then, the position of the connecting portion 16 formed for each unit is specified using the confirmation hole 14 formed in the vicinity thereof. This is because the closer the confirmation hole 14 and the unit 11 are, the better the alignment accuracy.
- the through hole 15 A is formed by irradiating the laser 23 and partially evaporating the second insulating film.
- the upper surface of the first wiring layer 18 A is exposed at the bottom of the through hole 15 A.
- the alignment between the laser beam 23 and the laminated sheet 10 is performed with reference to the center point of the confirmation hole 14. Therefore, the relative position accuracy between the first wiring layer 18 A and the through hole 15 A is very good.
- the second connection portion 16 B made of a plating film is formed in the through hole 15 A by performing an electroless plating process and an electrolytic plating process. Is formed.
- the details of the measuring process in this step are the same as the method described with reference to Fig. 1 (F).
- a plating film is also formed on the inner wall of the confirmation hole 14. Confirmation, since the hole 14 has a cylindrical shape, the cross-section is reduced by forming a plating film on the inner wall, but the circular cross-sectional shape is maintained. Similarly, a plating film is also formed on the inner wall of the guide hole 19.
- the third conductive film 13 C and the fourth conductive film 13 D are etched to form new electrode and wiring patterns.
- the alignment of the exposure mask 3 1 and the laminated sheet 10 is performed by recognizing the center point of the confirmation hole 14.
- the recognition method of the confirmation hole 14 in this step is basically the same as the recognition method described with reference to FIG. 4 (C).
- the cross section of the confirmation hole 14 is reduced by the formation of a plating film on the inner wall of the confirmation hole 14.
- the cross section of the confirmation hole 14 before the plating film is formed on the inner wall is indicated by a dotted line indicated by V 1.
- the cross section of the confirmation hole 14 after the plating film is formed on the inner wall is shown by a solid line.
- first observation point K1 By observing (first observation point K1, second observation point K2, third observation point K3), it is possible to accurately measure the position of center point C.
- Fig. 7 (A) is a plan view of the laminated sheet 10.
- Fig. 7 (B) to Fig. 7 (D) are sectional views of the laminated sheet 10.
- the third wiring layer 18 C is formed on the surface of the laminated sheet 0 10 by the process of etching the upper S 7 and the laminated sheet 1 1 On the back side of 0, a fourth selfish wire layer 18 D is formed.
- the third wiring layer 13 C and the fourth wiring layer 18 D formed on the front and back surfaces of the laminated sheet 10 are covered.
- the resin forming the resist 26 may be filled into the confirmation hole 14 and the guide hole 19
- an opening 2 7 is provided in the resist 2 6.
- the opening 27 may be provided on both sides of the laminated sheet 10 or may be provided only on one side.
- the third wiring layer 18 C or the fourth wiring layer 18 D is exposed at the bottom of the opening 27.
- the opening 27 can be formed by recognizing the position of the confirmation portion 28 formed of the third wiring layer 18 C. Further, in this process, the opening 2 7 can be formed on the basis of the position of the confirmation hole 14.
- each unit 11 can be separated by dividing the laminated sheet 10 by the dividing line L 1 indicated by the alternate long and short dash line. This separation can be performed by cutting a laminated sheet 10 in a region where the wiring layer 18 is not formed using a laser. This makes it possible to separate the units 11 while minimizing the occurrence of vibration during cutting.
- a multilayer substrate having a multilayer wiring structure is completed.
- Each unit may be divided after the circuit element is fixed to the laminated sheet 10 through the opening portion 27. The separation can also be performed by processing using a router or pressing.
- a circuit element 3 3 B which is a semiconductor element, is mounted on the surface of the multilayer substrate 3 6 via a brazing material 3 4.
- the circuit element 3 3 B is mounted face-down, but it is also possible to adopt a fixed structure using metal wires.
- the circuit element 3 3 A is a passive element such as a chip resistor or a chip capacitor, and is fixed to the multilayer substrate 3 6 via a row material 3 4. If necessary, a lead or connector that is an external connection means may be mounted. Also, it is configured as a module substrate, and when it is not attached to a case, a packaged IC, CSP, or the like is mounted as a semiconductor element. When it is attached to a case, a bare chip may be mounted.
- a semiconductor package using a multilayer substrate will be described.
- the circuit element 3 3 described above is mounted on the surface of the multilayer substrate 3 6, and the circuit A sealing resin 35 is formed on the surface of the multilayer substrate 36 so that the path element 33 is sealed.
- the multilayer substrate 36 according to the present invention is extremely thin, a thin circuit device can be provided by applying such a multilayer substrate to the circuit device.
- the IC itself has a tendency to increase the number of pins to 500 pins and 100 pins, and the size of the external electrodes tends to be fine and narrow pitch. Therefore, if a multi-layer board is used, circuit modules that use ICs, discrete elements, chip capacitors, chip resistors, etc., so-called SIP, will be possible.
- the position of the confirmation portion provided in the first conductive film is recognized, and the second and subsequent conductive films are patterned. Therefore, even when a plurality of wiring layers are formed, the position is recognized by the first confirmation portion formed first, so that the relative positions of the layers can be made accurate. Furthermore, the connection part that connects the wiring layers is performed after recognizing the position of the confirmation part. Therefore, it is possible to improve the position accuracy of the location where the connection portion is formed.
- a confirmation sheet is provided so as to pass through a laminated sheet made of a conductive film adhered to both surfaces of the insulating film, and alignment is performed after the next process using this confirmation hole. Therefore, even when the wiring layers are laminated on both sides of the laminated sheet, the positioning accuracy of the wiring layers can be improved because all the wiring layers are aligned using the same confirmation hole. Furthermore, since the formation of the connection part, which is a part for electrical connection between the layers, is performed after the position of the confirmation hole is recognized, the position accuracy can be improved.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US10/598,469 US7661191B2 (en) | 2004-03-03 | 2005-02-24 | Multilayer substrate manufacturing method |
JP2006510700A JP4767163B2 (ja) | 2004-03-03 | 2005-02-24 | 多層基板の製造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2004-059267 | 2004-03-03 | ||
JP2004059267 | 2004-03-03 |
Publications (1)
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WO2005086553A1 true WO2005086553A1 (ja) | 2005-09-15 |
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PCT/JP2005/003562 WO2005086553A1 (ja) | 2004-03-03 | 2005-02-24 | 多層基板の製造方法 |
Country Status (6)
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US (1) | US7661191B2 (ja) |
JP (1) | JP4767163B2 (ja) |
KR (1) | KR100861137B1 (ja) |
CN (1) | CN100527921C (ja) |
TW (1) | TWI255672B (ja) |
WO (1) | WO2005086553A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007157774A (ja) * | 2005-11-30 | 2007-06-21 | Sanyo Electric Co Ltd | 多層基板の製造方法 |
JP2011171658A (ja) * | 2010-02-22 | 2011-09-01 | Sanyo Electric Co Ltd | 多層基板およびその製造方法 |
JP2011258909A (ja) * | 2010-06-10 | 2011-12-22 | Subtron Technology Co Ltd | 回路基板の製造方法 |
CN113710009A (zh) * | 2021-07-30 | 2021-11-26 | 昆山丘钛微电子科技股份有限公司 | 一种电路板及其制作方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI381921B (zh) * | 2009-12-08 | 2013-01-11 | Zhen Ding Technology Co Ltd | 衝型方法 |
US9018094B2 (en) | 2011-03-07 | 2015-04-28 | Invensas Corporation | Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates |
US8431431B2 (en) | 2011-07-12 | 2013-04-30 | Invensas Corporation | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers |
JP5595363B2 (ja) * | 2011-09-30 | 2014-09-24 | 富士フイルム株式会社 | 穴付き積層体の製造方法、穴付き積層体、多層基板の製造方法、下地層形成用組成物 |
CN107949150A (zh) * | 2017-11-22 | 2018-04-20 | 广州兴森快捷电路科技有限公司 | 印制电路板及印制电路板的制作方法 |
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JP2003007922A (ja) * | 2001-06-19 | 2003-01-10 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
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2005
- 2005-02-04 TW TW094103573A patent/TWI255672B/zh not_active IP Right Cessation
- 2005-02-24 WO PCT/JP2005/003562 patent/WO2005086553A1/ja active Application Filing
- 2005-02-24 KR KR1020067017201A patent/KR100861137B1/ko not_active IP Right Cessation
- 2005-02-24 CN CNB2005800063870A patent/CN100527921C/zh not_active Expired - Fee Related
- 2005-02-24 US US10/598,469 patent/US7661191B2/en not_active Expired - Fee Related
- 2005-02-24 JP JP2006510700A patent/JP4767163B2/ja not_active Expired - Fee Related
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JPH08153976A (ja) * | 1994-11-28 | 1996-06-11 | Matsushita Electric Works Ltd | 多層プリント配線板の製造方法 |
JP2002290044A (ja) * | 2001-03-27 | 2002-10-04 | Sharp Corp | 多層プリント配線板およびその製造方法 |
JP2002329964A (ja) * | 2001-04-27 | 2002-11-15 | Mitsubishi Paper Mills Ltd | 多層プリント配線板の製造方法 |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2007157774A (ja) * | 2005-11-30 | 2007-06-21 | Sanyo Electric Co Ltd | 多層基板の製造方法 |
JP2011171658A (ja) * | 2010-02-22 | 2011-09-01 | Sanyo Electric Co Ltd | 多層基板およびその製造方法 |
JP2011258909A (ja) * | 2010-06-10 | 2011-12-22 | Subtron Technology Co Ltd | 回路基板の製造方法 |
CN113710009A (zh) * | 2021-07-30 | 2021-11-26 | 昆山丘钛微电子科技股份有限公司 | 一种电路板及其制作方法 |
CN113710009B (zh) * | 2021-07-30 | 2023-04-11 | 昆山丘钛微电子科技股份有限公司 | 一种电路板及其制作方法 |
Also Published As
Publication number | Publication date |
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TWI255672B (en) | 2006-05-21 |
JP4767163B2 (ja) | 2011-09-07 |
KR20060116230A (ko) | 2006-11-14 |
JPWO2005086553A1 (ja) | 2008-01-24 |
KR100861137B1 (ko) | 2008-09-30 |
TW200534752A (en) | 2005-10-16 |
US20070281459A1 (en) | 2007-12-06 |
CN100527921C (zh) | 2009-08-12 |
CN1926931A (zh) | 2007-03-07 |
US7661191B2 (en) | 2010-02-16 |
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