US20070108610A1 - Embedded semiconductor device substrate and production method thereof - Google Patents
Embedded semiconductor device substrate and production method thereof Download PDFInfo
- Publication number
- US20070108610A1 US20070108610A1 US11/555,760 US55576006A US2007108610A1 US 20070108610 A1 US20070108610 A1 US 20070108610A1 US 55576006 A US55576006 A US 55576006A US 2007108610 A1 US2007108610 A1 US 2007108610A1
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- semiconductor device
- wiring pattern
- layer
- connection wiring
- substrate
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
Definitions
- the present invention relates to an embedded semiconductor device substrate having a semiconductor device buried in an insulating resin layer of a printed wiring board, and a method of producing the same.
- an embedded semiconductor device substrate having a semiconductor device buried inside of a printed wiring board has been proposed such as disclosed in Japanese Patent Application Laid-Open No. H09-321408.
- a semiconductor device having stud bumps formed thereon is mounted in a recessed portion formed beforehand on a printed wiring board, and an insulating layer is then formed so as to cover the semiconductor device.
- a semiconductor device 101 is mounted through an insulating epoxy resin 104 on a Cu foil 103 .
- a prepreg material 105 is disposed at such a location that an opening 105 a of the prepreg materiel 105 contains the semiconductor device 101 .
- the prepreg material 105 has approximately the same thickness as the thickness of the semiconductor device 101 , and the opening 105 a having a shape corresponding to the shape of the semiconductor device 101 is formed with a punching press.
- RCC Resin Coated Cupper
- the Cu foil 103 , prepreg material 105 , and RCC material 107 are disposed by stacking in this way, and are subjected to thermocompression bonding in a vacuum atmosphere as shown in FIG. 10C .
- a part of the Cu foil 103 a corresponding to an electrode portion 102 on the semiconductor device 101 is removed by ordinary etching to form a hole portion.
- a part of the epoxy resin 106 which is exposed via the hole portion is removed by a laser such as a CO 2 , YAG, or excimer laser to form an opening 108 , whereby the electrode portion 102 of the semiconductor device 101 is exposed therethrough.
- a laser such as a CO 2 , YAG, or excimer laser to form an opening 108 , whereby the electrode portion 102 of the semiconductor device 101 is exposed therethrough.
- FIG. 12E while a Cu layer 103 b is formed on the entire surface by plating, the opening 108 is filled with the Cu layer 103 b.
- a resist material is coated on the Cu layer 103 b, and a wiring pattern is formed in an exposure step through a mask and a development step, so that the embedded semiconductor device substrate having the semiconductor device 101 integrated therein as shown in FIG. 10F is obtained.
- the present invention has been accomplished in view of such problems, and it is an object of the present invention to provide an embedded semiconductor device substrate, which can increase the stability of electric connection to a wiring pattern, corresponding to the tendency of reduction in pitch of an electrode portion of a semiconductor device, and a method of producing the same.
- an embedded semiconductor device substrate having a semiconductor device integrated in an insulating resin layer, wherein a wiring pattern is formed on the insulating resin layer, a bump for connection is formed on an electrode portion on the semiconductor device, and the wiring pattern and the bump are connected through a connection wiring pattern provided on the wiring pattern and the bump.
- connection wiring pattern is thinner than the wiring pattern.
- the wiring has a multi-layer structure which is comprised of a plurality of materials.
- a method of producing an embedded semiconductor device substrate having a semiconductor device integrated therein comprising the steps of: forming a bump on an electrode portion on a surface of a semiconductor device; disposing the semiconductor device in an opening formed on a substrate; forming a conductive film on the semiconductor device and the substrate; integrating the semiconductor device and the substrate into a single body; patterning the conductive film to form wiring patterns and removing the conductive film on the semiconductor device to expose the bump; and forming a connection wiring pattern for connecting the electrode portion on the semiconductor device and the wiring pattern.
- connection wiring pattern is formed by forming a connection wiring layer on the insulating resin layer and the semiconductor device, patterning a resist material formed on the connection wiring layer by performing direct exposure with a laser, and then performing etching.
- connection wiring pattern is formed by forming a connection wiring layer on the insulating resin layer and the semiconductor device, performing direct writing of a resist material on the connection wiring layer, and then performing etching.
- connection wiring pattern is formed by performing direct writing of a conductive material on the insulating resin layer and the semiconductor device.
- FIG. 1 is a cross-sectional view of an embedded semiconductor device substrate according to Example 1 of the present invention.
- FIGS. 2A, 2B , and 2 C are cross-sectional views illustrating the steps of Production Method 1 of a semiconductor substrate according to Example 1 of the present invention.
- FIGS. 3A and 3B are cross-sectional views illustrating the steps of Production Method 1 of the semiconductor substrate according to Example 1 of the present invention.
- FIGS. 4A, 4B , and 4 C are cross-sectional views illustrating the steps of Production Method 1 of the semiconductor substrate according to Example 1 of the present invention.
- FIGS. 5A and 5B are plan views illustrating the arrangement of bumps of a semiconductor device and a connection wiring pattern according to Example 1 of the present invention.
- FIGS. 6A and 6B are plan views illustrating the arrangement of bumps of a semiconductor device and a connection wiring pattern according to Example 1 of the present invention.
- FIGS. 7A, 7B , and 7 C are cross-sectional views illustrating the steps of Production Method 2 of the semiconductor substrate according to Example 1 of the present invention.
- FIG. 8 is a cross-sectional view of an embedded semiconductor device substrate according to Example 2 of the present invention.
- FIGS. 9A and 9B are cross-sectional views illustrating the steps of a production method of a semiconductor substrate according to Example 2 of the present invention.
- FIGS. 10A, 10B , 10 C, 10 D, 10 E, and 10 F are cross-sectional views illustrating the steps of a production method of a semiconductor substrate according to a conventional example.
- FIG. 1 is a cross-sectional view of an embedded semiconductor device substrate 20 according to Example 1 of the present invention.
- reference numeral 1 denotes a semiconductor device
- reference numeral 2 denotes a bump formed on an electrode portion 11 on the semiconductor device 1 . Portions other than the electrode portion 11 on the semiconductor device 1 are covered with an insulating layer 13 .
- Reference numeral 12 denotes a resin film provided on the insulating layer 13 and having a thickness which is approximately the same as the height of the bump 2 .
- An insulating layer 4 is provided under the semiconductor device 1 .
- Reference numeral 5 denotes an insulating resin layer which forms a body of a printed wiring board.
- Reference symbol 3 a denotes a rear surface wiring pattern formed on a rear surface of the insulating resin layer 5
- reference symbol 7 a denotes a front surface wiring pattern formed on a front surface of the insulating resin layer 5
- Reference numeral 6 denotes an adhesive resin layer which seals the semiconductor device 1
- Reference symbol 10 a denotes a connection wiring pattern which connects the front surface wiring pattern 7 a on the insulating resin layer 5 and the bump 2 on the semiconductor device 1 .
- the connection wiring pattern 10 a connects the bump 2 and the front surface wiring pattern 7 a through a conductive protective layer 9 a.
- bumps 2 are formed on the electrode portion 11 on an upper surface of the semiconductor device 1 .
- a metal such as Au or Cu or a solder is used.
- a sphere or cylinder with a diameter of 20 to 30 ⁇ m is used.
- the upper surface of the semiconductor device 1 is covered with the insulating layer 13 , and only the electrode portion 11 is exposed to the upper surface.
- An epoxy resin or the like can be used as the insulating layer 13 .
- the resin film 12 having a thickness which is approximately the same as the height of the bump 2 is formed in an active area of the upper surface of the insulating layer 13 formed on the upper surface of the semiconductor device 1 .
- a polyimide film or the like can be used as the resin film 12 .
- the semiconductor device 1 having the bumps 2 and the resin film 12 formed on the surface thereof, and the rear surface wiring layer 3 are bonded through the insulating layer 4 .
- the insulating layer 4 there is used an epoxy resin film of 10 to 50 ⁇ m in thickness or the like.
- the rear surface wiring layer 3 it is possible to use a thin film such as of copper or aluminum of 10 to 35 ⁇ m in thickness.
- the semiconductor device 1 is bonded to the rear surface wiring layer 3 through the insulating layer 4 by heat curing.
- the insulating resin layer 5 which has approximately the same thickness as the thickness (50 to 150 ⁇ m) of the semiconductor device 1 , and has the opening 5 a with a shape corresponding to the shape of the semiconductor device 1 is disposed at such a location that the opening 5 a contains the semiconductor device 1 .
- a prepreg material containing glass cloth can be used as the insulating resin layer 5 .
- the semiconductor device 1 is disposed in the opening 5 a of the insulating resin layer 5 .
- an RCC material 8 having the adhesive resin layer 6 such as of an epoxy lined on the front surface wiring layer 7 is disposed on the insulating resin layer 5 and semiconductor device 1 .
- the front surface wiring layer 7 similarly to the rear surface wiring layer 3 , it is possible to use a thin film such as of copper or aluminum of 10 to 35 ⁇ m in thickness.
- the adhesive resin layer 6 an epoxy resin film with a thickness of 20 to 60 ⁇ m or the like can be used.
- the rear surface wiring layer 3 , the insulating resin layer 5 , and the RCC material 8 are simultaneously subjected to heat pressing at a temperature of 150 to 200° C. in a vacuum atmosphere. Thereby, the rear surface wiring layer 3 , the insulating resin layer 5 , and the RCC material 8 are integrated into a single substrate. Since the flowability of the adhesive resin layer 6 becomes high by the heating, the adhesive resin is flown to enter a gap between the semiconductor device 1 in the opening 5 a and the insulating resin layer 5 to fix the semiconductor device 1 securely. In addition, since the adhesive resin layer 6 on the bumps 2 is flown away by the bumps, the bumps 2 and the front surface wiring layer 7 come into contact with each other.
- the reason why the prepreg material 5 containing glass cloth is used is to prevent the flatness of the surface after the heat pressing from being impaired due to a difference in pressure between a portion where the semiconductor device 1 exists and a portion where no semiconductor device exists generated by the pressure applied during the heat pressing. Also from this viewpoint, it is preferable that the thickness of the glass cloth is equal to or somewhat larger than the sum of the thickness of the semiconductor device 1 and the height of the bump 2 .
- the above-mentioned resin film 12 prevents the front surface wiring layer 7 on the semiconductor device 1 from becoming uneven (non-flat) due to the bumps 2 provided on the semiconductor device 1 . Furthermore, when the bumps 2 deform to reduce their heights to the thickness of the resin film 12 , the resin film 12 also receives the applied pressure, so that it is possible to prevent the semiconductor device 1 from being damaged by concentration of the pressing pressure on the bumps 2 .
- the front surface wiring layer 7 and the rear surface wiring layer 3 of the integrated substrate are patterned to form the front surface wiring pattern 7 a and the rear surface wiring pattern 3 a. Thereby, the top portions of the bumps 2 are exposed.
- a protective layer 9 of 1 to 3 ⁇ m thick is formed on the front and the rear surfaces of the substrate by electroless plating.
- a metal such as Ni can be used as the protective layer 9 .
- the protective layer 9 plays roles of protecting the thus formed wiring pattern 7 a and of preventing diffusion between the bumps 2 of the semiconductor device 1 and the connection wiring pattern 10 a described later.
- connection wiring layer 10 of 1 to 3 ⁇ m thick is formed on the protective layer 9 by plating.
- a metal such as Cu can be used for the connection wiring layer 10 .
- a resist R 1 is formed in alignment with those positions, as shown in FIG. 4B .
- a negative resist layer is provided on the surface on the side of which the bumps 2 of the semiconductor device 1 are exposed, and the positions of the respective bumps 2 are detected with respect to the individual semiconductor devices.
- direct exposure with a light beam is performed to an area ranging from the region where the bump 2 is exposed to the electrode portion of the wiring pattern 7 a to be connected.
- the light beam any light may be used as long as it has a wavelength band in which the resist material is photosensitive, with UV light being generally used.
- the resist pattern R 1 can be formed, not only by forming once a resist film on the entire surface and then performing direct writing with a laser as described above, but also by performing direct writing of a resist itself. By performing direct writing of the resist itself, it becomes possible to reduce the production steps.
- the resist pattern R 1 is formed only on portions from the bumps 2 of the semiconductor device 1 to the electrode portion of the wiring pattern 7 a.
- the connection wiring pattern layer 10 is etched with a persulfuric acid solution, a portion of the connection wiring pattern layer (Cu layer) 10 on the protective layer (Ni layer) 9 other than the portion covered with the resist pattern R 1 is removed. Thereby, the connection wiring pattern layer 10 is patterned to provide the connection wiring pattern 10 a.
- the etching conditions are adjusted so that the etchant does not etch the protective layer (Ni layer) 9 .
- the protective layer (Ni layer) 9 is etched.
- a ferric chloride based solution is used as an etchant.
- the ferric chloride based solution also etches the connection wiring pattern 10 a, since the connection wiring pattern 10 a is far thicker than the protective layer 9 , the connection wiring pattern will not be disconnected.
- the connection wiring pattern 10 a is far thicker than the protective layer 9 , the connection wiring pattern will not be disconnected.
- the embedded semiconductor device substrate 20 can be obtained.
- FIGS. 5A, 5B , 6 A and 6 B are plan views of the embedded semiconductor device substrate 20 showing the connection wiring pattern 10 a which connects the bumps 2 and the wiring pattern 7 a.
- FIGS. 5A and 6A are views showing the state before forming the connection wiring pattern 10 a
- FIGS. 5B and 6B are views showing the state after forming the connection wiring pattern 10 a.
- the semiconductor device 1 is disposed obliquely.
- FIGS. 7A to 7 C a second method of producing the embedded semiconductor device substrate 20 shown in FIG. 1 will be explained with reference to FIGS. 7A to 7 C.
- a positive resist R 2 is used instead of the negative resist R 1 used in the first production method.
- the steps of the first production method described with reference to FIGS. 2A to 3 B are similarly carried out as such, and then the steps shown in FIGS. 7A to 7 C are carried out instead of the steps shown in FIGS. 4A to 4 C.
- a positive resist R 2 is formed so that only portions of the protective layer (Ni layer) 9 in which the connection wiring pattern 10 a is to be formed is exposed. Then, electroplating is performed by using the protective layer 9 as a common electrode layer to form the connection wiring pattern (Cu layer) 10 a.
- the thickness of the connection wiring pattern (Cu layer) 10 a is preferably 5 to 15 ⁇ m.
- the resist pattern R 2 is stripped, and as shown in FIG.7C , the protective layer 9 is etched. At that time, although the connection wiring pattern 10 a is also etched, since the film thickness thereof is larger than that of the protective layer 9 , the film thickness becomes about 3 to 10 ⁇ m when etching is completed.
- the resist pattern R 2 can be formed also by performing direct writing of a resist itself as is the case with the above-mentioned resist pattern R 1 . By performing direct writing of the resist itself, it becomes possible to reduce the production steps.
- FIG. 8 is a cross-sectional view of an embedded semiconductor device substrate 30 according to Example 2 of the present invention.
- this example has such a structure that there is no protective layer 9 .
- the material of the bumps 2 of the semiconductor device 1 is Ni.
- the protective layer 9 which functions as a diffusion barrier layer between the bumps 2 and the wiring pattern 7 a.
- the elements which are the same as those shown in FIG. 1 are identified by like reference numerals or symbols.
- FIGS. 9A and 9B the steps of the first production method described with reference to FIGS. 2A to 3 B are similarly carried out as such, and then the steps shown in FIGS. 9A and 9B are carried out instead of the steps shown in FIGS. 4A to 4 C.
- connection wiring pattern layer (Cu layer) 10 is formed on the entire surface in a thickness of 3 to 10 ⁇ m by electroless plating. Then, the connection wiring pattern layer 10 is etched using a negative resist pattern R 3 to form the connection wiring pattern 10 a which is a very thin pattern as shown in FIG. 9B .
- the bumps 2 are made of Ni and the connection wiring pattern 10 a is made of Cu
- the bumps 2 may be made of Cu and the connection wiring pattern 10 a may be made of Ni.
- the bumps 2 may be made of Ni and the connection wiring pattern 10 a may also be made of Ni, or the bumps 2 may be made of Cu and the connection wiring pattern 10 a may also be made of Cu.
- the resist pattern R 3 can be formed also by performing direct writing of a resist itself as is the case with the above-mentioned resist pattern R 1 .
- direct writing of the resist itself it becomes possible to reduce the production steps.
- connection wiring pattern 10 a instead of the resist.
- direct writing of the connection wiring pattern 10 a instead of the resist.
- connection wiring pattern is formed in a separate step after burying the semiconductor device into the printed wiring board.
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Abstract
An embedded semiconductor device substrate having a semiconductor device integrated therein is formed by disposing a semiconductor device in an opening provided on an insulating resin, and sandwiching the semiconductor device and the insulating resin with a front surface wiring layer and a rear surface wiring layer and performing heat pressing. Connection between bumps of the semiconductor device and the front surface wiring layer is made with a connection wiring pattern. The connection wiring pattern is formed by patterning a resist film by direct exposure thereof with a light beam, and then performing etching. Thereby, it becomes possible to absorb a mounting error of a semiconductor device to a printed wiring board and a positional error of electrodes between semiconductor devices accompanying the tendency of reduction of the pitch of a semiconductor device, and to perform electric connection with a wiring pattern securely.
Description
- 1. Field of the Invention
- The present invention relates to an embedded semiconductor device substrate having a semiconductor device buried in an insulating resin layer of a printed wiring board, and a method of producing the same.
- 2. Description of the Related Art
- In recent years, the semiconductor package having a semiconductor device mounted therein has been continuously reduced in size and weight. Therefore, there has been increasing adopted a structure in which an electrode portion of a semiconductor package is formed into an area array, such as BGA (Ball Grid Array) and CSP (Chip Scale Package).
- Furthermore, not only a two-dimensional size reduction such as the BGA and CSP, but also a multi chip package in which a plurality of semiconductor devices are stacked in a single package has been proposed such as disclosed in Japanese Patent Application Laid-Open No. H11-3970.
- On the other hand, in addition to such size reduction of semiconductor packages, an embedded semiconductor device substrate having a semiconductor device buried inside of a printed wiring board has been proposed such as disclosed in Japanese Patent Application Laid-Open No. H09-321408. In the embedded semiconductor device substrate disclosed in Japanese Patent Application Laid-Open No. H09-321408, a semiconductor device having stud bumps formed thereon is mounted in a recessed portion formed beforehand on a printed wiring board, and an insulating layer is then formed so as to cover the semiconductor device.
- However, in the embedded semiconductor device substrate described in Japanese Patent Application Laid-Open No. H09-321408, since a routering is necessary for forming a recessed portion in a printed wiring board, which increases the processing time remarkably. In addition, in order to bury a semiconductor device, it is necessary to form a holding surface for holding the semiconductor device at a bottom of the recessed portion, and an insulating layer is needed for the holding surface. In consequence, the thickness of the embedded semiconductor device substrate having the semiconductor device varied therein becomes very large, which makes the size reduction difficult.
- So, there has been proposed a method which does not form a recessed portion beforehand in a printed wiring board but buries a semiconductor device during production of a printed wiring board to thereby produce an embedded semiconductor device substrate, in Japanese Patent Application Laid-Open No. 2004-335641. The production method disclosed therein will be explained with reference to
FIGS. 10A to 10F. - First, as shown in
FIG. 10A , asemiconductor device 101 is mounted through aninsulating epoxy resin 104 on aCu foil 103. Next, as shown inFIG. 10B , aprepreg material 105 is disposed at such a location that anopening 105 a of theprepreg materiel 105 contains thesemiconductor device 101. Theprepreg material 105 has approximately the same thickness as the thickness of thesemiconductor device 101, and theopening 105 a having a shape corresponding to the shape of thesemiconductor device 101 is formed with a punching press. In addition, on theprepreg material 105, there is put an RCC (Resin Coated Cupper)material 107 having anepoxy resin 106 as an insulating resin coated on aCu foil 103 a. TheCu foil 103,prepreg material 105, and RCC material 107 (epoxy resin 106/cupper foil 103 a) are disposed by stacking in this way, and are subjected to thermocompression bonding in a vacuum atmosphere as shown inFIG. 10C . - Next, as shown in
FIG. 1D , a part of theCu foil 103a corresponding to anelectrode portion 102 on thesemiconductor device 101 is removed by ordinary etching to form a hole portion. Then, a part of theepoxy resin 106 which is exposed via the hole portion is removed by a laser such as a CO2, YAG, or excimer laser to form anopening 108, whereby theelectrode portion 102 of thesemiconductor device 101 is exposed therethrough. Next, as shown inFIG. 12E , while aCu layer 103 b is formed on the entire surface by plating, theopening 108 is filled with theCu layer 103 b. - Subsequently, a resist material is coated on the
Cu layer 103 b, and a wiring pattern is formed in an exposure step through a mask and a development step, so that the embedded semiconductor device substrate having thesemiconductor device 101 integrated therein as shown inFIG. 10F is obtained. - In the embedded semiconductor device substrate disclosed in Japanese Patent Application Laid-Open No. 2004-335641 above, by forming an opening accurately by use of a laser, electrodes of a semiconductor device are exposed outside. Furthermore, by etching a Cu layer formed on a printed wiring board by use of a mask, a wiring pattern connected to the electrodes is formed. Hence, there is required an etching accuracy of such an extent as to surely connect the electrodes of the semiconductor device and the wiring pattern on the printed wiring board to each other.
- On the other hand, since a large number of semiconductor devices are produced from a single semiconductor wafer, there are differences between individual semiconductor devices obtained therefrom, and there are positional errors between the individual semiconductor devices also with regard to electrode positions. Furthermore, there will be necessarily generated a mounting error within a predetermined range in the mounting position of a semiconductor device to a printed wiring board. Therefore, there is generated a displacement with respect to a design position between the patterning position of a wiring pattern, and the position of an electrode of a semiconductor device. Generally, in prospect of this displacement, the patterning using a mask is made so as to provide a pattern shape with a predetermined amount of margin.
- Nevertheless, as the pitch of electrodes of a semiconductor device is reduced, it becomes impossible to take a sufficient margin to avoid interference with an adjacent wiring pattern. That is, it becomes difficult to allow the above described errors when mounting semiconductor devices to a printed wiring board and positional errors of electrodes between individual semiconductor devices, by means of a margin of a pattern shape. Thereby, the electrodes of the semiconductor devices and the wiring on the printed wiring board will not be connected. Such a situation becomes significant as the pitch between electrodes of a semiconductor device is reduced, and it is believed that it will become a more serious problem in the future.
- Therefore, the present invention has been accomplished in view of such problems, and it is an object of the present invention to provide an embedded semiconductor device substrate, which can increase the stability of electric connection to a wiring pattern, corresponding to the tendency of reduction in pitch of an electrode portion of a semiconductor device, and a method of producing the same.
- According to a first aspect of the present invention, there is provided an embedded semiconductor device substrate having a semiconductor device integrated in an insulating resin layer, wherein a wiring pattern is formed on the insulating resin layer, a bump for connection is formed on an electrode portion on the semiconductor device, and the wiring pattern and the bump are connected through a connection wiring pattern provided on the wiring pattern and the bump.
- In the present invention, it is preferred that the connection wiring pattern is thinner than the wiring pattern.
- Further, it is preferred that the wiring has a multi-layer structure which is comprised of a plurality of materials.
- According to a second aspect of the present invention, there is provided a method of producing an embedded semiconductor device substrate having a semiconductor device integrated therein, comprising the steps of: forming a bump on an electrode portion on a surface of a semiconductor device; disposing the semiconductor device in an opening formed on a substrate; forming a conductive film on the semiconductor device and the substrate; integrating the semiconductor device and the substrate into a single body; patterning the conductive film to form wiring patterns and removing the conductive film on the semiconductor device to expose the bump; and forming a connection wiring pattern for connecting the electrode portion on the semiconductor device and the wiring pattern.
- In the present invention, it is preferred that the connection wiring pattern is formed by forming a connection wiring layer on the insulating resin layer and the semiconductor device, patterning a resist material formed on the connection wiring layer by performing direct exposure with a laser, and then performing etching.
- Further, it is preferred that the connection wiring pattern is formed by forming a connection wiring layer on the insulating resin layer and the semiconductor device, performing direct writing of a resist material on the connection wiring layer, and then performing etching.
- Moreover, it is preferred that the connection wiring pattern is formed by performing direct writing of a conductive material on the insulating resin layer and the semiconductor device.
- The above and other objects of the Invention will become more apparent from the following drawings taken in conjunction with the accompanying drawings.
-
FIG. 1 is a cross-sectional view of an embedded semiconductor device substrate according to Example 1 of the present invention. -
FIGS. 2A, 2B , and 2C are cross-sectional views illustrating the steps ofProduction Method 1 of a semiconductor substrate according to Example 1 of the present invention. -
FIGS. 3A and 3B are cross-sectional views illustrating the steps ofProduction Method 1 of the semiconductor substrate according to Example 1 of the present invention. -
FIGS. 4A, 4B , and 4C are cross-sectional views illustrating the steps ofProduction Method 1 of the semiconductor substrate according to Example 1 of the present invention. -
FIGS. 5A and 5B are plan views illustrating the arrangement of bumps of a semiconductor device and a connection wiring pattern according to Example 1 of the present invention. -
FIGS. 6A and 6B are plan views illustrating the arrangement of bumps of a semiconductor device and a connection wiring pattern according to Example 1 of the present invention. -
FIGS. 7A, 7B , and 7C are cross-sectional views illustrating the steps ofProduction Method 2 of the semiconductor substrate according to Example 1 of the present invention. -
FIG. 8 is a cross-sectional view of an embedded semiconductor device substrate according to Example 2 of the present invention. -
FIGS. 9A and 9B are cross-sectional views illustrating the steps of a production method of a semiconductor substrate according to Example 2 of the present invention. -
FIGS. 10A, 10B , 10C, 10D, 10E, and 10F are cross-sectional views illustrating the steps of a production method of a semiconductor substrate according to a conventional example. - Embodiments of the present invention will be explained.
-
FIG. 1 is a cross-sectional view of an embeddedsemiconductor device substrate 20 according to Example 1 of the present invention. In the figure,reference numeral 1 denotes a semiconductor device, andreference numeral 2 denotes a bump formed on anelectrode portion 11 on thesemiconductor device 1. Portions other than theelectrode portion 11 on thesemiconductor device 1 are covered with an insulatinglayer 13.Reference numeral 12 denotes a resin film provided on the insulatinglayer 13 and having a thickness which is approximately the same as the height of thebump 2. An insulatinglayer 4 is provided under thesemiconductor device 1.Reference numeral 5 denotes an insulating resin layer which forms a body of a printed wiring board.Reference symbol 3 a denotes a rear surface wiring pattern formed on a rear surface of the insulatingresin layer 5, andreference symbol 7 a denotes a front surface wiring pattern formed on a front surface of the insulatingresin layer 5.Reference numeral 6 denotes an adhesive resin layer which seals thesemiconductor device 1.Reference symbol 10 a denotes a connection wiring pattern which connects the frontsurface wiring pattern 7 a on the insulatingresin layer 5 and thebump 2 on thesemiconductor device 1. Theconnection wiring pattern 10 a connects thebump 2 and the frontsurface wiring pattern 7 a through a conductiveprotective layer 9 a. - (Production Method 1)
- Next, a first method of producing the embedded
semiconductor device substrate 20 shown inFIG. 1 will be explained with reference toFIGS. 2A to 4C. Firstly, as shown inFIG. 2A , bumps 2 are formed on theelectrode portion 11 on an upper surface of thesemiconductor device 1. For thebumps 2, a metal such as Au or Cu or a solder is used. As to the shape thereof, a sphere or cylinder with a diameter of 20 to 30 μm is used. The upper surface of thesemiconductor device 1 is covered with the insulatinglayer 13, and only theelectrode portion 11 is exposed to the upper surface. An epoxy resin or the like can be used as the insulatinglayer 13. Further, theresin film 12 having a thickness which is approximately the same as the height of thebump 2 is formed in an active area of the upper surface of the insulatinglayer 13 formed on the upper surface of thesemiconductor device 1. A polyimide film or the like can be used as theresin film 12. - Next, the
semiconductor device 1 having thebumps 2 and theresin film 12 formed on the surface thereof, and the rearsurface wiring layer 3 are bonded through the insulatinglayer 4. As the insulatinglayer 4, there is used an epoxy resin film of 10 to 50 μm in thickness or the like. As the rearsurface wiring layer 3, it is possible to use a thin film such as of copper or aluminum of 10 to 35 μm in thickness. Thesemiconductor device 1 is bonded to the rearsurface wiring layer 3 through the insulatinglayer 4 by heat curing. - Subsequently, as shown in
FIG. 2B , the insulatingresin layer 5 which has approximately the same thickness as the thickness (50 to 150 μm) of thesemiconductor device 1, and has theopening 5 a with a shape corresponding to the shape of thesemiconductor device 1 is disposed at such a location that theopening 5 a contains thesemiconductor device 1. As the insulatingresin layer 5, a prepreg material containing glass cloth can be used. Thesemiconductor device 1 is disposed in theopening 5 a of the insulatingresin layer 5. - In addition, on the insulating
resin layer 5 andsemiconductor device 1, anRCC material 8 having theadhesive resin layer 6 such as of an epoxy lined on the frontsurface wiring layer 7 is disposed. As the frontsurface wiring layer 7, similarly to the rearsurface wiring layer 3, it is possible to use a thin film such as of copper or aluminum of 10 to 35 μm in thickness. As theadhesive resin layer 6, an epoxy resin film with a thickness of 20 to 60 μm or the like can be used. - Next, as shown in
FIG. 2C , the rearsurface wiring layer 3, the insulatingresin layer 5, and theRCC material 8 are simultaneously subjected to heat pressing at a temperature of 150 to 200° C. in a vacuum atmosphere. Thereby, the rearsurface wiring layer 3, the insulatingresin layer 5, and theRCC material 8 are integrated into a single substrate. Since the flowability of theadhesive resin layer 6 becomes high by the heating, the adhesive resin is flown to enter a gap between thesemiconductor device 1 in theopening 5 a and the insulatingresin layer 5 to fix thesemiconductor device 1 securely. In addition, since theadhesive resin layer 6 on thebumps 2 is flown away by the bumps, thebumps 2 and the frontsurface wiring layer 7 come into contact with each other. - At this time, the reason why the
prepreg material 5 containing glass cloth is used is to prevent the flatness of the surface after the heat pressing from being impaired due to a difference in pressure between a portion where thesemiconductor device 1 exists and a portion where no semiconductor device exists generated by the pressure applied during the heat pressing. Also from this viewpoint, it is preferable that the thickness of the glass cloth is equal to or somewhat larger than the sum of the thickness of thesemiconductor device 1 and the height of thebump 2. - In addition, the above-mentioned
resin film 12 prevents the frontsurface wiring layer 7 on thesemiconductor device 1 from becoming uneven (non-flat) due to thebumps 2 provided on thesemiconductor device 1. Furthermore, when thebumps 2 deform to reduce their heights to the thickness of theresin film 12, theresin film 12 also receives the applied pressure, so that it is possible to prevent thesemiconductor device 1 from being damaged by concentration of the pressing pressure on thebumps 2. - Next, as shown in
FIG. 3A , the frontsurface wiring layer 7 and the rearsurface wiring layer 3 of the integrated substrate are patterned to form the frontsurface wiring pattern 7 a and the rearsurface wiring pattern 3 a. Thereby, the top portions of thebumps 2 are exposed. - Subsequently, as shown in
FIG. 3B , aprotective layer 9 of 1 to 3 μm thick is formed on the front and the rear surfaces of the substrate by electroless plating. As theprotective layer 9, a metal such as Ni can be used. Theprotective layer 9 plays roles of protecting the thus formedwiring pattern 7 a and of preventing diffusion between thebumps 2 of thesemiconductor device 1 and theconnection wiring pattern 10 a described later. - Next, as shown in
FIG. 4A , aconnection wiring layer 10 of 1 to 3 μm thick is formed on theprotective layer 9 by plating. A metal such as Cu can be used for theconnection wiring layer 10. - Subsequently, the positions of the
bumps 2 and the frontsurface wiring pattern 7 a are confirmed, and a resist R1 is formed in alignment with those positions, as shown inFIG. 4B . Specifically, a negative resist layer is provided on the surface on the side of which thebumps 2 of thesemiconductor device 1 are exposed, and the positions of therespective bumps 2 are detected with respect to the individual semiconductor devices. After that, direct exposure with a light beam is performed to an area ranging from the region where thebump 2 is exposed to the electrode portion of thewiring pattern 7 a to be connected. As the light beam, any light may be used as long as it has a wavelength band in which the resist material is photosensitive, with UV light being generally used. In addition, as a method of performing direct exposure, it is possible to provide an X-Y driving unit on a beam head, or to provide an X-Y driving unit on a stage for holding the substrate and perform driving as programmed. - Incidentally, the resist pattern R1 can be formed, not only by forming once a resist film on the entire surface and then performing direct writing with a laser as described above, but also by performing direct writing of a resist itself. By performing direct writing of the resist itself, it becomes possible to reduce the production steps.
- Next, by performing exposure followed by development for the
respective semiconductor devices 1, the resist pattern R1 is formed only on portions from thebumps 2 of thesemiconductor device 1 to the electrode portion of thewiring pattern 7 a. In this state, when the connectionwiring pattern layer 10 is etched with a persulfuric acid solution, a portion of the connection wiring pattern layer (Cu layer) 10 on the protective layer (Ni layer) 9 other than the portion covered with the resist pattern R1 is removed. Thereby, the connectionwiring pattern layer 10 is patterned to provide theconnection wiring pattern 10 a. At this time, the etching conditions are adjusted so that the etchant does not etch the protective layer (Ni layer) 9. - Subsequently, in the state in which the resist pattern R1 remains, the protective layer (Ni layer) 9 is etched. At this time, a ferric chloride based solution is used as an etchant. Although the ferric chloride based solution also etches the
connection wiring pattern 10 a, since theconnection wiring pattern 10a is far thicker than theprotective layer 9, the connection wiring pattern will not be disconnected. In particular, in the case of a very thinconnection wiring pattern 10 a, it is possible to perform stable pattern formation since the Cu and the resist exist on the Ni. - Then, by stripping the resist pattern R1, as shown in
FIG. 4C , the embeddedsemiconductor device substrate 20 can be obtained. -
FIGS. 5A, 5B , 6A and 6B are plan views of the embeddedsemiconductor device substrate 20 showing theconnection wiring pattern 10 a which connects thebumps 2 and thewiring pattern 7 a.FIGS. 5A and 6A are views showing the state before forming theconnection wiring pattern 10 a, andFIGS. 5B and 6B are views showing the state after forming theconnection wiring pattern 10 a. With respect toFIGS. 5A and 5B , inFIGS. 6A and 6B thesemiconductor device 1 is disposed obliquely. In this example, in the step of forming the resist R1 shown inFIG. 4B mentioned above, writing of the resist with a beam is performed while positions ranging from thebumps 2 of thesemiconductor device 1 to the connecting portions of thewiring pattern 7 a are corrected automatically. Hence, even if the positional relationship between thebumps 3 of thesemiconductor device 1 and the frontsurface wiring pattern 7 a deviates somewhat from the adequate one, it is possible to attain always stable connection. - According to the present invention, a process of forming the
wiring pattern 7 a and a process of forming theconnection wiring pattern 10 a are separated from each other. Thereby, it becomes possible to form the resist, when forming theconnection wiring pattern 10 a, so as to be in alignment with the positions of the electrodes of the individual semiconductor devices. Thereby, even if the positions of the semiconductor devices are deviated from the adequate ones, since it is possible to attend thereto by correcting the writing program, it is possible to form easily such an extremely fineconnection wiring pattern 10 a having dimensions of wiring width/space=10 μm/10 μm to 20 μm/20 μm. - (Production Method 2)
- Next, a second method of producing the embedded
semiconductor device substrate 20 shown inFIG. 1 will be explained with reference toFIGS. 7A to 7C. In the second production method, a positive resist R2 is used instead of the negative resist R1 used in the first production method. In the second production method, the steps of the first production method described with reference toFIGS. 2A to 3B are similarly carried out as such, and then the steps shown inFIGS. 7A to 7C are carried out instead of the steps shown inFIGS. 4A to 4C. - As shown in
FIG. 7A , a positive resist R2 is formed so that only portions of the protective layer (Ni layer) 9 in which theconnection wiring pattern 10 a is to be formed is exposed. Then, electroplating is performed by using theprotective layer 9 as a common electrode layer to form the connection wiring pattern (Cu layer) 10 a. The thickness of the connection wiring pattern (Cu layer) 10 a is preferably 5 to 15 μm. - Next, as shown in
FIG. 7B , the resist pattern R2 is stripped, and as shown inFIG.7C , theprotective layer 9 is etched. At that time, although theconnection wiring pattern 10 a is also etched, since the film thickness thereof is larger than that of theprotective layer 9, the film thickness becomes about 3 to 10 μm when etching is completed. Incidentally, the resist pattern R2 can be formed also by performing direct writing of a resist itself as is the case with the above-mentioned resist pattern R1. By performing direct writing of the resist itself, it becomes possible to reduce the production steps. -
FIG. 8 is a cross-sectional view of an embeddedsemiconductor device substrate 30 according to Example 2 of the present invention. In comparison with the embeddedsemiconductor device substrate 20 of Example 1 shown inFIG. 1 , this example has such a structure that there is noprotective layer 9. In this example, the material of thebumps 2 of thesemiconductor device 1 is Ni. In this case, it is not necessary to provide theprotective layer 9 which functions as a diffusion barrier layer between thebumps 2 and thewiring pattern 7 a. Incidentally, inFIG. 8 , the elements which are the same as those shown inFIG. 1 are identified by like reference numerals or symbols. - Next, the method of producing the embedded
semiconductor device substrate 30 shown inFIG. 8 will be explained with reference toFIGS. 9A and 9B . In the production method of this example, the steps of the first production method described with reference toFIGS. 2A to 3B are similarly carried out as such, and then the steps shown inFIGS. 9A and 9B are carried out instead of the steps shown inFIGS. 4A to 4C. - As shown in
FIG. 9A , after forming thewiring patterns wiring pattern layer 10 is etched using a negative resist pattern R3 to form theconnection wiring pattern 10 a which is a very thin pattern as shown inFIG. 9B . - Incidentally, although in this example the
bumps 2 are made of Ni and theconnection wiring pattern 10 a is made of Cu, thebumps 2 may be made of Cu and theconnection wiring pattern 10 a may be made of Ni. Furthermore, thebumps 2 may be made of Ni and theconnection wiring pattern 10 a may also be made of Ni, or thebumps 2 may be made of Cu and theconnection wiring pattern 10 a may also be made of Cu. - Incidentally, the resist pattern R3 can be formed also by performing direct writing of a resist itself as is the case with the above-mentioned resist pattern R1. By performing direct writing of the resist itself, it becomes possible to reduce the production steps.
- Furthermore, it is also possible to perform direct writing of the
connection wiring pattern 10 a instead of the resist. Thereby, it is possible to omit exposure and development process after writing of a resist. - According to the present invention, in an embedded semiconductor device substrate, electrodes of a semiconductor device and a wiring pattern on a printed wiring board are connected by means of a connection wiring pattern. In addition, the connection wiring pattern is formed in a separate step after burying the semiconductor device into the printed wiring board. Thereby, it becomes possible to form the connection wiring pattern corresponding to positions of the electrodes of the semiconductor device and the patterned wiring on the printed wiring board. In addition, it becomes possible to perform electric connection with a wiring pattern securely even when the electrode portion of the semiconductor device has a narrow pitch.
- Furthermore, when a semiconductor device is buried inside a substrate and a wiring pattern is formed, it becomes possible to perform post-process tests such as a burn-in test easily, so that non-defective products can be selected. Hence, even when further combined with other components or devices, it is possible to maintain a high yield and to reduce the production cost.
- Moreover, since the degree of freedom of wiring design is high, it is possible to address combination with various semiconductor devices or electric circuit components flexibly. Hence, it becomes possible to provide higher-performance, small-size, and low-cost semiconductor products.
- While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
- This application claims priority from Japanese Patent Application Nos. 2005-318962 filed on Nov. 2, 2005 and 2006-291272 filed on Oct. 26, 2006, which are hereby incorporated by reference herein.
Claims (8)
1. An embedded semiconductor device substrate having a semiconductor device integrated in an insulating resin layer, wherein a wiring pattern is formed on the insulating resin layer, a bump for connection is formed on an electrode portion on the semiconductor device, and the wiring pattern and the bump are connected through a connection wiring pattern provided on the wiring pattern and the bump.
2. The embedded semiconductor device substrate according to claim 1 , wherein the connection wiring pattern is thinner than the wiring pattern.
3. The embedded semiconductor device substrate according to claim 1 , wherein the wiring has a multi-layer structure which is comprised of a plurality of materials.
4. A method of producing an embedded semiconductor device substrate having a semiconductor device integrated therein, comprising the steps of:
forming a bump on an electrode portion on a surface of a semiconductor device;
disposing the semiconductor device in an opening formed on an substrate;
forming a conductive film on the semiconductor device and the substrate;
integrating the semiconductor device and the substrate into a single body;
patterning the conductive film to form wiring patterns and removing the conductive film on the semiconductor device to expose the bump; and
forming a connection wiring pattern for connecting the electrode portion on the semiconductor device and the wiring pattern.
5. The method according to claim 4 , wherein the connection wiring pattern is formed by forming a connection wiring layer on the substrate and the semiconductor device, patterning a resist material formed on the connection wiring layer by performing direct exposure with a laser, and then performing etching by using the resist material as an etching mask.
6. The method according to claim 4 , wherein the connection wiring pattern is formed by forming an under layer of a connection wiring layer on the substrate and the semiconductor device, patterning a resist material formed on the connection wiring layer by performing direct exposure with a laser, and then performing plating by using the resist material as a plating mask.
7. The method according to claim 4 , wherein the connection wiring pattern is formed by forming a connection wiring layer on the insulating resin layer and the semiconductor device, performing direct writing of a resist material on the connection wiring layer, and then performing etching.
8. The method according to claim 4 , wherein the connection wiring pattern is formed by performing direct writing of a conductive material on the insulating resin layer and the semiconductor device.
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US13/748,657 US8609539B2 (en) | 2005-11-02 | 2013-01-24 | Embedded semiconductor device substrate and production method thereof |
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JP2006291272A JP5164362B2 (en) | 2005-11-02 | 2006-10-26 | Semiconductor embedded substrate and manufacturing method thereof |
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Publication number | Priority date | Publication date | Assignee | Title |
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US20080273314A1 (en) * | 2007-05-04 | 2008-11-06 | Samsung Electronics Co., Ltd. | PCB having embedded IC and method for manufacturing the same |
WO2009124246A1 (en) * | 2008-04-04 | 2009-10-08 | The Charles Stark Draper Laboratory, Inc. | Interposers, electronic modules, and methods for forming the same |
US20090250823A1 (en) * | 2008-04-04 | 2009-10-08 | Racz Livia M | Electronic Modules and Methods for Forming the Same |
EP2148366A1 (en) * | 2008-07-21 | 2010-01-27 | Commissariat a L'Energie Atomique | Device having plurality of integrated circuits in a matrix |
US20100078204A1 (en) * | 2008-09-29 | 2010-04-01 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board including electronic component embedded therein and method of manufacturing the same |
US20100195299A1 (en) * | 2007-06-07 | 2010-08-05 | Commissariat A L'energie Atomique | Integrated multicomponent device in a semiconducting die |
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US10618206B2 (en) | 2017-02-27 | 2020-04-14 | Omron Corporation | Resin-molded electronic device with disconnect prevention |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101113889B1 (en) | 2007-12-04 | 2012-02-29 | 삼성테크윈 주식회사 | Electronic chip embedded circuit board and method of manufacturing the same |
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Citations (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3903590A (en) * | 1973-03-10 | 1975-09-09 | Tokyo Shibaura Electric Co | Multiple chip integrated circuits and method of manufacturing the same |
US4754319A (en) * | 1984-05-30 | 1988-06-28 | Kabushiki Kaisha Toshiba | IC card and method for manufacturing the same |
US4997791A (en) * | 1986-05-20 | 1991-03-05 | Kabushiki Kaisha Toshiba | IC card and method of manufacturing the same |
US5548091A (en) * | 1993-10-26 | 1996-08-20 | Tessera, Inc. | Semiconductor chip connection components with adhesives and methods for bonding to the chip |
US6239983B1 (en) * | 1995-10-13 | 2001-05-29 | Meiko Electronics Co., Ltd. | Circuit board, manufacturing method therefor, and bump-type contact head and semiconductor component packaging module using the circuit board |
US20020041021A1 (en) * | 2000-10-05 | 2002-04-11 | Noriaki Sakamoto | Semiconductor device, semiconductor module and hard disk |
US20040113260A1 (en) * | 2002-11-26 | 2004-06-17 | Shinko Electric Industries Co., Ltd. | Electronic parts packaging structure and method of manufacturing the same |
US20040130013A1 (en) * | 2002-11-11 | 2004-07-08 | Masahiro Sunohara | Electronic parts packaging structure and method of manufacturing the same |
US20040159933A1 (en) * | 2003-01-23 | 2004-08-19 | Masahiro Sunohara | Electronic parts packaging structure and method of manufacturing the same |
US6873060B2 (en) * | 2002-03-25 | 2005-03-29 | Infineon Technologies Ag | Electronic component with a semiconductor chip, method of producing an electronic component and a panel with a plurality of electronic components |
US6909054B2 (en) * | 2000-02-25 | 2005-06-21 | Ibiden Co., Ltd. | Multilayer printed wiring board and method for producing multilayer printed wiring board |
US20050211465A1 (en) * | 2004-03-29 | 2005-09-29 | Shinko Electric Industries Co., Ltd. | Electronic parts packaging structure and method of manufacturing the same |
US20050230835A1 (en) * | 2004-04-20 | 2005-10-20 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
US20050263860A1 (en) * | 2004-05-26 | 2005-12-01 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20050269698A1 (en) * | 2004-06-02 | 2005-12-08 | Casio Computer Co., Ltd. | Semiconductor device having adhesion increasing film and method of fabricating the same |
US20060003495A1 (en) * | 2004-06-30 | 2006-01-05 | Masahiro Sunohara | Method for fabricating an electronic component embedded substrate |
US20060021791A1 (en) * | 2004-08-02 | 2006-02-02 | Masahiro Sunohara | Electronic component embedded substrate and method for manufacturing the same |
US20060040463A1 (en) * | 2004-08-19 | 2006-02-23 | Masahiro Sunohara | Manufacturing method of an electronic part built-in substrate |
US20060121718A1 (en) * | 2004-12-07 | 2006-06-08 | Yoshihiro Machida | Manufacturing method of chip integrated substrate |
US20060216854A1 (en) * | 2003-04-02 | 2006-09-28 | Kazuhiro Nishikawa | Circuit board and process for producing the same |
US7566584B2 (en) * | 2005-05-23 | 2009-07-28 | Seiko Epson Corporation | Electronic substrate manufacturing method, semiconductor device manufacturing method, and electronic equipment manufacturing method |
US7855342B2 (en) * | 2000-09-25 | 2010-12-21 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2772157B2 (en) * | 1991-05-28 | 1998-07-02 | 三菱重工業株式会社 | Semiconductor device wiring method |
JPH07153867A (en) * | 1993-11-30 | 1995-06-16 | Hitachi Ltd | Semiconductor device and its manufacture |
JP2842378B2 (en) * | 1996-05-31 | 1999-01-06 | 日本電気株式会社 | High-density mounting structure for electronic circuit boards |
JP2001291797A (en) * | 2000-04-10 | 2001-10-19 | Shinko Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
JP2004152982A (en) * | 2002-10-30 | 2004-05-27 | Matsushita Electric Ind Co Ltd | Method of manufacturing device mounted with electronic component, and finished product mounted with electronic component and method of manufacturing the same mounted with electronic component |
JP4137659B2 (en) | 2003-02-13 | 2008-08-20 | 新光電気工業株式会社 | Electronic component mounting structure and manufacturing method thereof |
JP2004335641A (en) | 2003-05-06 | 2004-11-25 | Canon Inc | Method of manufacturing substrate having built-in semiconductor element |
TWI260056B (en) * | 2005-02-01 | 2006-08-11 | Phoenix Prec Technology Corp | Module structure having an embedded chip |
-
2006
- 2006-10-26 JP JP2006291272A patent/JP5164362B2/en not_active Expired - Fee Related
- 2006-11-02 US US11/555,760 patent/US20070108610A1/en not_active Abandoned
-
2013
- 2013-01-24 US US13/748,657 patent/US8609539B2/en not_active Expired - Fee Related
Patent Citations (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3903590A (en) * | 1973-03-10 | 1975-09-09 | Tokyo Shibaura Electric Co | Multiple chip integrated circuits and method of manufacturing the same |
US4754319A (en) * | 1984-05-30 | 1988-06-28 | Kabushiki Kaisha Toshiba | IC card and method for manufacturing the same |
US4997791A (en) * | 1986-05-20 | 1991-03-05 | Kabushiki Kaisha Toshiba | IC card and method of manufacturing the same |
US5548091A (en) * | 1993-10-26 | 1996-08-20 | Tessera, Inc. | Semiconductor chip connection components with adhesives and methods for bonding to the chip |
US6239983B1 (en) * | 1995-10-13 | 2001-05-29 | Meiko Electronics Co., Ltd. | Circuit board, manufacturing method therefor, and bump-type contact head and semiconductor component packaging module using the circuit board |
US6909054B2 (en) * | 2000-02-25 | 2005-06-21 | Ibiden Co., Ltd. | Multilayer printed wiring board and method for producing multilayer printed wiring board |
US7435910B2 (en) * | 2000-02-25 | 2008-10-14 | Ibiden Co., Ltd. | Multilayer printed circuit board |
US7855342B2 (en) * | 2000-09-25 | 2010-12-21 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
US20020041021A1 (en) * | 2000-10-05 | 2002-04-11 | Noriaki Sakamoto | Semiconductor device, semiconductor module and hard disk |
US6933604B2 (en) * | 2000-10-05 | 2005-08-23 | Sanyo Electric Co., Ltd. | Semiconductor device, semiconductor module and hard disk |
US6873060B2 (en) * | 2002-03-25 | 2005-03-29 | Infineon Technologies Ag | Electronic component with a semiconductor chip, method of producing an electronic component and a panel with a plurality of electronic components |
US20050067721A1 (en) * | 2002-03-25 | 2005-03-31 | Infineon Technologies Ag | Method of producing an electronic component and a panel with a plurality of electronic components |
US7223639B2 (en) * | 2002-03-25 | 2007-05-29 | Infineon Technologies Ag | Method of producing an electronic component and a panel with a plurality of electronic components |
US20040130013A1 (en) * | 2002-11-11 | 2004-07-08 | Masahiro Sunohara | Electronic parts packaging structure and method of manufacturing the same |
US20040113260A1 (en) * | 2002-11-26 | 2004-06-17 | Shinko Electric Industries Co., Ltd. | Electronic parts packaging structure and method of manufacturing the same |
US20040159933A1 (en) * | 2003-01-23 | 2004-08-19 | Masahiro Sunohara | Electronic parts packaging structure and method of manufacturing the same |
US20060216854A1 (en) * | 2003-04-02 | 2006-09-28 | Kazuhiro Nishikawa | Circuit board and process for producing the same |
US7563650B2 (en) * | 2003-04-02 | 2009-07-21 | Panasonic Corporation | Circuit board and the manufacturing method |
US20050211465A1 (en) * | 2004-03-29 | 2005-09-29 | Shinko Electric Industries Co., Ltd. | Electronic parts packaging structure and method of manufacturing the same |
US7285728B2 (en) * | 2004-03-29 | 2007-10-23 | Shinko Electric Industries Co., Ltd. | Electronic parts packaging structure and method of manufacturing the same |
US7122901B2 (en) * | 2004-04-20 | 2006-10-17 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
US20050230835A1 (en) * | 2004-04-20 | 2005-10-20 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
US7157789B2 (en) * | 2004-05-26 | 2007-01-02 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20050263860A1 (en) * | 2004-05-26 | 2005-12-01 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20050269698A1 (en) * | 2004-06-02 | 2005-12-08 | Casio Computer Co., Ltd. | Semiconductor device having adhesion increasing film and method of fabricating the same |
US7727802B2 (en) * | 2004-06-30 | 2010-06-01 | Shinko Electric Industries Co., Ltd. | Method for fabricating an electronic component embedded substrate |
US20060003495A1 (en) * | 2004-06-30 | 2006-01-05 | Masahiro Sunohara | Method for fabricating an electronic component embedded substrate |
US7420128B2 (en) * | 2004-08-02 | 2008-09-02 | Shinko Electric Industries Co., Ltd. | Electronic component embedded substrate and method for manufacturing the same |
US20060021791A1 (en) * | 2004-08-02 | 2006-02-02 | Masahiro Sunohara | Electronic component embedded substrate and method for manufacturing the same |
US20060040463A1 (en) * | 2004-08-19 | 2006-02-23 | Masahiro Sunohara | Manufacturing method of an electronic part built-in substrate |
US20060121718A1 (en) * | 2004-12-07 | 2006-06-08 | Yoshihiro Machida | Manufacturing method of chip integrated substrate |
US7521283B2 (en) * | 2004-12-07 | 2009-04-21 | Shinko Electric Industries Co., Ltd. | Manufacturing method of chip integrated substrate |
US7566584B2 (en) * | 2005-05-23 | 2009-07-28 | Seiko Epson Corporation | Electronic substrate manufacturing method, semiconductor device manufacturing method, and electronic equipment manufacturing method |
Cited By (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080273314A1 (en) * | 2007-05-04 | 2008-11-06 | Samsung Electronics Co., Ltd. | PCB having embedded IC and method for manufacturing the same |
US8629354B2 (en) * | 2007-05-04 | 2014-01-14 | Samsung Electronics Co., Ltd. | PCB having embedded IC and method for manufacturing the same |
US8409971B2 (en) | 2007-06-07 | 2013-04-02 | Commissariat A L'energie Atomique | Integrated multicomponent device in a semiconducting die |
US20100195299A1 (en) * | 2007-06-07 | 2010-08-05 | Commissariat A L'energie Atomique | Integrated multicomponent device in a semiconducting die |
EP2624289A3 (en) * | 2008-04-04 | 2014-04-16 | The Charles Stark Draper Laboratory, Inc. | Interposers, electronic modules, and methods for forming the same |
US20090250249A1 (en) * | 2008-04-04 | 2009-10-08 | Racz Livia M | Interposers, electronic modules, and methods for forming the same |
US9425069B2 (en) | 2008-04-04 | 2016-08-23 | Charles Stark Draper Laboratory, Inc. | Electronic modules |
US8017451B2 (en) | 2008-04-04 | 2011-09-13 | The Charles Stark Draper Laboratory, Inc. | Electronic modules and methods for forming the same |
US8273603B2 (en) | 2008-04-04 | 2012-09-25 | The Charles Stark Draper Laboratory, Inc. | Interposers, electronic modules, and methods for forming the same |
EP2624289A2 (en) * | 2008-04-04 | 2013-08-07 | The Charles Stark Draper Laboratory, Inc. | Interposers, electronic modules, and methods for forming the same |
US20090250823A1 (en) * | 2008-04-04 | 2009-10-08 | Racz Livia M | Electronic Modules and Methods for Forming the Same |
WO2009124246A1 (en) * | 2008-04-04 | 2009-10-08 | The Charles Stark Draper Laboratory, Inc. | Interposers, electronic modules, and methods for forming the same |
US8535984B2 (en) | 2008-04-04 | 2013-09-17 | The Charles Stark Draper Laboratory, Inc. | Electronic modules and methods for forming the same |
US20140307403A1 (en) * | 2008-05-30 | 2014-10-16 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for integrating an electronic component into a printed circuit board |
US20100047567A1 (en) * | 2008-07-21 | 2010-02-25 | Commissariat A L'energie Atomique | Multi-component device integrated into a matrix |
EP2148366A1 (en) * | 2008-07-21 | 2010-01-27 | Commissariat a L'Energie Atomique | Device having plurality of integrated circuits in a matrix |
US8466568B2 (en) | 2008-07-21 | 2013-06-18 | Commissariat A L'energie Atomique | Multi-component device integrated into a matrix |
US20100078204A1 (en) * | 2008-09-29 | 2010-04-01 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board including electronic component embedded therein and method of manufacturing the same |
US8288841B2 (en) | 2009-07-09 | 2012-10-16 | Commissariat à l'énergie atomique et aux énergies alternatives | Handle wafer having viewing windows |
US20110006400A1 (en) * | 2009-07-09 | 2011-01-13 | Comm. á I'éner. atom. et aux énergies alter. | Handle wafer having viewing windows |
US8435837B2 (en) * | 2009-12-15 | 2013-05-07 | Silicon Storage Technology, Inc. | Panel based lead frame packaging method and device |
US20130015572A1 (en) * | 2009-12-15 | 2013-01-17 | Technische Universitat Berlin | Electronic assembly including an embedded electronic component |
US20110140254A1 (en) * | 2009-12-15 | 2011-06-16 | Silicon Storage Technology, Inc. | Panel Based Lead Frame Packaging Method And Device |
US8975116B2 (en) * | 2009-12-15 | 2015-03-10 | Technische Universität Berlin | Electronic assembly including an embedded electronic component |
US10618206B2 (en) | 2017-02-27 | 2020-04-14 | Omron Corporation | Resin-molded electronic device with disconnect prevention |
Also Published As
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JP5164362B2 (en) | 2013-03-21 |
US8609539B2 (en) | 2013-12-17 |
JP2007150275A (en) | 2007-06-14 |
US20130130494A1 (en) | 2013-05-23 |
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