JP4931277B2 - フレキシブル基板上の相互接続用金属にダイを位置合せするための装置及び方法 - Google Patents

フレキシブル基板上の相互接続用金属にダイを位置合せするための装置及び方法 Download PDF

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Publication number
JP4931277B2
JP4931277B2 JP2000388006A JP2000388006A JP4931277B2 JP 4931277 B2 JP4931277 B2 JP 4931277B2 JP 2000388006 A JP2000388006 A JP 2000388006A JP 2000388006 A JP2000388006 A JP 2000388006A JP 4931277 B2 JP4931277 B2 JP 4931277B2
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Japan
Prior art keywords
die
flexible substrate
bond pad
reference point
camera
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2000388006A
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English (en)
Japanese (ja)
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JP2001250888A5 (https=
JP2001250888A (ja
Inventor
リチャード・ジョセフ・サイア
ケビン・マシュー・ドゥロチャー
ジェームズ・ウィルソン・ローズ
レオナルド・リチャード・ダグラス
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General Electric Co
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General Electric Co
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Publication of JP2001250888A5 publication Critical patent/JP2001250888A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07321—Aligning
    • H10W72/07327—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49131—Assembling to base an electrical component, e.g., capacitor, etc. by utilizing optical sighting device

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Laser Beam Processing (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
JP2000388006A 1999-12-22 2000-12-21 フレキシブル基板上の相互接続用金属にダイを位置合せするための装置及び方法 Expired - Lifetime JP4931277B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/469749 1999-12-22
US09/469,749 US6475877B1 (en) 1999-12-22 1999-12-22 Method for aligning die to interconnect metal on flex substrate

Publications (3)

Publication Number Publication Date
JP2001250888A JP2001250888A (ja) 2001-09-14
JP2001250888A5 JP2001250888A5 (https=) 2008-02-14
JP4931277B2 true JP4931277B2 (ja) 2012-05-16

Family

ID=23864927

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000388006A Expired - Lifetime JP4931277B2 (ja) 1999-12-22 2000-12-21 フレキシブル基板上の相互接続用金属にダイを位置合せするための装置及び方法

Country Status (5)

Country Link
US (2) US6475877B1 (https=)
EP (1) EP1111662B1 (https=)
JP (1) JP4931277B2 (https=)
CN (1) CN1199250C (https=)
TW (1) TW490716B (https=)

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6888240B2 (en) 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US7183658B2 (en) * 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
JP3645511B2 (ja) * 2001-10-09 2005-05-11 株式会社ルネサステクノロジ 半導体装置の製造方法
US8455994B2 (en) * 2002-01-31 2013-06-04 Imbera Electronics Oy Electronic module with feed through conductor between wiring patterns
FI119215B (fi) * 2002-01-31 2008-08-29 Imbera Electronics Oy Menetelmä komponentin upottamiseksi alustaan ja elektroniikkamoduuli
FI115285B (fi) * 2002-01-31 2005-03-31 Imbera Electronics Oy Menetelmä komponentin upottamiseksi alustaan ja kontaktin muodostamiseksi
US6964881B2 (en) * 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
US6855953B2 (en) * 2002-12-20 2005-02-15 Itt Manufacturing Enterprises, Inc. Electronic circuit assembly having high contrast fiducial
US7263677B1 (en) * 2002-12-31 2007-08-28 Cadence Design Systems, Inc. Method and apparatus for creating efficient vias between metal layers in semiconductor designs and layouts
FI115601B (fi) * 2003-04-01 2005-05-31 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli
US8704359B2 (en) 2003-04-01 2014-04-22 Ge Embedded Electronics Oy Method for manufacturing an electronic module and an electronic module
US8222723B2 (en) 2003-04-01 2012-07-17 Imbera Electronics Oy Electric module having a conductive pattern layer
CN1302541C (zh) * 2003-07-08 2007-02-28 敦南科技股份有限公司 具有柔性电路板的芯片封装基板及其制造方法
FI20031201A7 (fi) * 2003-08-26 2005-02-27 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli
FI20031341L (fi) 2003-09-18 2005-03-19 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
TWI237883B (en) * 2004-05-11 2005-08-11 Via Tech Inc Chip embedded package structure and process thereof
FI117814B (fi) * 2004-06-15 2007-02-28 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
TWI250596B (en) * 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
US8487194B2 (en) * 2004-08-05 2013-07-16 Imbera Electronics Oy Circuit board including an embedded component
FI117812B (fi) * 2004-08-05 2007-02-28 Imbera Electronics Oy Komponentin sisältävän kerroksen valmistaminen
FI117369B (fi) 2004-11-26 2006-09-15 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
CN100541767C (zh) * 2005-01-28 2009-09-16 松下电器产业株式会社 电子元件封装的制造方法以及电子元件封装
FI122128B (fi) * 2005-06-16 2011-08-31 Imbera Electronics Oy Menetelmä piirilevyrakenteen valmistamiseksi
DE112006001506T5 (de) 2005-06-16 2008-04-30 Imbera Electronics Oy Platinenstruktur und Verfahren zu ihrer Herstellung
FI119714B (fi) 2005-06-16 2009-02-13 Imbera Electronics Oy Piirilevyrakenne ja menetelmä piirilevyrakenteen valmistamiseksi
EP1905079A2 (en) * 2005-07-07 2008-04-02 Koninklijke Philips Electronics N.V. Package, method of manufacturing the same and use thereof
US20070012965A1 (en) * 2005-07-15 2007-01-18 General Electric Company Photodetection system and module
JP4487875B2 (ja) * 2005-07-20 2010-06-23 セイコーエプソン株式会社 電子基板の製造方法及び電気光学装置の製造方法並びに電子機器の製造方法
US9601474B2 (en) * 2005-07-22 2017-03-21 Invensas Corporation Electrically stackable semiconductor wafer and chip packages
KR100785014B1 (ko) * 2006-04-14 2007-12-12 삼성전자주식회사 Ｓｏｉ웨이퍼를 이용한 ｍｅｍｓ 디바이스 및 그 제조방법
JP5091600B2 (ja) * 2006-09-29 2012-12-05 三洋電機株式会社 半導体モジュール、半導体モジュールの製造方法および携帯機器
US7579215B2 (en) * 2007-03-30 2009-08-25 Motorola, Inc. Method for fabricating a low cost integrated circuit (IC) package
US9610758B2 (en) * 2007-06-21 2017-04-04 General Electric Company Method of making demountable interconnect structure
US20080318054A1 (en) * 2007-06-21 2008-12-25 General Electric Company Low-temperature recoverable electronic component
US20080318413A1 (en) * 2007-06-21 2008-12-25 General Electric Company Method for making an interconnect structure and interconnect component recovery process
US9953910B2 (en) * 2007-06-21 2018-04-24 General Electric Company Demountable interconnect structure
US20080318055A1 (en) * 2007-06-21 2008-12-25 General Electric Company Recoverable electronic component
US20080313894A1 (en) * 2007-06-21 2008-12-25 General Electric Company Method for making an interconnect structure and low-temperature interconnect component recovery process
US20090028491A1 (en) * 2007-07-26 2009-01-29 General Electric Company Interconnect structure
CN101373748B (zh) * 2007-08-20 2011-06-15 宏茂微电子(上海)有限公司 晶圆级封装结构及其制作方法
JP4966156B2 (ja) * 2007-10-23 2012-07-04 ソニーケミカル＆インフォメーションデバイス株式会社 配線基板の受台及びこれを用いた配線基板の接続装置、接続方法
US9010225B2 (en) * 2007-12-21 2015-04-21 Tokyo Seimitsu Co., Ltd. Dicing apparatus and dicing method
JP4840373B2 (ja) * 2008-01-31 2011-12-21 カシオ計算機株式会社 半導体装置およびその製造方法
FI123205B (fi) 2008-05-12 2012-12-31 Imbera Electronics Oy Piirimoduuli ja menetelmä piirimoduulin valmistamiseksi
KR20110076979A (ko) 2008-10-30 2011-07-06 에이티 앤 에스 오스트리아 테크놀로지 앤 시스템테크니크 악치엔게젤샤프트 인쇄회로기판에 전자부품을 통합하는 방법
US7964974B2 (en) 2008-12-02 2011-06-21 General Electric Company Electronic chip package with reduced contact pad pitch
US8008781B2 (en) 2008-12-02 2011-08-30 General Electric Company Apparatus and method for reducing pitch in an integrated circuit
US7897481B2 (en) * 2008-12-05 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. High throughput die-to-wafer bonding using pre-alignment
WO2011065062A1 (ja) * 2009-11-30 2011-06-03 シャープ株式会社 フレキシブル回路基板およびその製造方法
US8623689B2 (en) * 2010-07-07 2014-01-07 Ineffable Cellular Limited Liability Company Package process of backside illumination image sensor
JP5399542B2 (ja) * 2012-08-08 2014-01-29 富士通株式会社 半導体装置の製造方法
JP5554380B2 (ja) * 2012-08-08 2014-07-23 富士通株式会社 半導体装置
WO2014097641A1 (ja) * 2012-12-21 2014-06-26 パナソニック株式会社 電子部品パッケージおよびその製造方法
WO2014097644A1 (ja) * 2012-12-21 2014-06-26 パナソニック株式会社 電子部品パッケージおよびその製造方法
JP5624699B1 (ja) * 2012-12-21 2014-11-12 パナソニック株式会社 電子部品パッケージおよびその製造方法
US9449944B2 (en) 2012-12-21 2016-09-20 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing same
CN104584207A (zh) 2012-12-21 2015-04-29 松下知识产权经营株式会社 电子部件封装以及其制造方法
DE102015214219A1 (de) * 2015-07-28 2017-02-02 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Bauelements und ein Bauelement
JP2017073472A (ja) * 2015-10-07 2017-04-13 株式会社ディスコ 半導体装置の製造方法
CN110024107B (zh) * 2016-11-30 2023-11-10 深圳修远电子科技有限公司 集成电路封装方法以及集成封装电路
EP3557608A1 (en) 2018-04-19 2019-10-23 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Packaged integrated circuit with interposing functionality and method for manufacturing such a packaged integrated circuit
EP3833164A1 (en) 2019-12-05 2021-06-09 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Compensating misalignment of component carrier feature by modifying target design concerning correlated component carrier feature
US20240145258A1 (en) * 2022-10-27 2024-05-02 Stmicroelectronics Pte Ltd Panel level semiconductor package and method of manufacturing the same

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4783695A (en) 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US4933042A (en) 1986-09-26 1990-06-12 General Electric Company Method for packaging integrated circuit chips employing a polymer film overlay layer
US4835704A (en) 1986-12-29 1989-05-30 General Electric Company Adaptive lithography system to provide high density interconnect
US5192716A (en) 1989-01-25 1993-03-09 Polylithics, Inc. Method of making a extended integration semiconductor structure
US5055907A (en) * 1989-01-25 1991-10-08 Mosaic, Inc. Extended integration semiconductor structure with wiring layers
JP2803221B2 (ja) 1989-09-19 1998-09-24 松下電器産業株式会社 Ｉｃ実装装置及びその方法
US5194948A (en) * 1991-04-26 1993-03-16 At&T Bell Laboratories Article alignment method and apparatus
JPH05152794A (ja) * 1991-11-29 1993-06-18 Sharp Corp Ｉｃチツプ実装装置
JPH06338538A (ja) * 1993-05-28 1994-12-06 Nippon Chemicon Corp 半導体素子の接続方法
US5527741A (en) * 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
JPH09232363A (ja) 1996-02-23 1997-09-05 Toshiba Corp 半導体チップの位置合せ方法およびボンディング装置
GB9610689D0 (en) * 1996-05-22 1996-07-31 Int Computers Ltd Flip chip attachment
US5920123A (en) 1997-01-24 1999-07-06 Micron Technology, Inc. Multichip module assembly having via contacts and method of making the same
JP3160252B2 (ja) * 1997-12-11 2001-04-25 イビデン株式会社 多層プリント配線板の製造方法
JP3919972B2 (ja) * 1998-07-31 2007-05-30 セイコーエプソン株式会社 半導体装置の製造方法
US6246010B1 (en) * 1998-11-25 2001-06-12 3M Innovative Properties Company High density electronic package
US6284564B1 (en) 1999-09-20 2001-09-04 Lockheed Martin Corp. HDI chip attachment method for reduced processing
US6242282B1 (en) * 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package

Also Published As

Publication number Publication date
EP1111662B1 (en) 2012-12-12
EP1111662A2 (en) 2001-06-27
CN1199250C (zh) 2005-04-27
US20020197767A1 (en) 2002-12-26
US6475877B1 (en) 2002-11-05
TW490716B (en) 2002-06-11
EP1111662A3 (en) 2003-10-01
CN1301039A (zh) 2001-06-27
US6790703B2 (en) 2004-09-14
JP2001250888A (ja) 2001-09-14

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