CN1199250C - 对准管芯与柔性基板上的通孔掩模层的装置和方法 - Google Patents

对准管芯与柔性基板上的通孔掩模层的装置和方法 Download PDF

Info

Publication number
CN1199250C
CN1199250C CNB001364499A CN00136449A CN1199250C CN 1199250 C CN1199250 C CN 1199250C CN B001364499 A CNB001364499 A CN B001364499A CN 00136449 A CN00136449 A CN 00136449A CN 1199250 C CN1199250 C CN 1199250C
Authority
CN
China
Prior art keywords
die
welding pad
bonding welding
hole
flexible substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB001364499A
Other languages
English (en)
Chinese (zh)
Other versions
CN1301039A (zh
Inventor
R·J·赛尔
K·M·杜罗切尔
J·W·罗斯
L·R·杜格拉斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of CN1301039A publication Critical patent/CN1301039A/zh
Application granted granted Critical
Publication of CN1199250C publication Critical patent/CN1199250C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/76—Apparatus for connecting with build-up interconnects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49131—Assembling to base an electrical component, e.g., capacitor, etc. by utilizing optical sighting device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Laser Beam Processing (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
CNB001364499A 1999-12-22 2000-12-22 对准管芯与柔性基板上的通孔掩模层的装置和方法 Expired - Lifetime CN1199250C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/469749 1999-12-22
US09/469,749 US6475877B1 (en) 1999-12-22 1999-12-22 Method for aligning die to interconnect metal on flex substrate

Publications (2)

Publication Number Publication Date
CN1301039A CN1301039A (zh) 2001-06-27
CN1199250C true CN1199250C (zh) 2005-04-27

Family

ID=23864927

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB001364499A Expired - Lifetime CN1199250C (zh) 1999-12-22 2000-12-22 对准管芯与柔性基板上的通孔掩模层的装置和方法

Country Status (5)

Country Link
US (2) US6475877B1 (enExample)
EP (1) EP1111662B1 (enExample)
JP (1) JP4931277B2 (enExample)
CN (1) CN1199250C (enExample)
TW (1) TW490716B (enExample)

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US6888240B2 (en) 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US7183658B2 (en) 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
JP3645511B2 (ja) * 2001-10-09 2005-05-11 株式会社ルネサステクノロジ 半導体装置の製造方法
US8455994B2 (en) * 2002-01-31 2013-06-04 Imbera Electronics Oy Electronic module with feed through conductor between wiring patterns
FI119215B (fi) * 2002-01-31 2008-08-29 Imbera Electronics Oy Menetelmä komponentin upottamiseksi alustaan ja elektroniikkamoduuli
FI115285B (fi) * 2002-01-31 2005-03-31 Imbera Electronics Oy Menetelmä komponentin upottamiseksi alustaan ja kontaktin muodostamiseksi
US6964881B2 (en) * 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
US6855953B2 (en) * 2002-12-20 2005-02-15 Itt Manufacturing Enterprises, Inc. Electronic circuit assembly having high contrast fiducial
US7263677B1 (en) * 2002-12-31 2007-08-28 Cadence Design Systems, Inc. Method and apparatus for creating efficient vias between metal layers in semiconductor designs and layouts
US8222723B2 (en) 2003-04-01 2012-07-17 Imbera Electronics Oy Electric module having a conductive pattern layer
US8704359B2 (en) 2003-04-01 2014-04-22 Ge Embedded Electronics Oy Method for manufacturing an electronic module and an electronic module
FI115601B (fi) * 2003-04-01 2005-05-31 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli
CN1302541C (zh) * 2003-07-08 2007-02-28 敦南科技股份有限公司 具有柔性电路板的芯片封装基板及其制造方法
FI20031201A7 (fi) * 2003-08-26 2005-02-27 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli
FI20031341L (fi) 2003-09-18 2005-03-19 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
TWI237883B (en) * 2004-05-11 2005-08-11 Via Tech Inc Chip embedded package structure and process thereof
FI117814B (fi) * 2004-06-15 2007-02-28 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
TWI250596B (en) * 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
US8487194B2 (en) * 2004-08-05 2013-07-16 Imbera Electronics Oy Circuit board including an embedded component
FI117812B (fi) * 2004-08-05 2007-02-28 Imbera Electronics Oy Komponentin sisältävän kerroksen valmistaminen
FI117369B (fi) 2004-11-26 2006-09-15 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
JP4588753B2 (ja) * 2005-01-28 2010-12-01 パナソニック株式会社 電子素子パッケージの製造方法および電子素子パッケージ
JP2008544512A (ja) 2005-06-16 2008-12-04 イムベラ エレクトロニクス オサケユキチュア 回路基板構造体およびその製造方法
FI122128B (fi) * 2005-06-16 2011-08-31 Imbera Electronics Oy Menetelmä piirilevyrakenteen valmistamiseksi
FI119714B (fi) 2005-06-16 2009-02-13 Imbera Electronics Oy Piirilevyrakenne ja menetelmä piirilevyrakenteen valmistamiseksi
KR20080023721A (ko) * 2005-07-07 2008-03-14 코닌클리케 필립스 일렉트로닉스 엔.브이. 패키지, 이들의 제조 방법 및 이들의 사용 방법
US20070012965A1 (en) * 2005-07-15 2007-01-18 General Electric Company Photodetection system and module
JP4487875B2 (ja) * 2005-07-20 2010-06-23 セイコーエプソン株式会社 電子基板の製造方法及び電気光学装置の製造方法並びに電子機器の製造方法
US9601474B2 (en) * 2005-07-22 2017-03-21 Invensas Corporation Electrically stackable semiconductor wafer and chip packages
KR100785014B1 (ko) * 2006-04-14 2007-12-12 삼성전자주식회사 Ｓｏｉ웨이퍼를 이용한 ｍｅｍｓ 디바이스 및 그 제조방법
JP5091600B2 (ja) * 2006-09-29 2012-12-05 三洋電機株式会社 半導体モジュール、半導体モジュールの製造方法および携帯機器
US7579215B2 (en) * 2007-03-30 2009-08-25 Motorola, Inc. Method for fabricating a low cost integrated circuit (IC) package
US20080318413A1 (en) * 2007-06-21 2008-12-25 General Electric Company Method for making an interconnect structure and interconnect component recovery process
US20080313894A1 (en) * 2007-06-21 2008-12-25 General Electric Company Method for making an interconnect structure and low-temperature interconnect component recovery process
US9610758B2 (en) * 2007-06-21 2017-04-04 General Electric Company Method of making demountable interconnect structure
US9953910B2 (en) * 2007-06-21 2018-04-24 General Electric Company Demountable interconnect structure
US20080318054A1 (en) * 2007-06-21 2008-12-25 General Electric Company Low-temperature recoverable electronic component
US20080318055A1 (en) * 2007-06-21 2008-12-25 General Electric Company Recoverable electronic component
US20090028491A1 (en) * 2007-07-26 2009-01-29 General Electric Company Interconnect structure
CN101373748B (zh) * 2007-08-20 2011-06-15 宏茂微电子(上海)有限公司 晶圆级封装结构及其制作方法
JP4966156B2 (ja) * 2007-10-23 2012-07-04 ソニーケミカル＆インフォメーションデバイス株式会社 配線基板の受台及びこれを用いた配線基板の接続装置、接続方法
JP5459484B2 (ja) * 2007-12-21 2014-04-02 株式会社東京精密 ダイシング装置及びダイシング方法
JP4840373B2 (ja) * 2008-01-31 2011-12-21 カシオ計算機株式会社 半導体装置およびその製造方法
FI123205B (fi) 2008-05-12 2012-12-31 Imbera Electronics Oy Piirimoduuli ja menetelmä piirimoduulin valmistamiseksi
CN102204418B (zh) 2008-10-30 2016-05-18 At&S奥地利科技及系统技术股份公司 用于将电子部件集成到印制电路板中的方法
US7964974B2 (en) 2008-12-02 2011-06-21 General Electric Company Electronic chip package with reduced contact pad pitch
US8008781B2 (en) 2008-12-02 2011-08-30 General Electric Company Apparatus and method for reducing pitch in an integrated circuit
US7897481B2 (en) * 2008-12-05 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. High throughput die-to-wafer bonding using pre-alignment
US20120155038A1 (en) * 2009-11-30 2012-06-21 Sharp Kabushiki Kaisha Flexible circuit board and manufacturing method thereof
US8623689B2 (en) * 2010-07-07 2014-01-07 Ineffable Cellular Limited Liability Company Package process of backside illumination image sensor
JP5399542B2 (ja) * 2012-08-08 2014-01-29 富士通株式会社 半導体装置の製造方法
JP5554380B2 (ja) * 2012-08-08 2014-07-23 富士通株式会社 半導体装置
JP5624699B1 (ja) * 2012-12-21 2014-11-12 パナソニック株式会社 電子部品パッケージおよびその製造方法
CN104584210B (zh) * 2012-12-21 2017-09-26 松下知识产权经营株式会社 电子部件封装件及其制造方法
CN104603932A (zh) * 2012-12-21 2015-05-06 松下知识产权经营株式会社 电子部件封装件及其制造方法
WO2014097644A1 (ja) * 2012-12-21 2014-06-26 パナソニック株式会社 電子部品パッケージおよびその製造方法
US9595651B2 (en) 2012-12-21 2017-03-14 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing same
DE102015214219A1 (de) * 2015-07-28 2017-02-02 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Bauelements und ein Bauelement
JP2017073472A (ja) * 2015-10-07 2017-04-13 株式会社ディスコ 半導体装置の製造方法
US10867959B2 (en) * 2016-11-30 2020-12-15 Shenzhen Xiuyuan Electronic Technology Co., Ltd Integrated circuit packaging method and integrated packaged circuit
EP3557608A1 (en) 2018-04-19 2019-10-23 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Packaged integrated circuit with interposing functionality and method for manufacturing such a packaged integrated circuit
EP3833164A1 (en) 2019-12-05 2021-06-09 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Compensating misalignment of component carrier feature by modifying target design concerning correlated component carrier feature
US20240145258A1 (en) * 2022-10-27 2024-05-02 Stmicroelectronics Pte Ltd Panel level semiconductor package and method of manufacturing the same

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933042A (en) 1986-09-26 1990-06-12 General Electric Company Method for packaging integrated circuit chips employing a polymer film overlay layer
US4783695A (en) 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US4835704A (en) 1986-12-29 1989-05-30 General Electric Company Adaptive lithography system to provide high density interconnect
US5055907A (en) * 1989-01-25 1991-10-08 Mosaic, Inc. Extended integration semiconductor structure with wiring layers
US5192716A (en) 1989-01-25 1993-03-09 Polylithics, Inc. Method of making a extended integration semiconductor structure
JP2803221B2 (ja) 1989-09-19 1998-09-24 松下電器産業株式会社 Ｉｃ実装装置及びその方法
US5194948A (en) * 1991-04-26 1993-03-16 At&T Bell Laboratories Article alignment method and apparatus
JPH05152794A (ja) * 1991-11-29 1993-06-18 Sharp Corp Ｉｃチツプ実装装置
JPH06338538A (ja) * 1993-05-28 1994-12-06 Nippon Chemicon Corp 半導体素子の接続方法
US5527741A (en) * 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
JPH09232363A (ja) * 1996-02-23 1997-09-05 Toshiba Corp 半導体チップの位置合せ方法およびボンディング装置
GB9610689D0 (en) * 1996-05-22 1996-07-31 Int Computers Ltd Flip chip attachment
US5920123A (en) 1997-01-24 1999-07-06 Micron Technology, Inc. Multichip module assembly having via contacts and method of making the same
JP3160252B2 (ja) * 1997-12-11 2001-04-25 イビデン株式会社 多層プリント配線板の製造方法
JP3919972B2 (ja) * 1998-07-31 2007-05-30 セイコーエプソン株式会社 半導体装置の製造方法
US6246010B1 (en) * 1998-11-25 2001-06-12 3M Innovative Properties Company High density electronic package
US6284564B1 (en) 1999-09-20 2001-09-04 Lockheed Martin Corp. HDI chip attachment method for reduced processing
US6242282B1 (en) * 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package

Also Published As

Publication number Publication date
JP2001250888A (ja) 2001-09-14
JP4931277B2 (ja) 2012-05-16
CN1301039A (zh) 2001-06-27
EP1111662A2 (en) 2001-06-27
EP1111662B1 (en) 2012-12-12
EP1111662A3 (en) 2003-10-01
TW490716B (en) 2002-06-11
US6475877B1 (en) 2002-11-05
US6790703B2 (en) 2004-09-14
US20020197767A1 (en) 2002-12-26

Similar Documents

Publication Publication Date Title
CN1199250C (zh) 对准管芯与柔性基板上的通孔掩模层的装置和方法
US5875100A (en) High-density mounting method and structure for electronic circuit board
KR101455234B1 (ko) 회로 보드 구조체 제조 방법 및 회로 보드 구조체
US8119516B2 (en) Bump structure formed from using removable mandrel
CN100380649C (zh) 电气元件的基片及其制造方法
US6255726B1 (en) Vertical interconnect process for silicon segments with dielectric isolation
US6080596A (en) Method for forming vertical interconnect process for silicon segments with dielectric isolation
US8011086B2 (en) Method of manufacturing a component-embedded printed circuit board
US20090218678A1 (en) Semiconductor ic-embedded substrate and method for manufacturing same
US20070267136A1 (en) Method for Manufacturing an Electronics Module
JP3938921B2 (ja) 半導体ｉｃ内蔵モジュールの製造方法
CN101277592B (zh) 布线基板的制造方法
JP2000512083A (ja) バイアマトリックス層間接続を有する多層回路及びその製造方法
US20070267218A1 (en) Multilayer Electronic Component, Electronic Device, and Method for Manufacturing Multilayer Electronic Component
JP2021009992A (ja) 半導体パッケージの配線補正方法
EP1029360A2 (en) Vertical interconnect process for silicon segments with dielectric isolation
CN112930045A (zh) 对制造部件承载件期间的未对准进行补偿的方法和设备
CN100435302C (zh) 芯片内置基板的制造方法
WO2005086553A1 (ja) 多層基板の製造方法
JP2004327609A (ja) パターンフィルムの位置合わせ方法およびプリント配線基板の製造方法
Kahle et al. Development of an Adaptive Re-Distribution Patterning Process for Fan-Out Packages with Embedded High I/O Components
CN1882223A (zh) 一种印刷电路板的制作方法
CN116613140A (zh) 芯片封装组件及其制作方法
JP2003324168A (ja) 半導体集積回路実装用プリント配線板
JPH07321467A (ja) 厚膜・薄膜混成多層配線基板

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20050427