CN1119816C - 有控制字线激活/非激活定时电路的同步型半导体存储器 - Google Patents

有控制字线激活/非激活定时电路的同步型半导体存储器 Download PDF

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Publication number
CN1119816C
CN1119816C CN98116008A CN98116008A CN1119816C CN 1119816 C CN1119816 C CN 1119816C CN 98116008 A CN98116008 A CN 98116008A CN 98116008 A CN98116008 A CN 98116008A CN 1119816 C CN1119816 C CN 1119816C
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CN
China
Prior art keywords
signal
output
activation
test mode
inactivation
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Expired - Fee Related
Application number
CN98116008A
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English (en)
Chinese (zh)
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CN1217546A (zh
Inventor
樱井干夫
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication date
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Publication of CN1217546A publication Critical patent/CN1217546A/zh
Application granted granted Critical
Publication of CN1119816C publication Critical patent/CN1119816C/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
CN98116008A 1997-11-13 1998-07-13 有控制字线激活/非激活定时电路的同步型半导体存储器 Expired - Fee Related CN1119816C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP312355/1997 1997-11-13
JP312355/97 1997-11-13
JP9312355A JPH11144497A (ja) 1997-11-13 1997-11-13 同期型半導体記憶装置

Publications (2)

Publication Number Publication Date
CN1217546A CN1217546A (zh) 1999-05-26
CN1119816C true CN1119816C (zh) 2003-08-27

Family

ID=18028256

Family Applications (1)

Application Number Title Priority Date Filing Date
CN98116008A Expired - Fee Related CN1119816C (zh) 1997-11-13 1998-07-13 有控制字线激活/非激活定时电路的同步型半导体存储器

Country Status (4)

Country Link
US (1) US5973990A (https=)
JP (1) JPH11144497A (https=)
CN (1) CN1119816C (https=)
TW (1) TW409256B (https=)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4531892B2 (ja) * 1999-10-29 2010-08-25 富士通セミコンダクター株式会社 半導体集積回路、半導体集積回路の制御方法、および可変遅延回路
JP4712183B2 (ja) * 2000-11-30 2011-06-29 富士通セミコンダクター株式会社 同期型半導体装置、及び試験システム
JP2004046927A (ja) 2002-07-09 2004-02-12 Elpida Memory Inc 半導体記憶装置
JP2004063023A (ja) 2002-07-30 2004-02-26 Renesas Technology Corp 半導体記憶装置
JP3949081B2 (ja) * 2003-06-09 2007-07-25 株式会社東芝 サンプリング周波数変換装置
US7321991B2 (en) * 2004-01-10 2008-01-22 Hynix Semiconductor Inc. Semiconductor memory device having advanced test mode
JP2006331511A (ja) * 2005-05-25 2006-12-07 Matsushita Electric Ind Co Ltd 半導体記憶装置およびその検査手法
KR100695512B1 (ko) * 2005-06-30 2007-03-15 주식회사 하이닉스반도체 반도체 메모리 장치
EP1990805B1 (en) 2006-02-28 2010-06-30 Fujitsu Ltd. Ram macro and timing generating circuit for same
KR100894487B1 (ko) 2007-06-08 2009-04-22 주식회사 하이닉스반도체 워드라인 구동회로, 이를 포함하는 반도체 메모리장치 및그 테스트방법
KR100885485B1 (ko) * 2007-09-03 2009-02-24 주식회사 하이닉스반도체 반도체 메모리장치
JP2010027155A (ja) * 2008-07-22 2010-02-04 Sanyo Electric Co Ltd 半導体記憶装置
KR101188261B1 (ko) * 2010-07-30 2012-10-05 에스케이하이닉스 주식회사 멀티 비트 테스트 회로
KR101198139B1 (ko) * 2010-11-23 2012-11-12 에스케이하이닉스 주식회사 반도체 메모리 장치의 프리차지 신호 발생 회로
JP2012203970A (ja) 2011-03-28 2012-10-22 Elpida Memory Inc 半導体装置及び半導体装置の制御方法
US9674086B2 (en) * 2013-11-05 2017-06-06 Cisco Technology, Inc. Work conserving schedular based on ranking
KR102471500B1 (ko) * 2018-03-12 2022-11-28 에스케이하이닉스 주식회사 반도체 장치 및 이를 포함하는 테스트 시스템
WO2020063413A1 (en) 2018-09-28 2020-04-02 Changxin Memory Technologies, Inc. Chip and chip test system
CN109164374B (zh) * 2018-09-28 2024-03-29 长鑫存储技术有限公司 芯片与芯片测试系统

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960016807B1 (ko) * 1994-06-30 1996-12-21 삼성전자 주식회사 반도체 메모리 장치의 리던던시 회로
JP2629645B2 (ja) * 1995-04-20 1997-07-09 日本電気株式会社 半導体記憶装置
US5621690A (en) * 1995-04-28 1997-04-15 Intel Corporation Nonvolatile memory blocking architecture and redundancy
KR100392687B1 (ko) * 1995-10-31 2003-11-28 마츠시타 덴끼 산교 가부시키가이샤 반도체 기억장치
KR0172423B1 (ko) * 1995-11-16 1999-03-30 김광호 고주파수 동작을 하는 반도체 메모리 장치의 테스트회로 및 테스트 방법
KR0170271B1 (ko) * 1995-12-30 1999-03-30 김광호 리던던트셀 테스트 제어회로를 구비하는 반도체 메모리장치
JP3223817B2 (ja) * 1996-11-08 2001-10-29 日本電気株式会社 半導体メモリ装置及びその駆動方法

Also Published As

Publication number Publication date
TW409256B (en) 2000-10-21
CN1217546A (zh) 1999-05-26
US5973990A (en) 1999-10-26
JPH11144497A (ja) 1999-05-28

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Granted publication date: 20030827