JPH11144497A - 同期型半導体記憶装置 - Google Patents

同期型半導体記憶装置

Info

Publication number
JPH11144497A
JPH11144497A JP9312355A JP31235597A JPH11144497A JP H11144497 A JPH11144497 A JP H11144497A JP 9312355 A JP9312355 A JP 9312355A JP 31235597 A JP31235597 A JP 31235597A JP H11144497 A JPH11144497 A JP H11144497A
Authority
JP
Japan
Prior art keywords
signal
output
test mode
activation
act
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9312355A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11144497A5 (https=
Inventor
Mikio Sakurai
幹夫 櫻井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9312355A priority Critical patent/JPH11144497A/ja
Priority to US09/060,311 priority patent/US5973990A/en
Priority to TW087107443A priority patent/TW409256B/zh
Priority to CN98116008A priority patent/CN1119816C/zh
Publication of JPH11144497A publication Critical patent/JPH11144497A/ja
Publication of JPH11144497A5 publication Critical patent/JPH11144497A5/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/12Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045Read-write mode select circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
JP9312355A 1997-11-13 1997-11-13 同期型半導体記憶装置 Pending JPH11144497A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP9312355A JPH11144497A (ja) 1997-11-13 1997-11-13 同期型半導体記憶装置
US09/060,311 US5973990A (en) 1997-11-13 1998-04-15 Synchronous semiconductor memory device including a circuit for arbitrarily controlling activation/inactivation timing of word line
TW087107443A TW409256B (en) 1997-11-13 1998-05-14 Synchronous semiconductor memory device
CN98116008A CN1119816C (zh) 1997-11-13 1998-07-13 有控制字线激活/非激活定时电路的同步型半导体存储器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9312355A JPH11144497A (ja) 1997-11-13 1997-11-13 同期型半導体記憶装置

Publications (2)

Publication Number Publication Date
JPH11144497A true JPH11144497A (ja) 1999-05-28
JPH11144497A5 JPH11144497A5 (https=) 2005-07-07

Family

ID=18028256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9312355A Pending JPH11144497A (ja) 1997-11-13 1997-11-13 同期型半導体記憶装置

Country Status (4)

Country Link
US (1) US5973990A (https=)
JP (1) JPH11144497A (https=)
CN (1) CN1119816C (https=)
TW (1) TW409256B (https=)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001126480A (ja) * 1999-10-29 2001-05-11 Fujitsu Ltd 半導体集積回路、半導体集積回路の制御方法、および可変遅延回路
JP2002170398A (ja) * 2000-11-30 2002-06-14 Fujitsu Ltd 同期型半導体装置、及び試験システム
US6868020B2 (en) 2002-07-09 2005-03-15 Elpida Memory, Inc. Synchronous semiconductor memory device having a desired-speed test mode
JP2006331511A (ja) * 2005-05-25 2006-12-07 Matsushita Electric Ind Co Ltd 半導体記憶装置およびその検査手法
WO2007099579A1 (ja) * 2006-02-28 2007-09-07 Fujitsu Limited Ramマクロ、そのタイミング生成回路
JP2008305531A (ja) * 2007-06-08 2008-12-18 Hynix Semiconductor Inc ワードライン駆動回路及びこれを備える半導体メモリ装置並びにそのテスト方法
JP2010027155A (ja) * 2008-07-22 2010-02-04 Sanyo Electric Co Ltd 半導体記憶装置
US8737158B2 (en) 2011-03-28 2014-05-27 Kinu MATSUNAGA Semiconductor device and method of controlling the same

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004063023A (ja) 2002-07-30 2004-02-26 Renesas Technology Corp 半導体記憶装置
JP3949081B2 (ja) * 2003-06-09 2007-07-25 株式会社東芝 サンプリング周波数変換装置
US7321991B2 (en) * 2004-01-10 2008-01-22 Hynix Semiconductor Inc. Semiconductor memory device having advanced test mode
KR100695512B1 (ko) * 2005-06-30 2007-03-15 주식회사 하이닉스반도체 반도체 메모리 장치
KR100885485B1 (ko) * 2007-09-03 2009-02-24 주식회사 하이닉스반도체 반도체 메모리장치
KR101188261B1 (ko) * 2010-07-30 2012-10-05 에스케이하이닉스 주식회사 멀티 비트 테스트 회로
KR101198139B1 (ko) * 2010-11-23 2012-11-12 에스케이하이닉스 주식회사 반도체 메모리 장치의 프리차지 신호 발생 회로
US9674086B2 (en) * 2013-11-05 2017-06-06 Cisco Technology, Inc. Work conserving schedular based on ranking
KR102471500B1 (ko) * 2018-03-12 2022-11-28 에스케이하이닉스 주식회사 반도체 장치 및 이를 포함하는 테스트 시스템
WO2020063413A1 (en) 2018-09-28 2020-04-02 Changxin Memory Technologies, Inc. Chip and chip test system
CN109164374B (zh) * 2018-09-28 2024-03-29 长鑫存储技术有限公司 芯片与芯片测试系统

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960016807B1 (ko) * 1994-06-30 1996-12-21 삼성전자 주식회사 반도체 메모리 장치의 리던던시 회로
JP2629645B2 (ja) * 1995-04-20 1997-07-09 日本電気株式会社 半導体記憶装置
US5621690A (en) * 1995-04-28 1997-04-15 Intel Corporation Nonvolatile memory blocking architecture and redundancy
KR100392687B1 (ko) * 1995-10-31 2003-11-28 마츠시타 덴끼 산교 가부시키가이샤 반도체 기억장치
KR0172423B1 (ko) * 1995-11-16 1999-03-30 김광호 고주파수 동작을 하는 반도체 메모리 장치의 테스트회로 및 테스트 방법
KR0170271B1 (ko) * 1995-12-30 1999-03-30 김광호 리던던트셀 테스트 제어회로를 구비하는 반도체 메모리장치
JP3223817B2 (ja) * 1996-11-08 2001-10-29 日本電気株式会社 半導体メモリ装置及びその駆動方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001126480A (ja) * 1999-10-29 2001-05-11 Fujitsu Ltd 半導体集積回路、半導体集積回路の制御方法、および可変遅延回路
JP2002170398A (ja) * 2000-11-30 2002-06-14 Fujitsu Ltd 同期型半導体装置、及び試験システム
US6868020B2 (en) 2002-07-09 2005-03-15 Elpida Memory, Inc. Synchronous semiconductor memory device having a desired-speed test mode
JP2006331511A (ja) * 2005-05-25 2006-12-07 Matsushita Electric Ind Co Ltd 半導体記憶装置およびその検査手法
WO2007099579A1 (ja) * 2006-02-28 2007-09-07 Fujitsu Limited Ramマクロ、そのタイミング生成回路
US8000157B2 (en) 2006-02-28 2011-08-16 Fujitsu Limited RAM macro and timing generating circuit thereof
JP2008305531A (ja) * 2007-06-08 2008-12-18 Hynix Semiconductor Inc ワードライン駆動回路及びこれを備える半導体メモリ装置並びにそのテスト方法
US8488380B2 (en) 2007-06-08 2013-07-16 Hynix Semiconductors Inc. Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device
JP2010027155A (ja) * 2008-07-22 2010-02-04 Sanyo Electric Co Ltd 半導体記憶装置
US8737158B2 (en) 2011-03-28 2014-05-27 Kinu MATSUNAGA Semiconductor device and method of controlling the same

Also Published As

Publication number Publication date
CN1119816C (zh) 2003-08-27
TW409256B (en) 2000-10-21
CN1217546A (zh) 1999-05-26
US5973990A (en) 1999-10-26

Similar Documents

Publication Publication Date Title
JPH11144497A (ja) 同期型半導体記憶装置
US8472263B2 (en) Mode-register reading controller and semiconductor memory device
US7609553B2 (en) NAND flash memory device with burst read latency function
JP2000311028A (ja) 位相制御回路、半導体装置及び半導体メモリ
JP3180317B2 (ja) 半導体記憶装置
US7466623B2 (en) Pseudo SRAM capable of operating in continuous burst mode and method of controlling burst mode operation thereof
JP3792602B2 (ja) 半導体記憶装置
JP2002343100A (ja) プリチャージ制御信号生成回路及びこれを用いた半導体メモリ装置
JP4544808B2 (ja) 半導体記憶装置の制御方法、および半導体記憶装置
KR20020014563A (ko) 반도체 메모리 장치
JP4061029B2 (ja) 半導体メモリ装置、バッファ及び信号伝送回路
KR100473747B1 (ko) 클럭 신호에 동기하여 동작하는 반도체 기억 장치
JP2004046927A (ja) 半導体記憶装置
JP6006911B2 (ja) 半導体記憶装置
KR20150009309A (ko) 반도체 장치 및 그를 포함하는 반도체 시스템
US6636455B2 (en) Semiconductor memory device that operates in synchronization with a clock signal
JP3123473B2 (ja) 半導体記憶装置
JP2002352597A (ja) 半導体記憶装置
JPH11149770A (ja) 同期型半導体記憶装置
JPH09180435A (ja) 半導体記憶装置
US7254090B2 (en) Semiconductor memory device
CN114121119B (zh) 用于提供数据速率操作的设备和方法
KR100282975B1 (ko) 워드선의 활성화/비활성화 타이밍을 임의로 제어하는 회로를 포함하는 동기형 반도체 기억 장치
US7823025B2 (en) Method and apparatus for testing a memory device
US6504767B1 (en) Double data rate memory device having output data path with different number of latches

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041110

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20041110

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070824

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071127

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080116

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090303

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090630