CN109755173A - 形成氧化硅层的方法 - Google Patents

形成氧化硅层的方法 Download PDF

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CN109755173A
CN109755173A CN201811181745.7A CN201811181745A CN109755173A CN 109755173 A CN109755173 A CN 109755173A CN 201811181745 A CN201811181745 A CN 201811181745A CN 109755173 A CN109755173 A CN 109755173A
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silicon oxide
oxide layer
oxygen
precursor
water
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彭羽筠
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

公开了一种形成氧化硅层及半导体结构的方法。所述形成氧化硅层的方法包括以下步骤。提供含硅前体、含氧前体以及氧自由基，以形成含有水的氧化硅层。对所述氧化硅层执行热工艺以使所述水扩散入所述氧化硅层中并利用所述水作为氧化剂来氧化所述氧化硅层。

Description

形成氧化硅层的方法
背景技术
一般来说，使用浅沟槽隔离(shallow trench isolation，STI)将半导体晶片上的有源区域彼此分离并隔离。目前通过以下方法形成该些浅沟槽隔离：对沟槽(有时被称为间隙)进行蚀刻，利用例如氧化物等介电质对所述沟槽进行过填充，然后利用例如化学机械抛光(chemical mechanical polishing，CMP)或蚀刻等工艺移除任何过量的介电质以移除位于所述沟槽外部的介电质。此介电质有助于使有源区域彼此电隔离。
然而，随着电路密度持续增大，该些间隙的宽度减小，从而增大了间隙高宽比，所述间隙高宽比通常被定义为间隙高度除以间隙宽度。因此，十分难以利用间隙填充介电材料完全地填充该些窄且深的间隙。不完全的填充会导致在间隙填充介电材料中产生不期望的空隙以及不连续性以及包含不期望的材料。该些空隙以及包含不期望材料导致在有源区域之间不充分的隔离。隔离不充分的装置的电效能不良且装置良率降低。
发明内容
根据本发明的实施例，一种形成氧化硅层的方法包括以下步骤。提供含硅前体、含氧前体以及氧自由基以形成含有水的氧化硅层。对所述氧化硅层执行热工艺以使所述水扩散入所述氧化硅层中并利用所述水作为氧化剂来氧化所述氧化硅层。
附图说明
结合附图阅读以下详细说明，会最好地理解本公开的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1是根据本公开的一些实施例，一种形成氧化硅层的方法的流程图。
图2示出根据本公开的一些实施例，一种形成氧化硅层的方法的时序图。
图3A到图3D是根据一些实施例，一种形成半导体结构的方法沿第一方向的剖视图。
图4是根据一些实施例，一种半导体结构沿与第一方向垂直的第二方向的剖视图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开内容。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第二特征形成在第一特征“上方”或第二特征“上”可包括其中第二特征及第一特征被形成为直接接触的实施例，且也可包括其中第二特征与第一特征之间可形成有附加特征、进而使得所述第二特征与所述第一特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
另外，在本文中为便于说明，可使用例如“在…下面(beneath)”、“在…之下(below)”、“下方的(lower)”、“在…上(on)”、“在…上方(over)”、“位于…上方(overlying)”、“在…之上(above)”、“上方的(upper)”等空间相对关系用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对关系用语旨在除图中所绘示的取向以外还包括装置在使用或操作中的不同取向。所述设备可具有其他取向(旋转90度或其他取向)，且本文中所用的空间相对关系描述语可同样相应地进行解释。
鳍可通过任意适当的方法被图案化。举例来说，鳍可利用包括双重图案化或多重图案化工艺的一个或多个光刻工艺而被图案化。一般来说，双重图案化或多重图案化工艺将光刻工艺与自对准工艺相组合，从而使得能够生成具有例如小于利用单一、直接光刻工艺所能获得的图案的节距的图案。举例来说，在一个实施例中，在衬底之上形成牺牲层并利用光刻工艺将所述牺牲层图案化。利用自对准工艺在经图案化的牺牲层旁边形成间隔件。然后移除所述牺牲层，且然后可使用剩余的间隔件来对鳍进行图案化。
图1是根据本公开的一些实施例，一种形成氧化硅层的方法的流程图。参照图1，在步骤S10处，向处理区提供含硅前体以及氧自由基以在沉积室中沉积可流动的氧化硅层。在一些实施例中，处理区是衬底或晶片。在一些实施例中，含硅前体是Si核心前体(即，Si原子在结构中是中心原子)、N核心前体(即，N原子在结构中是中心原子)、具有N-Si-N骨架的前体或其组合。在一些实施例中，Si核心前体可被写为化学式SiHx(R1)y(R2)z，其中R1是SiH3，R2是NH2、N(CH3)2或N(C2H5)2，且x+y+z＝4、x≥0、y≥0且z≥0。在一些实施例中，举例来说，Si核心前体是三甲基烷基胺(TSA)(SiH(SiH3)3)或过氢聚硅氨烷(SiH3(NH2))。在一些实施例中，N核心前体可被写为化学式N(SiH3)xRyHz，其中R是CH3或C2H5，且x+y+z＝3，x≥1。在一些实施例中，举例来说，N核心前体是二硅烷胺(DSA)(NH(SiH3)2)。在一些实施例中，具有N-Si-N骨架的前体可被写为化学式Si(NR)xHy，其中R是H、CH3或C2H5，且x+y＝4，x≥2。在一些实施例中，举例来说，具有N-Si-N骨架的前体是SiH2(NC2H5)2。
在一些实施例中，氧自由基是在沉积室外部的远端等离子体系统(remote plasmasystem，RPS)中产生并被输送到沉积室的处理区中。氧自由基可自含氧反应气体(例如，分子氧(O2)、臭氧(O3)、水蒸气(H2O)或双氧水(H2O2))产生。
在一些实施例中，可提供无氧反应气体，且所述无氧反应气体包括NH3、N2、H2等或其组合。在一些实施例中，无氧反应气体包括氮(例如NH3或N2)以及H2。在一些实施例中，无氧反应气体流经位于沉积室外部的远端等离子体系统(RPS)且其自由基被产生并输送到沉积室的处理区中。
也可包括一种或多种运载气体。所述运载气体可包括氦气(He)、氩气(Ar)、氮气(N2)等或其组合。在一些实施例中，沉积温度为40℃到150℃，例如50℃到100℃或60℃到120℃。
接下来，在步骤S20处，提供含氧前体以与沉积室的处理区中的氧自由基反应，从而在可流动的氧化硅层中形成水。在一些实施例中，含氧前体不含氮。在一些实施例中，含氧前体可为氧基硅烷、烷氧基硅烷等或其组合。在一些实施例中，氧基硅烷可被写为化学式Si(OR)x(OH)yHz，其中R为CH3、C2H5或C3H7，且x+y+z＝4，x≥1。在一些实施例中，氧基硅烷为Si(OCH3)4或Si(OC2H5)4。在一些实施例中，氧基硅烷也可为环形，例如(SiO)xH2x，其中4≦x≦8，例如(SiO)4H8。在一些实施例中，烷氧基硅烷可被写为化学式Si(CH3)x(OR)yHz，其中R是CH3、C2H5或C3H7，且x+y+z＝4，x≥1，y≥1。在一些实施例中，烷氧基硅烷是SiH(CH3)(OC2H5)2。在一些实施例中，烷氧基硅烷可也为环形，(SiO)xHy(CH3)z，其中3≦x≦8，y+z＝2x，例如即(SiO)3(CH3)。
当含氧前体(例如，Si-O-R)与氧自由基反应时，水为副产物。详细来说，反应机制包括如以下所示的烃类氧化、自缩合及/或醇缩合。
Si-O-R+O或H2O→Si-OH+R’O(烃类氧化)
Si-OH+Si-OH→Si-O-Si+H2O(自缩合)
Si-O-R+Si-OH→Si-O-Si+ROH ROH+O→CO2+H2O(醇缩合)
在处理区中，含硅前体在存在于处理区中的衬底或晶片上沉积可流动的氧化硅层，且然后含氧前体与氧自由基反应以在可流动的氧化硅层中形成水。由于硅层具有可流动的特性，因此所形成的水可轻易地扩散入可流动的氧化硅层中，且所形成的水实质上分散且嵌入在整个可流动的氧化硅层中。此外，可流动的氧化硅层的可流动性使得所述层能够流入位于衬底/晶片的处理区上的狭窄的间隙、沟槽及其他结构中。
在一些实施例中，在将水嵌入可流动的氧化硅层中之前，可流动的氧化硅层含有氮，且在所述层中的N-H键及Si-O键可由FTIR([N-H]：3260-3450cm-1，FWHM＝180～220cm-1；[Si-O]：1010-1080cm-1，FWHM＝60～100cm-1)以峰值高度比表征为[N-H]peak/[Si-O]peak。在一些实施例中，举例来说，[N-H]peak/[Si-O]peak的峰值高度比大于0.02。在一些实施例中，[N-H]peak/[Si-O]peak的峰值高度比是0.04到0.06或0.035到0.07。在通过含氧前体及氧自由基形成水之后，可流动的氧化硅层含有H2O，且在所述层中的水键可由FTIR([H2O]：3250-3420cm-1，FWHM＝400～500cm-1)以峰值高度比表征为[H2O]peak/[Si-O]peak。在一些实施例中，举例来说，[H2O]peak/[Si-O]peak的峰值高度比大于0.05。在一些实施例中，[H2O]peak/[Si-O]peak的峰值高度比是0.12到0.165或0.135到0.175。
图2示出根据本公开的一些实施例，一种形成氧化硅层的方法的时序图。沉积工艺基本上是通过重复至少一个沉积循环形成的。举例来说，沉积循环包括时间段t1到t3。在从时间段t1开始到时间段t3结束的整个沉积循环期间，以恒定的量将含硅前体及含氧反应气体提供到沉积室中，并沉积可流动的氧化硅层。此外，在整个沉积循环期间，提供含氧反应气体以使所述含氧反应气体流经远端等离子体系统以产生氧自由基及其他自由基。在整个沉积循环期间，以恒定的量提供无氧反应气体，且在时间段t2期间以增大的量提供含氧反应气体。在位于时间段t1与时间段t3之间的时间段t2中，以恒定的量将含氧前体提供到沉积室中。在一些实施例中，假设氧化硅层是通过将多个氧化硅层沉积到彼此之上而形成的，则举例来说在时间段t1期间，通过含硅前体及含氧反应气体形成第一氧化硅层。在时间段t2期间，通过含硅前体及含氧反应气体在第一氧化硅层之上形成第二氧化硅层。此外，在时间段t2期间，含氧前体与氧自由基反应以在第二氧化硅层中形成水。沉积第二氧化硅层的步骤与在第二氧化硅层中形成水的步骤并非实质上分离的，且沉积第二氧化硅层与形成水可同时发生，此使得水能够轻易地扩散到第二氧化硅层中。在时间段t3期间，通过含硅前体及含氧反应气体在含有水的第二氧化硅层之上形成第三氧化硅层。
在一些实施例中，对氧自由基的流动进行控制及优化以与含氧前体反应来形成一定量的水。换言之，与在整个沉积循环期间提供的含硅前体相比，伴随氧自由基的优化流动来周期性地提供含氧前体，以对可流动性进行微调并控制水量。在一些实施例中，时间段t1到t3可具有0.25<t2/(t1+t3)<4的关系，例如t2/(t1+t3)＝1或0.8，但本公开并不仅限于此。在时间段t3的末尾完成沉积循环。在一些实施例中，在相邻的两个沉积循环之间具有闲置时间段tidle。在闲置时间段tidle期间，全部停止提供含硅前体、含氧反应气体、无氧反应气体以及含氧前体，此使得可流动的氧化硅层能够流动，且因此可改善含有水的可流动的氧化硅层的可流动性。在一些替代实施例中，举例来说，闲置时间段tidle可为0。换言之，可在两个连续的沉积循环中无中断地始终提供含氧反应气体及无氧反应气体。重复沉积循环直到已在沉积室中的至少一个衬底上沉积了所需厚度的材料。在图2中，示出了三个沉积循环，但本公开并不仅限于此。
然后，在步骤S30处，在沉积工艺之后，对氧化硅层执行热工艺以使水扩散入所述氧化硅层中并利用所述水作为氧化剂来氧化所述氧化硅层。在一些实施例中，举例来说，在第二氧化硅层中的水扩散到第一氧化硅层、第二氧化硅层及第三氧化硅层中。在一些实施例中，由于水是在执行热工艺之前形成于可流动的氧化硅层中，因此可流动的氧化硅层可以高转化率被转换为具有高结构完整性的氧化硅层。在实施例中，在氧化之后，氧化硅层本质上由硅及氧组成。在一些实施例中，热工艺使得可流动的氧化硅层充分转变为具有更高密度、更强机械强度及更低湿蚀刻损失的氧化硅层。在一些实施例中，热工艺是退火工艺，且可在大于300℃的温度下执行。退火工艺可为湿退火或干退火。退火工艺可被执行大于30分钟的持续时间。在一些替代实施例中，在退火工艺中，可提供例如O2、O3或H2O等额外的含氧气体。在一些实施例中，在氮气环境中以介于400℃到450℃范围内的温度执行热工艺达30分钟到60分钟，且在所形成的氧化硅层中，举例来说，碳的原子百分比小于7％且介电常数介于3.65到4.0范围内。
在一些实施例中，热工艺是固化工艺。在一些实施例中，固化工艺是紫外固化工艺，且固化工艺可利用含氧气体(例如，O2、O3等或其组合)以及高导热性气体(例如，He、Ar等或其组合)执行。在一些实施例中，当热工艺是退火工艺时，可在退火工艺之后执行另外的固化工艺，以减小残余碳浓度并增大Si-O交联。在一些实施例中，在H2O环境中以介于550℃到650℃范围内的温度执行热工艺达30分钟到60分钟，然后在O2或O3环境中在300℃到400℃的温度下执行额外的紫外固化工艺达3分钟到5分钟以实现更高的密度，且在所形成的氧化硅层中，举例来说，碳的原子百分比小于2％且介电常数介于3.85到4.05范围内。
在一些实施例中，在沉积工艺之后，对氧化硅层执行表面稳定化处理。在一些实施例中，通过利用NH3、N2、H2或O2等离子体或浸入在O3或H2O等或其组合中而执行所述表面稳定化处理。
在一些实施例中，通过周期性地提供含氧前体以与氧自由基反应，在所形成的氧化硅层中形成水，并使水嵌入在所述氧化硅层中，因此省略了添加水，且不需要用于驱动H2O的高温及长周期的热退火工艺。此外，由于水均质性地(homogeneously)扩散到氧化硅层中，因此可实现高速及均质的氧化。因此，提高了所形成的氧化硅的例如碳含量及K值等特性且允许针对剩余半导体制造工艺的较高的热预算。
以上公开的用于形成可流动的层的方法可用于在金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)(例如，鳍场效应晶体管(Fin Field-Effect Transistor，FinFET))或其他半导体装置中形成浅沟槽隔离(STI)区及/或层间介电质(inter-layer dielectric，ILD)。
图3A到图3D是根据一些实施例，一种形成半导体结构的方法沿第一方向的剖视图。图4是根据一些实施例，一种半导体结构沿与第一方向垂直的第二方向的剖视图，且图3D及图4是同一半导体结构的剖视图。
参照图3A，在例如衬底110等材料层中形成至少一个开口112。在移除衬底110的一些部分之后，在衬底110中形成例如鳍114等三维结构。在一些实施例中，衬底110可为半导体衬底，例如块状半导体、绝缘体上半导体(semiconductor-on-insulator，SOI)衬底等，所述半导体衬底可为经掺杂的(例如，以p型掺杂剂或n型掺杂剂掺杂)或未经掺杂。一般来说，绝缘体上半导体衬底包括形成在绝缘体层上的半导体材料层。衬底110可为晶片，例如硅晶片。所述绝缘体层可为例如隐埋氧化物(buried oxide，BOX)层、氧化硅层等。将所述绝缘体层提供于衬底上，所述衬底通常为硅或玻璃衬底。也可使用其他衬底，例如多层式衬底或梯度衬底。在一些实施例中，衬底110的半导体材料可包括：硅；锗；包含碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟的化合物半导体；包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP的合金半导体；或其组合。在一些实施例中，可通过在衬底110中蚀刻沟槽而形成开口112。所述蚀刻可为任意可接受的蚀刻工艺，例如反应离子蚀刻(reactive ion etch，RIE)、中性束蚀刻(neutral beam etch，NBE)等或其组合。所述蚀刻可为各向异性的。
参照图3B，形成绝缘层120以填充开口112并覆盖例如鳍114等三维结构。在一些实施例中，在邻近的鳍114之间形成绝缘层120。在一些实施例中，绝缘层120是通过以上在图1及图2以及对应段落中所述的方法形成的氧化硅层。在一些实施例中，举例来说，开口112的宽度w大于6nm，且开口112的高宽比(高度h比上宽度w)大于8。在一些实施例中，可流动性被定义为T/T’，其中T是填充在开口112中的绝缘层120的平均厚度，且T’是位于例如鳍114等三维结构的顶部上的绝缘层120的平均厚度。在一些实施例中，举例来说，当宽度w是约100nm时，可流动性大于5或5.5。在一些替代实施例中，绝缘层120可为通过任意可接受的工艺形成的氧化物、氮化物等或其组合，且绝缘层120可通过高密度等离子体化学气相沉积(high density plasma chemical vapor deposition，HDP-CVD)等或其组合形成。
在一些实施例中，移除位于开口112之外的绝缘层120。在一些实施例中，例如化学机械抛光(CMP)等平坦化工艺可移除任意多余的绝缘层120并形成共面的绝缘层120的顶表面及鳍114的顶表面。
参照图3C，在一些实施例中，使绝缘层120凹陷以形成浅沟槽隔离(STI)区。绝缘层120被凹陷使得鳍114从邻近的绝缘层120之间突出。此外，绝缘层120的顶表面可具有平坦的表面(如图所示)、凸出的表面、凹进的表面(例如凹面)或其组合。绝缘层120的顶表面可通过恰当的蚀刻被形成为平坦的、凸出的及/或凹进的。绝缘层120可利用可接受的蚀刻工艺(例如，对绝缘层120的材料具有选择性的蚀刻工艺)形成凹陷。举例来说，可使用稀释氢氟酸(dHF)。
参照图3D及图4，然后在衬底110中局部地形成源极/漏极122，在衬底110上形成栅极124，并在栅极124与衬底110之间形成栅极介电层126。在一些实施例中，源极/漏极122可为外延源极/漏极区且可包含硅、SiC、SiCP或SiP等。栅极124可由例如TiN、TaN、TaC、Co、Ru、Al、其组合或其多个层等含金属材料制成。在一些替代实施例中，举例来说，可通过替换栅极工艺形成栅极124，也就是说，首先形成虚拟栅极，且然后由真正的栅极替换虚拟栅极。
在衬底110上方在源极/漏极122与栅极124之间的开口/间隙中形成层间介电质层128。在一些实施例中，层间介电质层128填充在衬底110上方在源极/漏极122与栅极124之间的开口/间隙，暴露出栅极124的顶表面并覆盖源极/漏极122的顶表面。形成层间介电质层130以覆盖层间介电质层128，且形成至少一个接触件132以贯穿层间介电质层128及130来电连接源极/漏极122。在一些实施例中，层间介电质层128及130可为氧化物(例如氧化硅)、氮化物等或其组合。在一些实施例中，层间介电质层128及130是通过以上在图1及对应的段落中所述的方法形成的氧化硅层。换言之，通过以上在图1中所述的方法形成的氧化硅层可形成在源极/漏极122与栅极124之间并覆盖栅极124或位于接触件132之间。在一些替代实施例中，层间介电质层128及130可通过高密度等离子体化学气相沉积(HDP-CVD)等或其组合形成。可使用通过任意可接受的工艺形成的其他硅氧化物。
尽管未明确示出，但所属领域中的普通技术人员将轻易地理解，可对图3D及图4中的结构执行进一步的处理步骤。举例来说，可在层间介电质层130上方形成各种金属间介电质(inter-metal dielectric，IMD)以及位于所述金属层介电质中的金属层。
在一些实施例中，在例如鳍场效应晶体管等半导体装置中的例如浅沟槽隔离区及/或层间介电质等绝缘特征可为通过以上在图1中所述的方法形成的氧化硅层。可流动的氧化硅层的可流动性使得膜能够流入位于衬底的沉积表面上的狭窄的间隙、沟槽及其他结构中。因此，所形成的绝缘特征具有良好的间隙填充性质且因此提供良好的绝缘。此外，简化了工艺，且可显著减小用于形成绝缘特征的成本及时间。
在一些实施例中，一种形成氧化硅层的方法包括以下步骤。提供含硅前体、含氧前体以及氧自由基以形成含有水的氧化硅层。对所述氧化硅层执行热工艺以使所述水扩散入所述氧化硅层中并利用所述水作为氧化剂来氧化所述氧化硅层。
在一些实施例中，所述含硅前体包含Si或N作为中心原子或N-Si-N骨架。
在一些实施例中，所述含氧前体包含氢。
在一些实施例中，所述含氧前体包含氧基硅烷或烷氧基硅烷。
在一些实施例中，所述含氧前体不含氮。
在一些实施例中，所述热工艺包括退火工艺、固化工艺或其组合。在一些实施例中，一种形成氧化硅层的方法包括以下步骤。执行至少一个沉积循环。所述沉积循环包括：始终提供含硅前体及氧自由基以沉积氧化硅层；以及周期性地提供含氧前体并增大所述氧自由基的量以在所述氧化硅层中形成水。对所述氧化硅层执行热工艺以使所述水扩散入所述氧化硅层中并利用所述水作为氧化剂来氧化所述氧化硅层。
在一些实施例中，在所述沉积循环之间存在闲置时间段，且在所述闲置时间段期间，停止提供所述含硅前体、所述氧自由基以及所述含氧前体。
在一些实施例中，在所述沉积循环期间所述含硅前体的量是恒定的。
在一些实施例中，所述氧自由基是自含氧气体产生的。
在一些实施例中，所述水是在沉积所述氧化硅层的同时形成的。
在一些实施例中，所述含硅前体包含Si或N作为中心原子或N-Si-N骨架。
在一些实施例中，所述含氧前体包含氧基硅烷或烷氧基硅烷。
在一些实施例中，所述氧化硅层是通过可流动的化学气相沉积工艺形成的。
在一些实施例中，一种形成半导体结构的方法包括以下步骤。以氧化硅层填充开口，其中形成所述氧化硅层的方法包括以下步骤。提供含硅前体、含氧前体以及氧自由基，以形成含有水的氧化硅层。对所述氧化硅层执行热工艺以使所述水扩散入所述氧化硅层中并利用所述水作为氧化剂来氧化所述氧化硅层。
在一些实施例中，所述含硅前体包含Si或N作为中心原子或N-Si-N骨架。
在一些实施例中，所述含氧前体包含氧基硅烷或烷氧基硅烷。
在一些实施例中，所述含氧前体不含氮。
在一些实施例中，所述氧化硅层是通过可流动的化学气相沉积工艺沉积的。
在一些实施例中，所述半导体结构是浅沟槽隔离或层间介电质。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应知，其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开的精神及范围，而且他们可在不背离本公开的精神及范围的条件下对其作出各种改变、代替、及变更。

Claims (1)

1.一种形成氧化硅层的方法，其特征在于，包括：
提供含硅前体、含氧前体以及氧自由基，以形成含有水的氧化硅层；以及
对所述氧化硅层执行热工艺以使所述水扩散入所述氧化硅层中并利用所述水作为氧化剂来氧化所述氧化硅层。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113841224A (zh) * 2019-03-22 2021-12-24 朗姆研究公司 提供掺杂硅的方法
JP2023521607A (ja) * 2020-03-31 2023-05-25 バーサム マテリアルズ ユーエス，リミティド ライアビリティ カンパニー 高い弾性率を有する膜を堆積するための新規な前駆体
CN115346915A (zh) * 2021-05-14 2022-11-15 联华电子股份有限公司 半导体器件的制造方法

Family Cites Families (94)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429077B1 (en) * 1999-12-02 2002-08-06 United Microelectronics Corp. Method of forming a lateral diffused metal-oxide semiconductor transistor
US6323121B1 (en) * 2000-05-12 2001-11-27 Taiwan Semiconductor Manufacturing Company Fully dry post-via-etch cleaning method for a damascene process
KR20030018134A (ko) * 2001-08-27 2003-03-06 한국전자통신연구원 조성과 도핑 농도의 제어를 위한 반도체 소자의 절연막형성 방법
US7335609B2 (en) * 2004-08-27 2008-02-26 Applied Materials, Inc. Gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials
US20070212850A1 (en) * 2002-09-19 2007-09-13 Applied Materials, Inc. Gap-fill depositions in the formation of silicon containing dielectric materials
US9257302B1 (en) * 2004-03-25 2016-02-09 Novellus Systems, Inc. CVD flowable gap fill
US7074690B1 (en) * 2004-03-25 2006-07-11 Novellus Systems, Inc. Selective gap-fill process
US7524735B1 (en) * 2004-03-25 2009-04-28 Novellus Systems, Inc Flowable film dielectric gap fill process
US7582555B1 (en) * 2005-12-29 2009-09-01 Novellus Systems, Inc. CVD flowable gap fill
US7521378B2 (en) * 2004-07-01 2009-04-21 Micron Technology, Inc. Low temperature process for polysilazane oxidation/densification
JP4595702B2 (ja) * 2004-07-15 2010-12-08 東京エレクトロン株式会社 成膜方法、成膜装置及び記憶媒体
US7642171B2 (en) * 2004-08-04 2010-01-05 Applied Materials, Inc. Multi-step anneal of thin films for film densification and improved gap-fill
US7087536B2 (en) * 2004-09-01 2006-08-08 Applied Materials Silicon oxide gapfill deposition using liquid precursors
US7148155B1 (en) * 2004-10-26 2006-12-12 Novellus Systems, Inc. Sequential deposition/anneal film densification method
US7825038B2 (en) * 2006-05-30 2010-11-02 Applied Materials, Inc. Chemical vapor deposition of high quality flow-like silicon dioxide using a silicon containing precursor and atomic oxygen
US7498273B2 (en) * 2006-05-30 2009-03-03 Applied Materials, Inc. Formation of high quality dielectric films of silicon dioxide for STI: usage of different siloxane-based precursors for harp II—remote plasma enhanced deposition processes
US7790634B2 (en) * 2006-05-30 2010-09-07 Applied Materials, Inc Method for depositing and curing low-k films for gapfill and conformal film applications
TWI462179B (zh) * 2006-09-28 2014-11-21 Tokyo Electron Ltd 用以形成氧化矽膜之成膜方法與裝置
US9245739B2 (en) * 2006-11-01 2016-01-26 Lam Research Corporation Low-K oxide deposition by hydrolysis and condensation
US7745352B2 (en) * 2007-08-27 2010-06-29 Applied Materials, Inc. Curing methods for silicon dioxide thin films deposited from alkoxysilane precursor with harp II process
US7867923B2 (en) * 2007-10-22 2011-01-11 Applied Materials, Inc. High quality silicon oxide films by remote plasma CVD from disilane precursors
US7943531B2 (en) * 2007-10-22 2011-05-17 Applied Materials, Inc. Methods for forming a silicon oxide layer over a substrate
US7803722B2 (en) * 2007-10-22 2010-09-28 Applied Materials, Inc Methods for forming a dielectric layer within trenches
US7541297B2 (en) * 2007-10-22 2009-06-02 Applied Materials, Inc. Method and system for improving dielectric film quality for void free gap fill
US8012887B2 (en) * 2008-12-18 2011-09-06 Applied Materials, Inc. Precursor addition to silicon oxide CVD for improved low temperature gapfill
KR101583608B1 (ko) * 2009-03-24 2016-01-08 삼성전자 주식회사 무기계 실리콘 전구체를 이용한 실리콘 산화막의 형성 방법및 이를 이용한 반도체 장치의 제조 방법
US8197915B2 (en) * 2009-04-01 2012-06-12 Asm Japan K.K. Method of depositing silicon oxide film by plasma enhanced atomic layer deposition at low temperature
JP4944228B2 (ja) * 2009-09-16 2012-05-30 株式会社日立国際電気 基板処理方法及び基板処理装置
US20110151677A1 (en) * 2009-12-21 2011-06-23 Applied Materials, Inc. Wet oxidation process performed on a dielectric material formed from a flowable cvd process
SG181670A1 (en) * 2009-12-30 2012-07-30 Applied Materials Inc Dielectric film growth with radicals produced using flexible nitrogen/hydrogen ratio
US8580699B2 (en) * 2010-09-10 2013-11-12 Applied Materials, Inc. Embedded catalyst for atomic layer deposition of silicon oxide
US20120083133A1 (en) * 2010-10-05 2012-04-05 Applied Materials, Inc. Amine curing silicon-nitride-hydride films
US8685867B1 (en) * 2010-12-09 2014-04-01 Novellus Systems, Inc. Premetal dielectric integration process
US9460913B2 (en) * 2010-12-27 2016-10-04 Tokyo Electron Limited Film-forming method for forming silicon oxide film on tungsten film or tungsten oxide film
US20120177846A1 (en) * 2011-01-07 2012-07-12 Applied Materials, Inc. Radical steam cvd
US8445078B2 (en) * 2011-04-20 2013-05-21 Applied Materials, Inc. Low temperature silicon oxide conversion
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US8466073B2 (en) * 2011-06-03 2013-06-18 Applied Materials, Inc. Capping layer for reduced outgassing
JP5959307B2 (ja) * 2011-06-22 2016-08-02 株式会社日立国際電気 半導体装置の製造方法、基板処理方法、基板処理装置およびプログラム
KR101829281B1 (ko) * 2011-06-29 2018-02-20 삼성전자주식회사 인-시츄 공정을 이용한 산화막/질화막/산화막(ｏｎｏ) 구조의 절연막 형성 방법
TWI541377B (zh) * 2011-11-04 2016-07-11 Ａｓｍ國際股份有限公司 形成摻雜二氧化矽薄膜的方法
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8871656B2 (en) * 2012-03-05 2014-10-28 Applied Materials, Inc. Flowable films using alternative silicon precursors
US8846536B2 (en) * 2012-03-05 2014-09-30 Novellus Systems, Inc. Flowable oxide film with tunable wet etch rate
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US8946095B2 (en) * 2012-10-25 2015-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming interlayer dielectric film above metal gate of semiconductor device
US9330899B2 (en) * 2012-11-01 2016-05-03 Asm Ip Holding B.V. Method of depositing thin film
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
JP6035166B2 (ja) * 2013-02-26 2016-11-30 株式会社日立国際電気 半導体装置の製造方法、基板処理装置およびプログラム
US20140302690A1 (en) * 2013-04-04 2014-10-09 Applied Materials, Inc. Chemical linkers to impart improved mechanical strength to flowable films
US9343293B2 (en) * 2013-04-04 2016-05-17 Applied Materials, Inc. Flowable silicon—carbon—oxygen layers for semiconductor processing
JP5998101B2 (ja) * 2013-05-24 2016-09-28 株式会社日立国際電気 半導体装置の製造方法、基板処理装置及びプログラム
US8975155B2 (en) * 2013-07-10 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a shallow trench isolation structure
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9786542B2 (en) * 2014-01-13 2017-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming semiconductor device having isolation structure
JP5852151B2 (ja) * 2014-02-12 2016-02-03 株式会社日立国際電気 半導体装置の製造方法、基板処理装置、プログラム及び記録媒体
JP5883049B2 (ja) * 2014-03-04 2016-03-09 株式会社日立国際電気 半導体装置の製造方法、基板処理装置、プログラムおよび記録媒体
JP2015179729A (ja) * 2014-03-19 2015-10-08 東京エレクトロン株式会社 シリコン酸化膜の形成方法およびその形成装置
JP6306411B2 (ja) * 2014-04-17 2018-04-04 株式会社日立国際電気 半導体装置の製造方法、基板処理装置およびプログラム
US10113236B2 (en) * 2014-05-14 2018-10-30 Applied Materials, Inc. Batch curing chamber with gas distribution and individual pumping
JP5886366B2 (ja) * 2014-06-04 2016-03-16 株式会社日立国際電気 半導体装置の製造方法、基板処理装置、プログラムおよび記録媒体
US9412581B2 (en) * 2014-07-16 2016-08-09 Applied Materials, Inc. Low-K dielectric gapfill by flowable deposition
US9875888B2 (en) * 2014-10-03 2018-01-23 Applied Materials, Inc. High temperature silicon oxide atomic layer deposition technology
US9564312B2 (en) * 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
JP6484478B2 (ja) * 2015-03-25 2019-03-13 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置およびプログラム
US10526701B2 (en) * 2015-07-09 2020-01-07 Lam Research Corporation Multi-cycle ALD process for film uniformity and thickness profile modulation
JP6506666B2 (ja) * 2015-09-25 2019-04-24 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置およびプログラム
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US9607837B1 (en) * 2015-12-21 2017-03-28 Asm Ip Holding B.V. Method for forming silicon oxide cap layer for solid state diffusion process
KR102458309B1 (ko) * 2015-12-28 2022-10-24 삼성전자주식회사 SiOCN 물질막의 형성 방법 및 반도체 소자의 제조 방법
JP6594804B2 (ja) * 2016-03-11 2019-10-23 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置およびプログラム
US9837267B2 (en) * 2016-04-29 2017-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Optical filtering for integrated dielectrics UV curing processes
US20170323785A1 (en) * 2016-05-06 2017-11-09 Lam Research Corporation Method to deposit conformal and low wet etch rate encapsulation layer using pecvd
US10468244B2 (en) * 2016-08-30 2019-11-05 Versum Materials Us, Llc Precursors and flowable CVD methods for making low-K films to fill surface features
US11017998B2 (en) * 2016-08-30 2021-05-25 Versum Materials Us, Llc Precursors and flowable CVD methods for making low-K films to fill surface features
DE102016124968B4 (de) * 2016-12-20 2024-01-18 Infineon Technologies Ag Ausbilden von Siliziumoxidschichten durch Oxidation mit Radikalen
US10269558B2 (en) * 2016-12-22 2019-04-23 Asm Ip Holding B.V. Method of forming a structure on a substrate
US10176984B2 (en) * 2017-02-14 2019-01-08 Lam Research Corporation Selective deposition of silicon oxide
JP6817845B2 (ja) * 2017-02-22 2021-01-20 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置およびプログラム
JP6853116B2 (ja) * 2017-05-31 2021-03-31 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置およびプログラム
US10361137B2 (en) * 2017-07-31 2019-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
JP6840051B2 (ja) * 2017-08-02 2021-03-10 東京エレクトロン株式会社 タングステン膜上へシリコン酸化膜を形成する方法および装置
JP6777614B2 (ja) * 2017-09-26 2020-10-28 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置、およびプログラム
US10290739B2 (en) * 2017-09-29 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Device and method of dielectric layer
US10304677B2 (en) * 2017-09-29 2019-05-28 Taiwan Semiconductor Manufacturing Co., Ltd. Low-k feature formation processes and structures formed thereby
US10957543B2 (en) * 2017-09-29 2021-03-23 Taiwan Semiconductor Manufacturing Co., Ltd. Device and method of dielectric layer
US10535512B2 (en) * 2017-11-21 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Formation method of semiconductor device with gate spacer
US11373866B2 (en) * 2018-06-29 2022-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Dielectric material and methods of forming same
US11043373B2 (en) * 2018-07-31 2021-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect system with improved low-k dielectrics
US10950426B2 (en) * 2018-08-14 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Dielectric layer, interconnection structure using the same, and manufacturing method thereof

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