CN107104144A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN107104144A
CN107104144A CN201610094545.2A CN201610094545A CN107104144A CN 107104144 A CN107104144 A CN 107104144A CN 201610094545 A CN201610094545 A CN 201610094545A CN 107104144 A CN107104144 A CN 107104144A
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layer
semiconductor device
dielectric layer
germanium layer
manufacture method
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CN107104144B (zh
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201610094545.2A priority Critical patent/CN107104144B/zh
Priority to US15/346,586 priority patent/US10026828B2/en
Priority to EP17156218.4A priority patent/EP3208830A1/en
Publication of CN107104144A publication Critical patent/CN107104144A/zh
Priority to US16/011,562 priority patent/US10615268B2/en
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Abstract

本公开公开了半导体装置及其制造方法。该方法包括:提供半导体结构,半导体结构包括:衬底结构;突出于衬底结构的一个或多个鳍片,每个鳍片包括至少在鳍片顶部的锗层;包绕在锗层上的伪栅极结构,伪栅极结构包括:伪栅极绝缘物、伪栅极和硬掩模;以及分别位于伪栅极结构的两侧的间隔物;在衬底结构上形成层间电介质层以覆盖伪栅极结构;在形成层间电介质层之后进行平坦化,以使得伪栅极的上表面露出;去除伪栅极和伪栅极绝缘物以露出其下的锗层的表面;对锗层的露出表面执行硅烷浸透处理,以对锗层的所述露出表面引入硅;对引入了硅的锗层的露出表面执行第一氧化处理,以在锗层的表面形成氧化物层,氧化物层包含硅元素和锗元素。

Description

半导体装置及其制造方法
技术领域
本公开涉及半导体技术领域,特别涉及半导体装置及其制造方法。
背景技术
随着半导体技术的发展,半导体装置的尺寸越来越小,在一些情况下还需要将高迁移率的材料(例如,用于形成沟道或沟道区)与高k(介电常数)介质层一同集成在衬底上。由于GaAs、InP、InGaAs、InAs和GaSb具有较高的电子迁移率,而Ge具有较高的空穴迁移率,因此可以以这些材料作为MOS晶体管的沟道。
目前,在一些装置的设计中,高k介质层与高迁移率衬底之间的界面将会影响半导体装置的性能和可靠性。
发明内容
本公开的发明人发现上述现有技术中存在问题,并因此针对所述问题中的至少一个问题提出了新的技术方案。
本公开一个实施例的目的之一是:提供一种半导体装置的制造方法。本公开一个实施例的目的之一是:提供一种半导体装置。根据本公开的实施例,可以改善高k介质层与高迁移率衬底之间的界面特性,减少界面缺陷,提高装置的可靠性。
根据本公开的第一方面,提供了一种半导体装置的制造方法包括:
提供半导体结构,所述半导体结构包括:
衬底结构,所述衬底结构包括衬底;
突出于所述衬底结构的一个或多个鳍片,所述一个或多个鳍片每个包括至少在鳍片顶部的锗层;
包绕在所述锗层上的伪栅极结构,所述伪栅极结构包括:
包绕在所述锗层上的伪栅极绝缘物、所述伪栅极绝缘物上的伪栅极、以及在伪栅极上的硬掩模;以及
分别位于所述伪栅极结构的源极侧和漏极侧的间隔物,所述间隔物覆盖所述锗层的其余部分;
在所述衬底结构上形成层间电介质层以覆盖所述伪栅极结构;
在形成层间电介质层之后进行平坦化,以使得所述伪栅极的上表面露出;
去除所述伪栅极和所述伪栅极绝缘物以露出其下的锗层的表面;
对所述锗层的露出表面执行硅烷浸透处理,以对所述锗层的所述露出表面引入硅;以及
对引入了硅的所述锗层的所述露出表面执行第一氧化处理,以在所述锗层的表面形成氧化物层,所述氧化物层包含硅元素和锗元素。
在一些实施例中,所述半导体结构还包括位于所述锗层两侧的与所述锗层邻接的源极和漏极。
在一些实施例中,所述一个或多个鳍片每个还包括在锗层下面的硅层。
在一些实施例中,所述硅烷浸透处理包括:在400℃至500℃的温度,将所述半导体结构沉浸在硅烷气氛中1分钟至30分钟,硅烷气氛的气压为5托至20托。
在一些实施例中,所述氧化物层包括:SiO2、GeO2和SiGeO2
在一些实施例中,所述半导体装置的制造方法还包括:对所述氧化物层执行氮化处理,以形成含氮的氧化物层。
在一些实施例中,利用氨气、一氧化二氮、一氧化氮或氮气等离子体执行所述氮化处理。
在一些实施例中,所述半导体装置的制造方法还包括:在所述氧化物层上和所述间隔物的侧壁上形成高k介质层。
在一些实施例中,所述半导体装置的制造方法还包括:在所述含氮的氧化物层上和所述间隔物的侧壁上形成高k介质层。
在一些实施例中,所述半导体装置的制造方法还包括:对所述高k介质层执行第二氧化处理,以减少所述高k介质层中的空位。
在一些实施例中,在氧气气氛下、在450℃至550℃的温度范围内执行所述第二氧化处理,其中,所述氧气的浓度小于10ppm。
在一些实施例中,所述半导体装置的制造方法还包括:在所述高k介质层上形成栅极。
在一些实施例中,所述一个或多个鳍片包括用于形成第一类型装置的第一组鳍片和用于形成第二类型装置的第二组鳍片。
在一些实施例中,所述衬底结构还包括形成在所述衬底上的电介质层,其中,所述一个或多个鳍片突出于所述电介质层,所述伪栅极绝缘物和所述伪栅极在所述电介质层上方。
在一些实施例中,所述源极和所述漏极的材料包括硅锗(SiGe)或硅磷(SiP)。
在一些实施例中,提供半导体结构的步骤包括:
提供初始结构,所述初始结构包括:衬底结构和突出于所述衬底结构的一个或多个初始鳍片,所述一个或多个初始鳍片包括半导体层;
在所述半导体层的表面上形成初始锗层;
形成包绕在所述初始锗层上的伪栅极绝缘物层、所述伪栅极绝缘物层上的伪栅极材料层、以及在所述伪栅极材料层上的硬掩模层;
利用图案化的掩模蚀刻所述硬掩模层、所述伪栅极材料层和所述伪栅极绝缘物层以形成伪栅极结构;
分别在所述伪栅极结构的源极侧和漏极侧形成所述间隔物;以及
利用所述伪栅极结构以及所述间隔物作为掩模,蚀刻所述初始锗层和所述初始锗层下的半导体层。
在一些实施例中,所述一个或多个鳍片每个包括在鳍片的横向截面的表面处的锗层。
根据本公开的第二方面,提供了一种半导体装置,包括:
衬底结构,所述衬底结构包括衬底;
突出于所述衬底结构的一个或多个鳍片,所述一个或多个鳍片每个包括至少在鳍片顶部的锗层;
在所述锗层上两侧的间隔物,以及在所述锗层的未被间隔物覆盖的表面上的氧化物层,所述氧化物层包含硅元素和锗元素;以及
在所述氧化物层上和所述间隔物内侧侧壁上的高k介质层,和在所述高k介质层上的栅极,其中所述高k介质层和所述栅极在所述间隔物之间,并且,其中部分的所述高k介质层插入在所述栅极与所述间隔物之间。
在一些实施例中,所述氧化物层为含氮的氧化物层。
在一些实施例中,所述半导体装置还包括:位于所述间隔物相对于所述栅极的外侧的源极和漏极,所述锗层在所述源极和所述漏极之间并且与所述源极和所述漏极邻接。
在一些实施例中,所述一个或多个鳍片每个还包括在锗层下面的硅层。
在一些实施例中,所述一个或多个鳍片包括用于形成第一类型装置的第一组鳍片和用于形成第二类型装置的第二组鳍片。
在一些实施例中,所述衬底结构还包括形成在所述衬底上的电介质层,其中,所述一个或多个鳍片突出于所述电介质层,所述氧化物层、所述高k介质层和所述栅极在所述电介质层的上方。
在一些实施例中,所述源极和所述漏极的材料包括SiGe或SiP。
在一些实施例中,所述半导体装置还包括:在所述衬底结构上的层间电介质层,所述层间电介质层围绕所述间隔物以及所述高k介质层和所述栅极。
在一些实施例中,所述一个或多个鳍片每个包括在鳍片的横向截面的表面处的锗层。
本公开的实施例可以减少鳍片中的锗层的界面缺陷密度,从而可以提高半导体装置的可靠性。
进一步地,减少氧化物层的缺陷态密度,可以减少界面层(即该含氮的氧化物层)的等效氧化物层厚度,从而可以提高装置的性能。
另外,减少了高k介质层中的空位,也可以进一步提高装置的可靠性。
通过以下参照附图对本公开的示例性实施例的详细描述,本公开的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本公开的实施例,并且连同说明书一起用于解释本公开的原理。
参照附图,根据下面的详细描述,可以更加清楚地理解本公开,其中:
图1是示出根据本公开一些实施例的半导体装置的制造方法的流程图。
图2是示意性地示出根据本公开一些实施例的半导体装置的制造过程中一个阶段的结构的横截面示意图。
图3是示意性地示出根据本公开一些实施例的半导体装置的制造过程中一个阶段的结构的横截面示意图。
图4是示意性地示出根据本公开一些实施例的半导体装置的制造过程中一个阶段的结构的横截面示意图。
图5是示意性地示出根据本公开一些实施例的半导体装置的制造过程中一个阶段的结构的横截面示意图。
图6是示意性地示出根据本公开一些实施例的半导体装置的制造过程中一个阶段的结构的横截面示意图。
图7是示意性地示出根据本公开一些实施例的半导体装置的制造过程中一个阶段的结构的横截面示意图。
图8是示意性地示出根据本公开一些实施例的半导体装置的制造过程中一个阶段的结构的横截面示意图。
图9是示意性地示出根据本公开一些实施例的半导体装置的制造过程中一个阶段的结构的横截面示意图。
图10是示意性地示出根据本公开一些实施例的半导体装置的制造过程中一个阶段的结构的横截面示意图。
图11A是示意性地示出根据本公开一些实施例的半导体结构的制造过程中一个阶段的结构的横截面示意图。
图11B是示意性地示出根据本公开一些实施例的半导体结构的制造过程中一个阶段的结构的横截面示意图。
图11C是示意性地示出根据本公开一些实施例的半导体结构的制造过程中一个阶段的结构的横截面示意图。
图11D是示意性地示出根据本公开一些实施例的半导体结构的制造过程中一个阶段的结构的横截面示意图。
图11E是示意性地示出根据本公开一些实施例的半导体结构的制造过程中一个阶段的结构的横截面示意图。
图11F是示意性地示出根据本公开一些实施例的半导体结构的制造过程中一个阶段的结构的横截面示意图。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。应注意到:除非另外具体说明,否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本公开的范围。
同时,应当明白,为了便于描述,附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的,决不作为对本公开及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论,但在适当情况下,所述技术、方法和设备应当被视为授权说明书的一部分。
在这里示出和讨论的所有示例中,任何具体值应被解释为仅仅是示例性的,而不是作为限制。因此,示例性实施例的其它示例可以具有不同的值。
应注意到:相似的标号和字母在下面的附图中表示类似项,因此,一旦某一项在一个附图中被定义,则在随后的附图中不需要对其进行进一步讨论。
图1是示出根据本公开一些实施例的半导体装置的制造方法的流程图。图2至图10是示意性地示出根据本公开一些实施例的半导体装置的制造过程中若干阶段的结构的横截面示意图。
如图1所示,在步骤S101,提供半导体结构。如图2所示,图2中示出了半导体结构20。该半导体结构20可以包括:衬底结构30。该衬底结构30包括衬底(例如硅)31。该半导体结构20还可以包括突出于衬底结构30的一个或多个鳍片40,所述一个或多个鳍片每个包括至少在鳍片顶部的锗层41。该半导体结构20还可以包括包绕在锗层41上的伪栅极结构50。该伪栅极结构50可以包括:包绕在锗层41上的伪栅极绝缘物(例如二氧化硅)51、伪栅极绝缘物51上的伪栅极(例如多晶硅)52、以及在伪栅极52上的硬掩模(例如氮化硅)53。该半导体结构20还可以包括分别位于伪栅极结构50的源极侧和漏极侧的间隔物56,该间隔物56覆盖锗层41的其余部分。例如,间隔物可以是一层或多层。
这里需要注意的是,图2所示的截面是沿着鳍片纵向(纵轴)的截面;而鳍片和锗层的横向截面可以从图11B最佳地看出。关于根据本公开一些实施例的半导体结构的制造过程的细节将在下文中结合图11A至图11E详细描述。
在本公开的一些实施例中,所述一个或多个鳍片每个包括在鳍片的横向截面的表面处的锗层。
在本公开的一些实施例中,如图2所示,所述一个或多个鳍片每个还可以包括在锗层41下面的硅层42。
在本公开的一些实施例中,如图2所示,所述一个或多个鳍片40可以包括用于形成第一类型装置(例如NOMS晶体管)的第一组鳍片91和用于形成第二类型装置(例如PMOS晶体管)的第二组鳍片92。
在本公开的一些实施例中,如图2所示,衬底结构30还可以包括形成在衬底31上的电介质层(例如二氧化硅)32。在这种情况下,所述一个或多个鳍片突出于电介质层32,伪栅极绝缘物51和伪栅极52在该电介质层32上方。
应理解,在本文中,术语“鳍片”常常是指突出于衬底结构(其包括衬底或者包括衬底以及衬底上电介质层)的鳍片部分,以便于说明;但有时也泛指广义的鳍片。
在本公开的一些实施例中,半导体结构20还可以包括位于锗层41两侧的与锗层41邻接的源极和漏极。例如,如图2所示,在第一组鳍片91中,半导体结构20可以包括位于锗层41两侧的与锗层41邻接的第一源极61和第一漏极62,以及在第二组鳍片92中半导体结构20可以包括位于锗层41两侧的与锗层41邻接的第二源极71和第二漏极72。
在一些实施例中,源极和漏极的材料可以包括硅锗(SiGe)或硅磷(SiP),以向沟道区施加应力。例如,如图2所示,第一源极61和第一漏极62的材料可以为SiP,第二源极71和第二漏极72的材料可以为SiGe。这里,应理解,源极和漏极可以从例如硅层41生长而来。可以在生长过程中,对源极和漏极进行原位掺杂。
作为示意,图2中还示出了第一源极61中的重掺杂区63、第一漏极62中的重掺杂区64、第二源极71中的重掺杂区73、以及第二漏极72中的重掺杂区74。
回到图1,在步骤S102,在衬底结构上形成层间电介质层以覆盖伪栅极结构。
图3示意性地示出了在步骤S102中形成的结构。例如,如图3所示,在衬底结构30上例如通过沉积来形成层间电介质层45以覆盖伪栅极结构50。例如,层间电介质层的材料可以为二氧化硅。
回到图1,在步骤S103,在形成层间电介质层之后进行平坦化,以使得伪栅极的上表面露出。
图4示意性地示出了在步骤S103中形成的结构。例如,如图4所示,在形成层间电介质层之后进行平坦化(例如化学机械平坦化(Chemical Mechanical Planarization,CMP)),以使得伪栅极52的上表面露出。
回到图1,在步骤S104,去除伪栅极和伪栅极绝缘物以露出其下的锗层的表面。
图5示意性地示出了在步骤S104中形成的结构。例如,如图5所示,去除伪栅极52和伪栅极绝缘物51以露出其下的锗层41的表面。
回到图1,在步骤S105,对锗层的露出表面执行硅烷浸透处理,以对锗层的该露出表面引入硅。
图6示意性地示出了在步骤S105中形成的结构。例如,如图6所示,对锗层41的露出表面执行硅烷浸透处理,以对锗层的露出表面引入硅,例如形成如图6所示的包含硅和锗的第一表层47。
在本公开的实施例中,该硅烷浸透处理可以包括:在400℃至500℃的温度,将半导体结构沉浸在硅烷气氛中1分钟至30分钟(例如5分钟、10分钟或20分钟),硅烷气氛的气压为5托至20托。优选地,该硅烷浸透处理的温度为450℃。优选地,该硅烷浸透处理的硅烷气氛的气压为10托。从而,硅(硅烷)可以吸附在锗层的表面,或者进入锗层表面例如1nm以内。
回到图1,在步骤S106,对引入了硅的锗层的露出表面执行第一氧化处理,以在锗层的表面形成氧化物层,该氧化物层包含硅元素和锗元素。
图7示意性地示出了在步骤S106中形成的结构。例如,如图7所示,对引入了硅的锗层的露出表面(即第一表层47)执行第一氧化处理,以在锗层的表面形成氧化物层49,该氧化物层49包含硅元素和锗元素。该氧化物层可以包括硅和锗的氧化物,包括但不限于:SiO2、GeO2和SiGeO2。例如,该第一氧化处理可以采用原位水汽生成(In-situSteam Generation,ISSG)工艺或者采用快速热氧化(Rapid ThermalOxidation,RTO)来实施。例如该氧化物层的厚度可以为
至此,提供了根据本公开一些实施例的半导体装置的制造方法。该制造方法可以减少鳍片中的锗层的表面(界面)缺陷,降低缺陷密度,从而可以提高在此基础上形成的半导体装置的性能和可靠性。
在本公开的一些实施例中,如图8所示,半导体装置的制造方法还可以包括:对氧化物层49执行氮化处理,以形成含氮的氧化物层81。例如,利用氨气、一氧化二氮、一氧化氮或氮气等离子体执行该氮化处理。该氮化处理可以改善氧化物层的膜特性,可以减少该含氧化物层的等效氧化物厚度(Equivalent Oxide Thickness,简称为EOT),和/或可以进一步改善锗层与该氧化物层(含氮的氧化物层)的界面的界面特性,从而可以进一步提高装置的性能和可靠性。
接下来,如图9所示,本公开实施例的制造方法还可以包括:在含氮的氧化物层81上和间隔物56的侧壁(内侧侧壁)上形成高k介质层83。这里需要注意的是,内侧侧壁指的是间隔物面向凹陷或者栅极或者伪栅极的侧壁。
在另一些实施例中,可以在氧化物层上和间隔物的侧壁上形成高k介质层。即在未经过氮化处理的氧化物层上和间隔物的侧壁上形成高k介质层。
接下来,本公开实施例的制造方法还可以包括:对高k介质层83执行第二氧化处理,以减少该高k介质层中的空位。在一些实施例中,在氧气气氛下、在450℃至550℃的温度范围内执行第二氧化处理。优选地,第二氧化处理的温度可以为500℃。例如,氧气的浓度可以小于10ppm。通过第二氧化处理,可以补充高k介质层中的氧空位,从而提高装置的可靠性。
接下来,如图10所示,本公开实施例的制造方法还可以包括:在高k介质层上形成栅极85。该栅极为导电栅极。这里,栅极可以包括金属栅极以及在金属栅极与高k介质层之间的其它导电功能层(如果有的话,例如TaN缓冲层、功函数调节层等)。该金属栅极的材料可以包括:铜或铝等金属。例如可以先在图10所示的结构上沉积功能层材料(如果有的话)以及栅极材料,然后对其进行平坦化(例如CMP)以形成栅极。
至此,提供了根据本公开另一些实施例的半导体装置的制造方法。该制造方法可以减少氧化物层的缺陷态密度,减少高k介质层中的空位,从而提高装置的可靠性。
图11A至图11F是示意性地示出根据本公开一些实施例的半导体结构的制造过程中若干阶段的结构的截面示意图。
首先,如图11A所示,提供初始结构100,该初始结构100可以包括:衬底结构30和突出于该衬底结构30的一个或多个初始鳍片,所述一个或多个初始鳍片包括半导体层42。例如,该半导体层可以为硅层、硅锗层或其他类似的半导体层。该衬底结构30包括衬底(例如硅)31。在本公开的实施例中,如图11A所示,衬底结构30还可以包括形成在衬底31上的电介质层(例如二氧化硅)32,其中所述一个或多个初始鳍片突出于电介质层32。应理解,尽管这里衬底31被示出为基于体硅衬底,然而本公开不限于此。例如,衬底31也可以是绝缘体上硅衬底,在这种情况的一种实现方式中,鳍片可以形成在埋氧层(绝缘层)之上,从而可以不需要电介质层32。
在本公开的实施例中,如图11A所示,所述一个或多个初始鳍片可以包括用于形成第一类型装置(例如NOMS晶体管)的第一组鳍片91和用于形成第二类型装置(例如PMOS晶体管)的第二组鳍片92。
接下来,如图11B所示,在半导体层42的表面上形成初始锗层41。在一些实施例中,可以采用外延生长的工艺在半导体层42的顶部形成初始锗层41。例如该半导体层可以为硅层,在硅烷和锗烷的混合气体中进行外延生长,并且控制硅烷和锗烷的浓度比随时间逐渐减小,即锗烷的含量越来越大,直至最后硅烷的含量为零,从而外延生长出该初始锗层41。应理解,形成初始锗层的方法不限于此。
接下来,如图11C所示,形成包绕在初始锗层41上的伪栅极绝缘物层51、伪栅极绝缘物层51上的伪栅极材料层52、以及在伪栅极材料层52上的硬掩模层53。例如,可以在初始锗层41上沉积形成伪栅极绝缘物层51,在伪栅极绝缘物层51上沉积形成伪栅极材料层52,以及在伪栅极材料层52上沉积形成硬掩模层53。
接下来,利用图案化的掩模(图11D未示出)蚀刻硬掩模层53、伪栅极材料层52和伪栅极绝缘物层51以形成伪栅极结构50,如图11D所示。该伪栅极结构50包括:伪栅极绝缘物51、伪栅极52、以及硬掩模53。为了描述的方便,图11D中示出的结构的视图是图11C的结构分别沿着A-A’方向和B-B’方向截取的横截面的视图,其中图11D中的第一组鳍片的视图是图11C的第一组鳍片沿着A-A’方向截取的横截面的视图,图11D中的第二组鳍片的视图是图11C的第二组鳍片沿着B-B’方向截取的横截面的视图。
接下来,如图11E所示,分别在伪栅极结构50的源极侧和漏极侧形成间隔物56。
接下来,如图11F所示,利用伪栅极结构50以及间隔物56作为掩模,蚀刻初始锗层41和初始锗层41下的半导体层42。
至此,提供了根据本公开一些实施例的半导体结构的制造方法。
可选地,半导体结构的制造方法还可以包括:在剩余的初始锗层两侧形成与锗层邻接的源极和漏极,以及源极中的重掺杂区和漏极中的重掺杂区。关于形成源极、漏极、源极中的重掺杂区、以及漏极中的重掺杂区的方法为本领域技术人员已知的技术,这里不再赘述。
至此,还应理解,本公开还提供了一种半导体装置,例如如图10所示,该半导体装置包括:衬底结构30,该衬底结构可以包括衬底(例如)31。该半导体装置还可以包括突出于衬底结构30的一个或多个鳍片40,所述一个或多个鳍片40每个包括至少在鳍片顶部的锗层41。该半导体装置还可以包括在锗层41上两侧的间隔物56,以及在锗层41的未被间隔物56覆盖的表面上的氧化物层,该氧化物层包含硅元素和锗元素。例如,该氧化物层可以为含氮的氧化物层81。该半导体装置还可以包括在氧化物层上和间隔物内侧侧壁上的高k介质层83,和在高k介质层83上的栅极85,其中该高k介质层和该栅极在间隔物56之间,并且,其中部分的高k介质层插入在栅极与间隔物之间。例如,间隔物可以是一层或多层。该实施例中减少了界面的缺陷态,从而提高了装置的可靠性。
在一些实施例中,该高k介质层83经过了氧化处理,减少高k介质层中的空位,提高了装置的可靠性。
在本公开的一些实施例中,所述一个或多个鳍片每个包括在鳍片的横向截面的表面处的锗层。
在本公开的一些实施例中,如图10所示,所述一个或多个鳍片每个还包括在锗层41下面的硅层42。
在本公开的一些实施例中,如图10所示,衬底结构30还可以包括形成在衬底31上的电介质层32。所述一个或多个鳍片40突出于电介质层32,氧化物层(例如含氮的氧化物层81)、高k介质层83和栅极85在电介质层32上方。
在本公开的一些实施例中,如图10所示,所述一个或多个鳍片40可以包括用于形成第一类型装置(例如NOMS晶体管)的第一组鳍片91和用于形成第二类型装置(例如PMOS晶体管)的第二组鳍片92。
在本公开的一些实施例中,该半导体装置还可以包括:位于间隔物56相对于栅极85的外侧的源极和漏极,锗层41在源极和漏极之间并且与源极和漏极邻接。例如,图10示出了第一组鳍片91中的位于锗层41两侧的与锗层41邻接的第一源极61和第一漏极62,以及在第二组鳍片92中的位于锗层41两侧的与锗层41邻接的第二源极71和第二漏极72。
在本公开的一些实施例中,源极和漏极的材料包括SiGe或SiP。例如,第一源极61和第一漏极62的材料可以为SiP,第二源极71和第二漏极72的材料可以为SiGe。
在本公开的一些实施例中,该半导体装置还可以包括:源极中的重掺杂区和漏极中的重掺杂区。例如如图10所示,该半导体装置还可以包括:第一源极61中的重掺杂区63、第一漏极62中的重掺杂区64、第二源极71中的重掺杂区73、以及第二漏极72中的重掺杂区74。
在本公开的一些实施例中,该半导体装置还可以包括在衬底结构上的层间电介质层45,该层间电介质层45围绕间隔物56以及高k介质层83和栅极85。
至此,已经详细描述了根据本公开的制造半导体装置的方法和所形成的半导体装置。为了避免遮蔽本公开的构思,没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述,完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明,但是本领域的技术人员应该理解,以上示例仅是为了进行说明,而不是为了限制本公开的范围。本领域的技术人员应该理解,可在不脱离本公开的范围和精神的情况下,对以上实施例进行修改。本公开的范围由所附权利要求来限定。

Claims (26)

1.一种半导体装置的制造方法,其特征在于,包括:
提供半导体结构,所述半导体结构包括:
衬底结构,所述衬底结构包括衬底;
突出于所述衬底结构的一个或多个鳍片,所述一个或多个鳍片每个包括至少在鳍片顶部的锗层;
包绕在所述锗层上的伪栅极结构,所述伪栅极结构包括:包绕在所述锗层上的伪栅极绝缘物、所述伪栅极绝缘物上的伪栅极、以及在伪栅极上的硬掩模;以及
分别位于所述伪栅极结构的源极侧和漏极侧的间隔物,所述间隔物覆盖所述锗层的其余部分;
在所述衬底结构上形成层间电介质层以覆盖所述伪栅极结构;
在形成层间电介质层之后进行平坦化,以使得所述伪栅极的上表面露出;
去除所述伪栅极和所述伪栅极绝缘物以露出其下的锗层的表面;
对所述锗层的露出表面执行硅烷浸透处理,以对所述锗层的所述露出表面引入硅;以及
对引入了硅的所述锗层的所述露出表面执行第一氧化处理,以在所述锗层的表面形成氧化物层,所述氧化物层包含硅元素和锗元素。
2.根据权利要求1所述半导体装置的制造方法,其特征在于,
所述半导体结构还包括位于所述锗层两侧的与所述锗层邻接的源极和漏极。
3.根据权利要求1所述半导体装置的制造方法,其特征在于,
所述一个或多个鳍片每个还包括在锗层下面的硅层。
4.根据权利要求1所述半导体装置的制造方法,其特征在于,
所述硅烷浸透处理包括:在400℃至500℃的温度,将所述半导体结构沉浸在硅烷气氛中1分钟至30分钟,硅烷气氛的气压为5托至20托。
5.根据权利要求1所述半导体装置的制造方法,其特征在于,所述氧化物层包括:SiO2、GeO2和SiGeO2
6.根据权利要求1所述半导体装置的制造方法,其特征在于,还包括:
对所述氧化物层执行氮化处理,以形成含氮的氧化物层。
7.根据权利要求6所述半导体装置的制造方法,其特征在于,
利用氨气、一氧化二氮、一氧化氮或氮气等离子体执行所述氮化处理。
8.根据权利要求1所述半导体装置的制造方法,其特征在于,还包括:
在所述氧化物层上和所述间隔物的侧壁上形成高k介质层。
9.根据权利要求6所述半导体装置的制造方法,其特征在于,还包括:
在所述含氮的氧化物层上和所述间隔物的侧壁上形成高k介质层。
10.根据权利要求8或9所述半导体装置的制造方法,其特征在于,还包括:
对所述高k介质层执行第二氧化处理,以减少所述高k介质层中的空位。
11.根据权利要求10所述半导体装置的制造方法,其特征在于,
在氧气气氛下、在450℃至550℃的温度范围内执行所述第二氧化处理,
其中,所述氧气的浓度小于10ppm。
12.根据权利要求10所述半导体装置的制造方法,其特征在于,还包括:
在所述高k介质层上形成栅极。
13.根据权利要求1所述半导体装置的制造方法,其特征在于,
所述一个或多个鳍片包括用于形成第一类型装置的第一组鳍片和用于形成第二类型装置的第二组鳍片。
14.根据权利要求1所述半导体装置的制造方法,其特征在于,
所述衬底结构还包括形成在所述衬底上的电介质层,
其中,所述一个或多个鳍片突出于所述电介质层,所述伪栅极绝缘物和所述伪栅极在所述电介质层上方。
15.根据权利要求2所述半导体装置的制造方法,其特征在于,
所述源极和所述漏极的材料包括硅锗(SiGe)或硅磷(SiP)。
16.根据权利要求1所述半导体装置的制造方法,其特征在于,提供半导体结构的步骤包括:
提供初始结构,所述初始结构包括:衬底结构和突出于所述衬底结构的一个或多个初始鳍片,所述一个或多个初始鳍片包括半导体层;
在所述半导体层的表面上形成初始锗层;
形成包绕在所述初始锗层上的伪栅极绝缘物层、所述伪栅极绝缘物层上的伪栅极材料层、以及在所述伪栅极材料层上的硬掩模层;
利用图案化的掩模蚀刻所述硬掩模层、所述伪栅极材料层和所述伪栅极绝缘物层以形成伪栅极结构;
分别在所述伪栅极结构的源极侧和漏极侧形成所述间隔物;以及
利用所述伪栅极结构以及所述间隔物作为掩模,蚀刻所述初始锗层和所述初始锗层下的半导体层。
17.根据权利要求1所述半导体装置的制造方法,其特征在于,
所述一个或多个鳍片每个包括在鳍片的横向截面的表面处的锗层。
18.一种半导体装置,其特征在于,包括:
衬底结构,所述衬底结构包括衬底;
突出于所述衬底结构的一个或多个鳍片,所述一个或多个鳍片每个包括至少在鳍片顶部的锗层;
在所述锗层上两侧的间隔物,以及在所述锗层的未被间隔物覆盖的表面上的氧化物层,所述氧化物层包含硅元素和锗元素;以及
在所述氧化物层上和所述间隔物内侧侧壁上的高k介质层,和在所述高k介质层上的栅极,其中所述高k介质层和所述栅极在所述间隔物之间,并且,其中部分的所述高k介质层插入在所述栅极与所述间隔物之间。
19.根据权利要求18所述半导体装置,其特征在于,
所述氧化物层为含氮的氧化物层。
20.根据权利要求18所述半导体装置,其特征在于,还包括:
位于所述间隔物相对于所述栅极的外侧的源极和漏极,所述锗层在所述源极和所述漏极之间并且与所述源极和所述漏极邻接。
21.根据权利要求18所述半导体装置,其特征在于,
所述一个或多个鳍片每个还包括在锗层下面的硅层。
22.根据权利要求18所述半导体装置,其特征在于,
所述一个或多个鳍片包括用于形成第一类型装置的第一组鳍片和用于形成第二类型装置的第二组鳍片。
23.根据权利要求18所述半导体装置,其特征在于,
所述衬底结构还包括形成在所述衬底上的电介质层,
其中,所述一个或多个鳍片突出于所述电介质层,所述氧化物层、所述高k介质层和所述栅极在所述电介质层的上方。
24.根据权利要求20所述半导体装置,其特征在于,
所述源极和所述漏极的材料包括SiGe或SiP。
25.根据权利要求18所述半导体装置,其特征在于,还包括:
在所述衬底结构上的层间电介质层,所述层间电介质层围绕所述间隔物以及所述高k介质层和所述栅极。
26.根据权利要求18所述半导体装置,其特征在于,
所述一个或多个鳍片每个包括在鳍片的横向截面的表面处的锗层。
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