TW202034378A - 積體電路裝置及其形成方法 - Google Patents
積體電路裝置及其形成方法 Download PDFInfo
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- TW202034378A TW202034378A TW108137411A TW108137411A TW202034378A TW 202034378 A TW202034378 A TW 202034378A TW 108137411 A TW108137411 A TW 108137411A TW 108137411 A TW108137411 A TW 108137411A TW 202034378 A TW202034378 A TW 202034378A
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- 238000000034 method Methods 0.000 title claims abstract description 140
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 139
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Abstract
一種積體電路裝置的形成方法包括在一晶圓上形成一閘極介電質,在閘極介電質的上方形成一功函數層,在功函數層的上方沉積一覆蓋層,將覆蓋層浸置於一含矽氣體以形成一含矽層,在形成含矽層之後形成一阻擋層,以及在阻擋層的上方形成一金屬填充區域。
Description
本發明實施例內容是有關於一種積體電路裝置及其形成方法,特別是有關於一種具有可避免功函數層氧化以及穩定功函數層之組成的積體電路裝置及其形成方法。
金屬氧化物半導體(metal-oxide-semiconductor,MOS)裝置為積體電路中的基礎建構元件。現有的金屬氧化物半導體裝置通常具有透過摻雜操作(例如離子佈植或熱擴散)摻雜p型雜質或n型雜質的多晶矽所形成的閘極電極。可將閘極電極的功函數調整至矽的能帶邊緣(band-edge)。對於n型金屬氧化物半導體(n-type MOS,NMOS)裝置,可將功函數調整至接近矽的傳導帶(conduction band)。對於p型金屬氧化物半導體(p-type MOS,PMOS)裝置,可將功函數調整至接近矽的價帶(valence band)。多晶矽閘極電極的功函數的調整可透過選擇適當的雜質而達成。
具有多晶矽閘極電極的金屬氧化物半導體裝置表現出載子空乏效應(carrier depletion effect),此也被稱為多晶矽空乏效應(poly depletion effect)。當施加的電場從接近閘極介電質的閘極區域掃除載子時,產生多晶矽空乏效應,形成空乏層。在n型摻雜的多晶矽層中,空乏層包含離子化非移動的施體位置(donor site),其中在p型摻雜的多晶矽層中,空乏層包含離子化非移動的受體位置(acceptor site)。空乏效應導致有效閘極介電質厚度的增加,使得在半導體表面上產生反轉層(inversion layer)更加困難。
多晶矽空乏的問題可透過形成金屬閘極電極來解決,其中在n型金屬氧化物半導體(NMOS)裝置和p型金屬氧化物半導體(PMOS)裝置中使用的金屬閘極也可具有能帶邊緣的功函數。因此,最終的金屬閘極包含複數層,以滿足n型金屬氧化物半導體裝置和p型金屬氧化物半導體裝置的需求。
金屬閘極的形成通常涉及沉積金屬層,然後進行化學機械研磨(Chemical Mechanical Polish,CMP)以移除金屬層的多餘部分。金屬層的留下部分則形成金屬閘極。
本發明的一些實施例提供一種積體電路裝置的形成方法。此形成方法包括在一基底上形成一閘極介電質;在閘極介電質的上方形成一功函數層;在功函數層的上方沉積一覆蓋層(capping layer);將覆蓋層浸置於一含矽氣體(silicon-containing gas)以形成一含矽層;在形成含矽層之後,形成一阻擋層(blocking layer);以及在阻擋層的上方形成一金屬填充區域(metal-filling region)。在一實施例中,沉積上述覆蓋層包括複數次循環,各循環包括:一TiCl4
循環,包括通氣和吹掃TiCl4
;以及一氨(NH3
)循環,包括通氣和吹掃NH3
,且覆蓋層的沉積係終止於一額外的TiCl4
循環。在一實施例中,沉積上述覆蓋層包括複數次循環,各循環包括:一TiCl4
循環,包括通氣和吹掃TiCl4
;以及一氨循環,包括通氣和吹掃NH3
,且覆蓋層的沉積係終止於一額外的氨循環。在一實施例中,在浸置覆蓋層時,此覆蓋層浸置於含矽氣體,此含矽氣體包括的氣體係選自由SiH4
、Si2
H6
、二氯矽烷(DCS)、和前述之組合所組成之群組。在浸置覆蓋層時,基底例如是被加熱到約400°C至約600°C範圍之間的溫度。在一實施例中,積體電路裝置的形成方法更包括破壞真空,以使含矽層暴露於空氣中。在一實施例中,形成功函數層、沉積覆蓋層、以及浸置覆蓋層皆在相同的一真空環境中原位(in-situ)進行。沉積覆蓋層以及浸置覆蓋層例如是皆在相同的一製程腔室中進行。在一實施例中,積體電路裝置的形成方法更包括在一半導體條的一側壁和一頂面上,形成一虛置閘極堆疊;在虛置閘極堆疊的相對側壁上形成閘極間隔物;形成一層間介電質,使虛置閘極堆疊以及此些閘極間隔物都在層間介電質中;以及移除虛置閘極堆疊,以在此些閘極間隔物之間形成一溝槽,其中閘極介電質以及功函數層的形成係延伸至溝槽內。
本發明的一些實施例又提供一種積體電路裝置的形成方法。此形成方法包括在一半導體區上形成一閘極介電質;在一生產設備的一第一製程腔室中,在閘極介電質的上方形成一功函數層;在生產設備的一第二製程腔室中,在功函數層的上方沉積一第一氮化鈦層;在生產設備的第二製程腔室中,將第一氮化鈦層浸置於一含矽氣體,以形成一含矽層,其中含矽氣體係選自由SiH4
、Si2
H6
、二氯矽烷和前述之組合所組成之群組;暴露含矽層於氧中,以使含矽層的一部份轉換成為一含氧化矽層;在含氧化矽層上方形成一第二氮化鈦層;以及在第二氮化鈦層上方形成一金屬填充區域。在一實施例中,上述第一製程腔室和第二製程腔室係共用相同的一真空環境。浸置第一氮化鈦層的持續時間例如是在約180秒至約600秒之間的範圍。在一實施例中,暴露含矽層於氧中包括暴露含矽層於空氣中。在一實施例中,在室溫下使含矽層暴露於氧中。
本發明的一些實施例提供一種積體電路裝置,包括一半導體區;以及一閘極堆疊位於半導體區上。閘極堆疊包括:一閘極介電質;一功函數層位於閘極介電質的上方;一第一鈦層位於功函數層的上方;一含矽層位於第一鈦層的上方;一第二鈦層位於該含矽層的上方;以及一金屬填充區域位於第二鈦層的上方。在一實施例中,上述含矽層包括矽、氧、氮以及鈦。在一實施例中,上述含矽層包括氧化矽。在一實施例中,上述含矽層包括氮化矽。上述含矽層例如具有在約0.1nm至約1.5nm之間的範圍內的厚度。在一實施例中,上述功函數層包括鈦鋁(TiAl)層。
以下內容提供了很多不同的實施例或範例,用於實現本發明實施例的不同部件。組件和配置的具體範例描述如下,以簡化本發明實施例。當然,這些僅僅是範例,並非用以限定本發明實施例。舉例來說,敘述中若提及一第一部件形成於一第二部件之上方或位於其上,可能包含第一和第二部件直接接觸的實施例,也可能包含額外的部件形成於第一和第二部件之間,使得第一和第二部件不直接接觸的實施例。另外,本發明實施例可能在許多範例中重複元件符號及/或字母。這些重複是為了簡化和清楚的目的,其本身並非代表所討論各種實施例及/或配置之間有特定的關係。
此外,此處可能使用空間上的相關用語,例如「在…之下」、「在…下方」、「下方的」、「在…上方」、「上方的」及其他類似的用語可用於此,以便描述如圖所示之一元件或部件與其他元件或部件之間的關係。此空間上的相關用語除了包含圖式繪示的方位外,也包含使用或操作中的裝置的不同方位。裝置可以被轉至其他方位(旋轉90度或其他方位),則在此所使用的空間相對描述可同樣依旋轉後的方位來解讀。
依據各種例示性的實施例提供電晶體及其形成方法。依據一些實施例顯示形成電晶體的中間階段。討論一些實施例的一些變化。在各種視圖和顯示的實施例中,使用相同的參考符號來表示相同的元件。在顯示之例示性的實施例中,以鰭式場效電晶體(FinFET)的形成來說明本揭露實施例的概念。平面式電晶體亦可適用於本揭露的概念。根據本揭露的一些實施例,係在形成功函數層以及金屬覆蓋層之後,以及在填充金屬以形成金屬閘極之前,進行一種含矽氣體浸置(處理)製程(a silicon-containing soaking (treatment) process)。再者,前述含矽氣體浸置製程可以在一TiCl4
通氣和吹掃製程(pulsing and purging process)之後進行,以改善浸置製程的效率。因含矽氣體浸置製程所產生的含矽混合層(silicon-containing intermixing layers)具有可避免功函數層的金屬向上擴散而嚴重影響功函數的功能,以及具有可避免氧向下擴散而進入功函數層的功能。
第1~9、16、17圖繪示根據一些實施例之形成鰭式場效電晶體的中間階段的剖面圖與透視圖。在此些圖式所示的步驟亦示意性地反映於第24圖所示的製程流程200。
如第1圖所示,提供一基底20。基底20可以是半導體基底,例如一塊狀半導體(bulk semiconductor)、一絕緣層上覆半導體(semiconductor-on-insulator;SOI)基底、或其類似物,其可以是已摻雜(如摻雜有p型或n型摻雜物)或者是未摻雜的基底。基底20可以是晶圓10的一部份,例如一矽晶圓的一部份。一般而言,一絕緣層上覆半導體是將一層半導體材料形成在一絕緣層上。此絕緣層可以例如為一埋入式的氧化物(BOX)層、氧化矽層或類似物。將上述絕緣層形成於一基底上,上述基底通常是一矽基底或一玻璃基底。亦可使用其他基底,例如多層基底或漸變基底。在一些實施例中,基底20的半導體材料可包含:矽;鍺;一化合物半導體,包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦以及/或銻化銦;一合金半導體,包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP以及/或GaInAsP;或上述之組合。
再參照第1圖,在基底20中形成井區(well region)22。相應製程在第24圖所示的製作流程200中係為製程202。根據本揭露的一些實施例,井區22是通過注入p型雜質於基底20中而形成的p型井區,此p型雜質可以是硼、銦、或類似物。根據本揭露的其他實施例,井區22是通過注入n型雜質於基底20中而形成的n型井區,此n型雜質可以是磷、砷、銻、或類似物。所形成的井區22可以延伸到基底20的頂面。n型雜質或p型雜質濃度可以等於或小於1018
cm-3
,例如在大約1017
cm-3
和大約1018
cm-3
範圍之間。
參照第2圖,所形成的隔離區域24是自基底20的一頂面延伸到基底20中。在下文中,隔離區域24亦可稱為淺溝槽隔離(shallow trench isolation ,STI)區域。相應製程在第24圖所示的製作流程200中係為製程204。基底20在相鄰的淺溝槽隔離區域24之間的部分被稱為半導體條(semiconductor strips)26。為了形成淺溝槽隔離區域24,襯墊氧化層(pad oxide layer)28和硬遮罩層30形成於半導體基底20上,然後對其進行圖案化。襯墊氧化層28可以是由氧化矽形成的薄膜。根據本揭露的一些實施例,在熱氧化製程中形成襯墊氧化層28,其中半導體基底20的頂面層被氧化。襯墊氧化層28可作為半導體基底20與硬遮罩層30之間的一黏著層。襯墊氧化層28還可以作為用於蝕刻硬遮罩層30時的蝕刻停止層。根據本揭露的一些實施例,硬遮罩層30例如通過使用低壓化學氣相沉積(LPCVD)而由氮化矽形成。根據本揭露的其他實施例,硬遮罩層30通過矽的熱氮化或是電漿輔助化學氣相沉積(PECVD)而形成。在硬遮罩層30上形成光阻(未示出),然後將其圖案化。然後,使用圖案化的光阻作為蝕刻遮罩對硬遮罩層30進行圖案化,以形成如第2圖所示的硬遮罩層30。
接著,將圖案化的硬遮罩層30作為蝕刻遮罩以蝕刻襯墊氧化層28和基底20,之後以一介電材料填充基底20中所形成的溝槽。進行例如化學機械研磨(CMP)製程或機械研磨製程的平坦化製程,以去除介電材料的多餘部分,而介電材料的留下部分則成為淺溝槽隔離區域24。淺溝槽隔離區域24可以包括一襯墊介電質(liner dielectric,未示出),其可以是通過對基底20的表面層進行熱氧化所形成的熱氧化物。襯墊介電質也可以是沉積的氧化矽層、氮化矽層、或類似的材料層,其使用例如原子層沉積(atomic layer deposition,ALD)、高密度電漿化學氣相沉積(high-density plasma chemical vapor deposition,HDPCVD)或化學氣相沉積(chemical vapor deposition,CVD)沉積而成。淺溝槽隔離區域24還可以包括在襯墊氧化物上方的介電材料,其中可以使用流動式化學氣相沉積(flowable chemical vapor deposition;FCVD)、旋轉塗佈(spin-on coating)法或其他類似方法來形成上述介電材料。根據一些實施例,在襯墊介電質上方的介電材料可以包括氧化矽。
硬遮罩層30的頂面和淺溝槽隔離區域24的頂面可實質上彼此齊平。半導體條26位於相鄰的淺溝槽隔離區域24之間。根據本揭露的一些實施例,半導體條26是原本基底20的一部分,因此半導體條26的材料與基底20的材料相同。在本揭露的一些其他實施例中,半導體條26是通過淺溝槽隔離區域24之間的基底20的部分進行蝕刻以形成凹部,並且進行一磊晶製程以在凹部中再生長其他的半導體材料而形成的替換條(replacement strips)。因此,半導體條26是由不同於基底20的半導體材料所形成。根據一些實施例,半導體條26由矽鍺、矽碳或III-V族化合物半導體材料所形成。
參照第3圖,使淺溝槽隔離區域24凹陷,因此使半導體條26的頂部突出而高於淺溝槽隔離區域24的其餘部分的頂面24A,而形成突出的鰭部36。相應製程在第24圖所示的製作流程200中係為製程206。使淺溝槽隔離區域24凹陷的蝕刻步驟可使用一乾式蝕刻製程來施行,其中例如使用HF3與NH3作為蝕刻氣體。在上述蝕刻製程中,可產生電漿。亦可於上述蝕刻製程中加入氬。根據本揭露提出的其他一些實施例中,可使用一溼式蝕刻製程來進行淺溝槽隔離區域24的凹陷,其蝕刻劑可包含例如氫氟酸。
在上述實施例中,可透過任何適當的方法將鰭部圖案化。舉例而言,可使用一或多道光學微影製程將鰭部圖案化,光學微影製程包含雙重圖案化(double-patterning)或多重圖案化(multi-patterning)製程。一般而言,雙重圖案化或多重圖案化製程結合光學微影技術與自對準(self-aligned)製程,這使得所形成的圖案的節距(pitch)小於使用單一或直接的光學微影製程所獲得的圖案的節距。例如,在一實施例中,形成一犧牲層於基底之上,並且使用光學微影製程使犧牲層圖案化。使用自對準製程形成間隔物於犧牲層旁邊。接著移除犧牲層,且使用留下的間隔物或心軸(mandrels)對鰭部進行圖案化。
參照第4圖,在(突出的)鰭部36的上表面與側壁上形成虛置閘極堆疊(dummy gate stacks)38。相應製程在第24圖所示的製作流程200中係為製程208。虛置閘極堆疊38可包含虛置閘極介電質(dummy gate dielectrics)40以及在虛置閘極介電質40上方的虛置閘極42。可以使用例如多晶矽來形成,亦可以使用其他材料來形成虛置閘極42。各個虛置閘極堆疊38還可包括一個(或複數個)硬遮罩層44於虛置閘極42的上方。硬遮罩層44可以是由氮化矽、氧化矽、碳氮化矽、或多層前述材料而形成。虛置閘極堆疊38可跨越過單一個或複數個突出的鰭部36以及/或淺溝槽隔離區域24的上方而與其交叉設置。虛置閘極堆疊38亦可具有一縱長方向,其垂直於突出的鰭部36的縱長方向。
接著,在虛置閘極堆疊38上形成閘極間隔物(gate spacers)46。相應製程在第24圖所示的製作流程200中係為製程208。根據本揭露的一些實施例,閘極間隔物46是以一介電材料來形成,介電材料例如是氮化矽、碳氮化矽、或其他類似材料,並可以是一單層結構、或者包含複數個介電層的一多層結構。
然後,進行一蝕刻步驟,以對於突出的鰭部36之未被虛置閘極堆疊38和閘極間隔物46覆蓋的部分進行蝕刻,而成為第5圖所繪示的結構。相應製程在第24圖所示的製作流程200中係為製程210。此處敘述的凹陷步驟可以是異向性(anisotropic),因而使直接位於虛置閘極堆疊38與閘極間隔物46正下方的突出鰭部36的部分受到保護,而未被蝕刻。根據本揭露的一些實施例,凹陷的半導體條26的頂面可低於淺溝槽隔離區域24的頂面24A。因而形成凹部(Recesses)50。凹部50包括位於虛置閘極堆疊38之相對兩側的部分,以及位於留下的突出鰭部36之間的部分。
接著,藉由在凹部50內選擇性地成長(透過磊晶方式)一半導體材料,以形成磊晶區(源極/汲極區)54,而成為第6圖所繪示的結構。相應製程在第24圖所示的製作流程200中係為製程212。根據欲形成的鰭式場效電晶體是p型鰭式場效電晶體或是n型鰭式場效電晶體,而在磊晶製程期間原位(in-situ)摻雜p型或n型雜質。例如,當欲形成的鰭式場效電晶體為p型鰭式場效電晶體,可成長矽鍺硼(silicon germanium boron;SiGeB)或矽硼(silicon boron;SiB)。相反地,當欲形成的鰭式場效電晶體為n型鰭式場效電晶體,可成長矽磷(silicon phosphorous;SiP)或矽碳磷(silicon carbon phosphorous;SiCP)。根據本揭露的一些替代性的實施例,磊晶區54包括III-V族化合物半導體,例如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、上述之組合、或上述之多層結構。在凹部50填充磊晶區54之後,磊晶區54進一步的磊晶成長會使磊晶區54水平地擴展,而可形成複數個刻面(facets)。磊晶區54進一步的磊晶成長也可能造成相鄰的磊晶區54彼此合併。也可能產生孔隙(voids)(空氣間隙(air gaps))56。根據本揭露的一些實施例,可能在磊晶區54的頂面仍呈波浪狀時完成磊晶區54的形成,或者進一步地使磊晶區54繼續成長而使合併的磊晶區54的頂面如第6圖所示已經變得平坦時,完成磊晶區54的形成。
在上述磊晶步驟之後,可進一步以p型雜質或n型雜質植入磊晶區54,以形成源極與汲極,其仍使用元件符號54。根據本揭露的一些其他實施例,在磊晶的過程中若磊晶區42已被原位摻雜p型雜質或n型雜質,則可省略此處敘述的佈植步驟。
第7A圖繪示形成接觸蝕刻停止層(contact etch stop layer;CESL)58以及層間介電質(inter-layer dielectric;ILD)60後之結構的透視圖。相應製程在第24圖所示的製作流程200中係為製程214。接觸蝕刻停止層58可以是以氧化矽、氮化矽、碳氮化矽、或其他類似材料來形成,且可以使用化學氣相沉積、原子層沉積、或其他沉積方式形成。層間介電質60可包含使用例如流動式化學氣相沉積、旋轉塗佈法、化學氣相沉積、或其他沉積方式形成的一介電材料。層間介電質60亦可以採用一含氧介電材料而形成,其可以是矽氧類材料,例如四乙氧基矽烷(Tetra Ethyl Ortho Silicate;TEOS)氧化物、磷矽玻璃(Phospho-Silicate Glass;PSG)、硼矽玻璃(Boro-Silicate Glass;BSG)、硼磷矽玻璃(Boron-Doped Phospho-Silicate Glass;BPSG)、或其他類似材料來形成。可以進行一平坦化步驟,例如化學機械研磨(Chemical Mechanical Polish;CMP)或是一機械研磨(mechanical grinding),以使層間介電質60、虛置閘極堆疊38與閘極間隔物46的頂面彼此互相齊平。
第7B圖繪示沿著第7A圖中剖面線7B-7B之包含虛置閘極堆疊38的剖面圖。接著,蝕刻包含硬遮罩層44、虛置閘極42以及虛置閘極介電質40的虛置閘極堆疊38,並於閘極間隔物46之間形成溝槽(trenches)62,如第8圖所示,相應製程在第24圖所示的製作流程200中係為製程216。突出鰭部36的頂面和側壁係暴露於溝槽62處。接著,如第9A和9B圖所示,替換閘極堆疊(replacement gate stacks)72形成於溝槽62(第8圖)中。此相應製程在第24圖所示的製作流程200中係為製程218。第9B圖繪示沿著第9A圖中剖面線9B-9B之剖面圖。替換閘極堆疊72包括閘極介電質68和對應的閘極電極70。
根據本揭露的一些實施例,如第9B圖所示,閘極介電質68包含界面層(interfacial layer;IL)64作為其下部。界面層64是形成在突出鰭部36的曝露出來的表面上。界面層64可包括經由突出鰭部36的熱氧化、一化學性氧化製程或一沉積製程而形成的一氧化物層,例如一氧化矽層。閘極介電質68亦可包括形成於界面層64的上方的高介電常數介電層(high-k dielectric layer)66,例如。高介電常數介電層66包括一高介電常數介電材料(high-k dielectric material),例如氧化鉿、氧化鑭、氧化鋁、氧化鋯、或其類似物。上述高介電常數介電材料的介電常數(k值)係大於3.9,並且可以大於7.0,有時甚至高達21.0或者更高。高介電常數介電層66是在界面層64之上,並可以接觸界面層64。高介電常數介電層66可以被形成為一共形層,並可以延伸到突出的鰭部36的側壁上以及閘極間隔物46的頂面與側壁上。根據本揭露的一些實施例,可使用原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積(PECVD)、 分子束沉積(Molecular-Beam Deposition;MBD)、或其他沉積方式來形成高介電常數介電層66。
請進一步參考第9B圖,閘極電極70形成於閘極介電質68上。閘極電極70可包含多個堆疊層74,其可以形成為多個共形層(conformal layers),且溝槽中未被堆疊層74填滿的空間則以金屬填充而形成金屬填充區域(filling-metal regions)76。堆疊層74包含一阻障層(barrier layer)、位於阻障層上方的一功函數層、以及位於功函數層上方的一個或多個金屬蓋層(metal capping layers)。堆疊層74的細部結構和形成方法係參照第10-15圖討論如後。
第9B圖所繪示的區域78,其包含有一部份的鰭部36、一部份的閘極介電質68、一部份的堆疊層74、以及一部份的金屬填充區域76。第10-15圖繪示根據本揭露一些實施例所形成的部件延伸至區域78中。此相應製程是繪示於第25圖所示的製作流程300中。藉由製作流程300而實現第24圖中所示的製程218。
參照第10圖,形成閘極介電質68,其包括界面層64以及高介電常數介電層66。此相應製程在第25圖所示的製作流程300中係為製程302。界面層64形成在突出的鰭部36上。高介電常數介電層66形成在界面層64上。在一些實施例中,在高介電常數介電層66的上方形成附著層(adhesion layer)(亦即一擴散阻障層)118。此相應製程在第25圖所示的製作流程300中係為製程304。附著層118可以是氮化鈦(TiN)或氮化鈦矽(TSN)。可以使用原子層沉積(ALD)或化學氣相沉積(CVD)形成氮化鈦層。而氮化鈦矽層可包含,例如經由原子層沉積方式,交替沉積的氮化鈦層以及氮化矽層。由於氮化鈦層以及氮化矽層都非常薄,使得這些層可能難以彼此區分,因此可被統稱為一氮化鈦矽 (TSN)層。
功函數層120形成在附著層118之上方。相應製程在第25圖所示的製作流程300中係為製程306。功函數層120決定了閘極的功函數,並包括至少一層或是多個以不同材料形成的層。前述功函數層的材料可根據鰭式場效電晶體是一n型鰭式場效電晶體或是一p型鰭式場效電晶體而做選擇。例如,當鰭式場效電晶體為一n型鰭式場效電晶體,其功函數層120可包括位於TaN層上方的一鈦鋁(TiAl)層。當鰭式場效電晶體為一p型鰭式場效電晶體,其功函數層可包括一TaN層、在TaN層上方的一TiN層、以及可能沒有包含或有包含在前述TiN層上方的一鈦鋁層。可以理解的是,功函數層可以包括不同的材料,這也是可以預期的。
根據本揭露的一些實施例,一覆蓋層(capping layer)122形成於功函數層120上方,如第11圖所示。相應製程在第25圖所示的製作流程300中係為製程308。根據一些實施例,覆蓋層122可以由氮化鈦(TiN)所製得,而其他材料例如氮化鉭(TaN)也可以使用。根據一些實施例,可以使用原子層沉積形成覆蓋層122。根據一些實施例,覆蓋層122的厚度可以在大約10 nm至大約50 nm的範圍之間。
根據一些實施例,形成覆蓋層122包含將四氯化鈦(TiCl4
)氣體通入(pulsing)相應製程的原子層沉積腔室(ALD chamber)(例如,第22圖中的腔室404),然後吹掃(purging)TiCl4
。相應製程在第25圖所示的製作流程300中係分別為製程310和312。通氣的持續時間(TiCl4
與晶圓10接觸的時間)可以是在約0.1秒至10秒的範圍之間。在一些實施例中,TiCl4
的流速在約50每分鐘標準毫升(standard cubic centimeter per minute,sccm)至約150sccm的範圍之間,且TiCl4
的通氣和吹掃則統稱為一TiCl4
循環(TiCl4
cycle)。
接著,將氨(NH3
)通入原子層沉積腔室,然後吹掃(purging)氨。相應製程在第25圖所示的製作流程300中係分別為製程314和316。通氣的持續時間(氨與晶圓10接觸的時間)可以是在約0.1秒至10秒的範圍之間。於文中之敘述,氨的通氣和吹掃則統稱為一氨循環(NH3
cycle)。氨的流速在約50 sccm至約100sccm的範圍之間。在形成覆蓋層122的期間,晶圓10的溫度是在約 400°C 至約600°C的範圍之間。TiCl4
和氨的壓力可分別在4托耳(torr)至約20托耳的範圍之間。
一次TiCl4
循環以及一次氨循環的組合可導致形成一TiN(原子)層,因此一次TiCl4
循環以及一次氨循環的組合可稱為一原子層沉積循環(ALD loop)。覆蓋層122的形成可包含複數次原子層沉積循環,而製作流程300包含回到製程310的循環。所製得的覆蓋層122的厚度可以在約10 nm至約50 nm的範圍之間。
根據一些實施例,覆蓋層122的形成可以終止於一氨循環,此以第25圖所示的製程316終止於製程322來表示。根據本揭露的一些其他的實施例,覆蓋層122的形成可以終止於一TiCl4
循環,這在第25圖所示的製作流程300中還包括了製程318和320。如將在隨後的段落中討論的,終止於TiCl4
循環所形成的覆蓋層122可以改善結果。當覆蓋層122於TiCl4
循環結束時完成時,結束的TiCl4
的第二通氣持續時間(second pulsing duration)(第25圖中的製程318)可以延長到比之前的原子層沉積循環的TiCl4
的第一通氣持續時間(第25圖中的製程310)要更長。例如,結束的TiCl4
的通氣持續時間可以在約0.1秒至約10秒的範圍之間。第二通氣持續時間與第一通氣持續時間的比值大於1.0,並且可以在大約2.0至大約5.0的範圍之間。
在結束TiCl4
通氣之製程318期間,亦可加熱晶圓10,例如,加熱到約400°C至約600°C之間的溫度。根據一些實施例,沒有電漿產生。最終的TiCl4
通氣致使得到的分子(例如Tix
Cly
分子,x和y為整數) 暴露並連接至下方的覆蓋層122。最終的TiCl4
通氣製程可用來改善覆蓋層122與後續提供的矽之間的鍵結,如後續段落所討論。
第12圖繪示使用一含矽氣體的一浸置製程(soaking process)(如箭頭123所示),其中含矽氣體可以是SiH4
、Si2
H6
、二氯矽烷(dichlorosilane,DCS)、或類似氣體、或前述之組合。此相應製程在第25圖所示的製作流程300中係為製程322。在含矽氣體浸置期間,晶圓10會被加熱,例如加熱到約400°C至約600°C之間的溫度。含矽氣體的流速可以在約300 sccm至約500sccm的範圍之間。含矽氣體的壓力可在4托耳(torr)至約20托耳的範圍之間。根據一些實施例,沒有電漿產生。浸置持續時間可以在約180秒至約600秒的範圍之間。
第12圖示意性地示出了由於含矽氣體的浸置而形成的矽層124。根據本揭露的一些實施例,矽層124的厚度在大約1埃(Å)至大約15埃之間的範圍內,而此厚度可以更大或更小於前述範圍。
可以在相同的真空環境中原位(in-situ)進行功函數層120的形成、覆蓋層122的形成、最終的TiCl4
通氣製程以及含矽氣體浸置(silicon-containing gas soaking)製程,從而在這些製程之間沒有破壞真空的情況發生。這些製程是連續進行的,並且可以在具有相同真空環境的同一平台中的不同處理腔室中進行這些製程。例如,第22圖繪示出了生產設備400,其包括承載/卸載器(loadlocks)402以及多個處理室(process chambers),這些處理室包括共享相同真空環境的真空室404和406。根據一些實施例,功函數層120在處理腔室404中沉積,而覆蓋層122的形成、最終的TiCl4
通氣製程以及含矽氣體浸置製程則在處理腔室406中進行,其被設計用於原子層沉積(ALD)製程。
第18圖示意性地示出了以氨(NH3
)循環結束的覆蓋層122的頂表面。在覆蓋層122的頂面上有一些Tix
Cly
分子。Tix
Cly
分子具有懸掛鍵(dangling bonds),此懸掛鍵可用來使矽原子附著。但是,由於此過程以氨循環結束,因此大部分Tix
Cly
分子可能會被氨(NH3
)分子(以沒有Tix
Cly
的空白表示)終止,從而留下有限數量的懸掛鍵。因此,可以連接的矽原子的數量受到限制。
第19圖示意性地示出了以TiCl4
循環結束的覆蓋層122的頂面。結果,更多的Tix
Cly
分子在覆蓋層122的表面上。與以氨(NH3
)循環結束所形成的覆蓋層相比,可以附著的矽原子的量因此增加。
第23圖顯示出結果的比較,其示出了附著到覆蓋層表面的矽的標準化含量(normalized amount of silicon)與浸置時間(soaking time)的關係。實心圓圈是矽附著到使用氨(NH3
)終止循環而形成的覆蓋層上的結果。空心圓圈和正方形是矽附著到使用TiCl4
終止循環形成的覆蓋層上的結果。數據結果顯示,使用TiCl4
終止循環可以有更多的矽附著到覆蓋層上。
再參照第13圖,在含矽氣體浸置製程之後,可以進行真空破壞,並且將矽層124暴露於空氣中。相應製程在第25圖所示的製作流程300中係為製程324。矽層124暴露於開放空氣(乾淨的空氣,其處於室溫,例如,在大約20°之間的範圍內)後,矽層124(第12圖)被氧化以形成如第13圖所示之含矽層126。
在矽層124暴露的期間,空氣中的氧氣與矽層124反應而形成氧化矽層126C。氧化矽層126C富含氧和矽,並且還可以包括其他元素,例如氮和鈦。因此,氧化矽層126C實際上是這些元素的一混合層,並且在下文中也稱為矽-氧混合層(silicon-oxide intermixing layer)126C。矽-氧混合層126C的厚度可以在約0.1nm至約10nm之間的範圍內。另一方面,由於矽層124接觸包括氮化鈦(TiN)的覆蓋層122,所以可以形成氮化矽混合層126A,部分是由於含矽氣體浸置製程中的高溫而形成。氮化矽混合層126A富含矽和氮,並且還可包括例如氧和鈦的其他元素。來自功函數層120的部分的鋁也可以擴散到氮化矽混合層126A中。氮化矽混合層126A的厚度可以在約0.1nm至約10nm之間的範圍內。
矽層124可能存在或可能不存在矽混合層(silicon intermixing layer)126B,此矽混合層126B富含矽,並且可以包含其他元素,例如氮、氧、鈦或類似物,並且可能包含少量的鋁,其包含物質或元素係視矽層124(第12圖)的厚度而定。氮化矽混合層126A、矽混合層126B和矽-氧混合層126C在下文中可被統稱為含矽層126。含矽層126可具有一厚度在約0.1nm至約1.5nm之間的範圍內。
雖然含矽層126很薄,但是它具有阻擋氧向下擴散而氧化功函數層120的功能,以及具有阻止金屬(例如鋁)自功函數層120擴散出去而導致相應鰭式場效電晶體(FinFET)的臨界電壓(threshold voltage)漂移的功能。第20圖示意性地示出了覆蓋層122的多晶粒結構(multi-grain structure),其包括多個晶粒。氧和金屬原子可通過覆蓋層122的晶粒之間的路徑而擴散。在覆蓋層122(第20圖中未示出)上方的含矽層126可作為阻擋擴散的一阻擋層。
再參照第13圖,應可理解的是,由於元素的擴散,在子層之間,例如氮化矽混合層126A、矽混合層126B和矽-氧混合層126C之間,可能沒有明確的邊界。第21圖示出了一些元素的含量與距離Z的函數關係(第13圖),此距離Z是從第13圖中突出的鰭部36的頂面開始測量的。X軸(第21圖)代表距離Z,Y軸表示元素氧(O),氮(N),鋁(Al),鈦(Ti)和鉿(Hf)的標準化含量(normalized amount)。分別對突出的鰭部36(包括Si)、高介電常數介電層66(包括鉿)、功函數層120(包括TiAl)、覆蓋層122(包括氮化鈦)、含矽層126和阻擋層氮化鈦(TiN)(在後續步驟中形成)進行簡短標記。將第21圖所示的結果與其形成過程不包括含矽氣體浸置製程的樣品(未示出)的結果進行比較,發現氧擴散到覆蓋層122中以及鋁擴散穿過含矽層126減少了。
第14圖繪示出了阻擋層(blocking layer)128的形成。相應製程在第25圖所示的製作流程300中係為製程326。阻擋層128的形成方法、材料、厚度等可以從適合的形成方法、適合的材料、適合的厚度中選擇。覆蓋層122的形成方法、材料、厚度亦可從適合的形成方法、適合的材料、適合的厚度中選擇。因此,細節不再贅述。例如,阻擋層128可以由TiN形成,其可以使用原子層沉積方式形成。擴散阻障層118、功函數層120、含矽層126以及阻擋層128的組合可對應於第9B圖中的堆疊層74。
第15圖繪示了金屬填充區域76的沉積。相應製程在第25圖所示的製作流程300中係為製程328。根據一些實施例,金屬填充區域76由鎢或鈷製得,其可以使用化學氣相沉積形成。根據一些實施例,WF6
和SiH4
可作為沉積鎢的製程氣體。在形成金屬填充區域76之後,可以進行平坦化製程以去除沉積的層的多餘部分,如第15圖所示,從而得到如第9A和9B圖所示的閘極堆疊72。在第25圖所示的製作流程300中,各個平坦化製程係為製程330。
第16圖繪示出了根據一些實施例的硬遮罩80的形成。相應製程在第24圖所示的製作流程200中係為製程220。 相應的過程在圖24所示的過程流程200中被示為過程220。硬遮罩80的形成可以包括進行蝕刻過程以使閘極堆疊72凹陷,從而在閘極間隔物46之間形成凹陷;使用介電材料,然後進行如化學機械研磨(CMP)製程或機械研磨製程的平坦化製程以去除介電材料的多餘部分。硬遮罩80可以由氮化矽、氧氮化矽, 碳氮氧化矽、或類似材料。
第17圖繪示出了源極/汲極接觸插塞(source/drain contact plugs)82的形成。相應製程在第24圖所示的製作流程200中係為製程222。源極/汲極接觸插塞82的形成包括蝕刻層間介電質60以暴露出下方的接觸蝕刻停止層58,然後,蝕刻接觸蝕刻停止層58露出來的部分,以暴露出源極區/汲極區(source/drain regions)54。在之後的製程中,沉積一金屬層(例如一鈦層)並延伸到接觸開口(contact openings)中。亦可以形成一金屬氮化物覆蓋層(metal nitride capping layer)。然後,進行退火製程,以使金屬層與源極區/汲極區54的頂部反應,而形成金屬矽化物區(silicide regions)84,如第17圖所示。接著,可以保留之前形成的金屬氮化物層而不將其去除,或者去除之前形成的金屬氮化物層。去除之前形成的金屬氮化物層,然後沉積一新的金屬氮化物層(例如氮化鈦層)。然後,將例如鎢、鈷、或類似物的金屬填充材料填充到接觸開口中,隨後進行平坦化以去除多餘的材料,從而形成源極/汲極接觸插塞82。圖中未繪示出閘極接觸插塞(gate contact plugs)。閘極接觸插塞也形成為穿過每個硬遮罩80的一部分,以接觸閘極電極70。因而形成鰭式場效電晶體86,而這些鰭式場效電晶體86彼此平行連接而如同單一個鰭式場效電晶體。
本揭露的實施例具有一些優異特徵。通過含矽氣體浸置製程,在功函數層上方形成一含矽層。含矽層很薄,並且是包括富含氧化矽部分和富含氮化矽部分的一混合層。含矽層可以有效避免氧氣向下滲透以到達功函數層,因此可以防止功函數層的氧化。此外,含矽層可以避免功函數層中的金屬向上擴散,因此可以幫助保持功函數層的組成穩定,並避免所製得的FinFET的臨界電壓漂移。據此,本揭露可以減少了臨界電壓方面的問題,此臨界電壓的問題是指在不同區域(例如,電晶體密集區域和電晶體稀疏區域)中的電晶體之間的臨界電壓值電壓差的擴大。
根據本揭露的一些實施例,一種積體電路裝置的形成方法包括在一基底上形成一閘極介電質;在閘極介電質的上方形成一功函數層;在功函數層的上方沉積一覆蓋層(capping layer);將覆蓋層浸置於一含矽氣體(silicon-containing gas)以形成一含矽層;在形成含矽層之後,形成一阻擋層(blocking layer);以及在阻擋層的上方形成一金屬填充區域(metal-filling region)。在一實施例中,沉積上述覆蓋層包括複數次循環,各循環包括:一TiCl4
循環,包括通氣和吹掃TiCl4
;以及一氨(NH3
)循環,包括通氣和吹掃NH3
,且覆蓋層的沉積係終止於一額外的TiCl4
循環。在一實施例中,沉積上述覆蓋層包括複數次循環,各循環包括:一TiCl4
循環,包括通氣和吹掃TiCl4
;以及一氨(NH3
)循環,包括通氣和吹掃NH3
,且覆蓋層的沉積係終止於一額外的氨循環。在一實施例中,在浸置覆蓋層時,此覆蓋層浸置於含矽氣體,此含矽氣體包括的氣體係選自由SiH4
、Si2
H6
、二氯矽烷(dichlorosilane,DCS)、和前述之組合所組成之群組。在一實施例中,在浸置覆蓋層時,基底被加熱到約400°C至約600°C範圍之間的溫度。在一實施例中,積體電路裝置的形成方法更包括破壞真空,以使含矽層暴露於空氣中。在一實施例中,形成功函數層、沉積覆蓋層、以及浸置覆蓋層皆在相同的一真空環境中原位(in-situ)進行。在一實施例中,沉積覆蓋層以及浸置覆蓋層皆在相同的一製程腔室中進行。在一實施例中,積體電路裝置的形成方法更包括在一半導體條的一側壁和一頂面上,形成一虛置閘極堆疊(dummy gate stack);在虛置閘極堆疊的相對側壁上形成閘極間隔物(gate spacers);形成一層間介電質,使虛置閘極堆疊以及此些閘極間隔物都在層間介電質中;以及移除虛置閘極堆疊,以在此些閘極間隔物之間形成一溝槽(trench),其中閘極介電質以及功函數層的形成係延伸至溝槽內。
根據本揭露的一些實施例,一種積體電路裝置的形成方法包括在一半導體區上形成一閘極介電質;在一生產設備的一第一製程腔室中,在閘極介電質的上方形成一功函數層;在生產設備的一第二製程腔室中,在功函數層的上方沉積一第一氮化鈦層;在生產設備的第二製程腔室中,將第一氮化鈦層浸置於一含矽氣體,以形成一含矽層,其中含矽氣體係選自由SiH4
、Si2
H6
、二氯矽烷和前述之組合所組成之群組;暴露含矽層於氧中,以使含矽層的一部份轉換成為一含氧化矽層(silicon oxide containing layer);在含氧化矽層上方形成一第二氮化鈦層;以及在第二氮化鈦層上方形成一金屬填充區域。在一實施例中,上述第一製程腔室和第二製程腔室係共用相同的一真空環境。在一實施例中,浸置第一氮化鈦層的持續時間係在約180秒至約600秒之間的範圍。在一實施例中,暴露含矽層於氧中包括暴露含矽層於空氣中。在一實施例中,在室溫下使含矽層暴露於氧中。
根據本揭露的一些實施例,一種積體電路裝置包括一半導體區;以及一閘極堆疊(gate stack)位於半導體區上。閘極堆疊包括:一閘極介電質;一功函數層位於閘極介電質的上方;一第一鈦層位於功函數層的上方;一含矽層位於第一鈦層的上方;一第二鈦層位於含矽層的上方;以及一金屬填充區域位於該第二鈦層的上方。在一實施例中,上述含矽層包括矽、氧、氮以及鈦。在一實施例中,上述含矽層包括氧化矽。在一實施例中,上述含矽層包括氮化矽。在一實施例中,上述含矽層具有一厚度在約0.1nm至約1.5nm之間的範圍內。在一實施例中,上述功函數層包括鈦鋁(TiAl)層。
以上概述數個實施例之部件,以便在本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解,他們能輕易地以本發明實施例為基礎,設計或修改其他製程和結構,以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解,此類等效的結構並無悖離本發明的精神與範圍,且他們能在不違背本發明之精神和範圍下,做各式各樣的改變、取代和替換。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。
10:晶圓
20:基底
22:井區
24:(淺溝槽)隔離區域
24A:頂面
26:半導體條
28:襯墊氧化層
30,44:硬遮罩層
36:鰭部
38:虛置閘極堆疊
40:虛置閘極介電質
42:虛置閘極
46:閘極間隔物
50:凹部
54:磊晶區(源極區/汲極區)
56:孔隙
58:接觸蝕刻停止層
60:層間介電質
62:溝槽
64:界面層
66:高介電常數介電層
68:閘極介電質
70:閘極電極
72:(替換)閘極堆疊
74:堆疊層
76:金屬填充區域
78:區域
80:硬遮罩
82:源極/汲極接觸插塞
84:金屬矽化物區
86:鰭式場效電晶體
118:附著層
120:功函數層
122:覆蓋層
124:矽層
126:含矽層
126A:氮化矽混合層
126B:矽混合層
126C:氧化矽層
128:阻擋層
400:生產設備
404,406:腔室
200,300:流程
202,204,206,208,210,212,214,216,218,220,222,302,304,306,308,310,312,314,316,318,320,322,324,326,328,330:製程
藉由以下的詳細描述配合所附圖式,可以更加理解本發明實施例的內容。需強調的是,根據產業上的標準慣例,許多部件(feature)並未按照比例繪製。事實上,為了能清楚地討論,各種部件的尺寸可能被任意地增加或減少。
第1、2、3、4、5、6、7A、7B、8、9A、9B、16、17圖繪示根據一些實施例之形成一鰭式場效電晶體(FinFET)的中間階段的剖面圖與透視圖。
其中,第7A圖繪示形成接觸蝕刻停止層以及層間介電質後之結構的透視圖;第7B圖繪示沿著第7A圖中剖面線7B-7B之包含虛置閘極堆疊的剖面圖;第9B圖繪示沿著第9A圖中剖面線9B-9B之剖面圖。
第10、11、12、13、14、15圖繪示根據本揭露一些實施例之形成一電晶體的一閘極堆疊的中間階段的透視圖與剖面圖。
其中,第11圖繪示形成一覆蓋層於功函數層上方;第12圖繪示使用一含矽氣體的一浸置製程(soaking process);第13圖繪示根據一些實施例的在含矽氣體浸置製程之後進行真空破壞,使如第12圖所示之矽層被氧化而形成含矽層;第14圖繪示根據一些實施例的阻擋層(blocking layer)的形成;第15圖繪示根據一些實施例的金屬填充區域的沉積。
第16圖繪示根據本揭露一些實施例之硬遮罩的形成。
第17圖繪示根據本揭露一些實施例之源極/汲極接觸插塞的形成。
第18圖繪示根據本揭露一些實施例之以氨循環結束的氮化鈦覆蓋層的頂表面附著有Tix
Cly
分子。
第19圖繪示根據本揭露一些實施例之以TiCl4
循環結束的氮化鈦覆蓋層122的頂面附著有Tix
Cly
分子。
第20圖繪示根據本揭露一些實施例之在多晶粒結構的氮化鈦層中的擴散路徑。
第21圖繪示根據本揭露一些實施例之在一電晶體的一閘極堆疊中不同元素的分布。
第22圖繪示根據本揭露一些實施例之用以原位(in-situ)形成一閘極堆疊中各個層的一生產設備(production tool)的示意圖。
第23圖繪示根據本揭露一些實施例之附著到氮化鈦層表面的矽的標準化含量,其中氮化鈦層的形成是以氨循環結束或是以TiCl4
循環結束。
第24圖繪示根據本揭露一些實施例之形成一鰭式場效電晶體的製作流程。
第25圖繪示根據本揭露一些實施例之於一鰭式場效電晶體中形成一閘極堆疊的製作流程。
300:流程
302,304,306,308,310,312,314,316,318,320,322,324,326,328,330:製程
Claims (20)
- 一種積體電路裝置的形成方法,包括: 在一基底上形成一閘極介電質; 在該閘極介電質的上方形成一功函數層; 在該功函數層的上方沉積一覆蓋層(capping layer); 將該覆蓋層浸置於一含矽氣體(silicon-containing gas)以形成一含矽層; 在形成該含矽層之後,形成一阻擋層(blocking layer);以及 在該阻擋層的上方形成一金屬填充區域(metal-filling region)。
- 如請求項1之所述之積體電路裝置的形成方法,其中沉積該覆蓋層包括複數次循環,該些循環各包括: 一四氯化鈦(TiCl4 )循環,包括通氣和吹掃TiCl4 ;以及 一氨(NH3 )循環,包括通氣和吹掃NH3 ,且沉積該覆蓋層係終止於一額外的TiCl4 循環。
- 如請求項1之所述之積體電路裝置的形成方法,其中沉積該覆蓋層包括複數次循環,該些循環各包括: 一TiCl4 循環,包括通氣和吹掃TiCl4 ;以及 一氨(NH3 )循環,包括通氣和吹掃NH3 ,且沉積該覆蓋層係終止於除了該些循環中的該些氨循環外的一額外的氨循環(an additional NH3 cycle)。
- 如請求項1之所述之積體電路裝置的形成方法,其中在浸置該覆蓋層時,該覆蓋層浸置於該含矽氣體,該含矽氣體包括選自由SiH4 、Si2 H6 、二氯矽烷(dichlorosilane,DCS)、和前述之組合所組成之群組的一氣體。
- 如請求項1之所述之積體電路裝置的形成方法,其中在浸置該覆蓋層時,該基底被加熱到約400°C至約600°C範圍之間的溫度。
- 如請求項1之所述之積體電路裝置的形成方法,更包括破壞真空,以使該含矽層暴露於空氣中。
- 如請求項1之所述之積體電路裝置的形成方法,其中形成該功函數層、沉積該覆蓋層、以及浸置該覆蓋層皆在相同的一真空環境中原位(in-situ)進行。
- 如請求項7之所述之積體電路裝置的形成方法,其中沉積該覆蓋層以及浸置該覆蓋層皆在相同的一製程腔室中進行。
- 如請求項1之所述之積體電路裝置的形成方法,更包括: 在一半導體鰭的一側壁和一頂面上,形成一虛置閘極堆疊(dummy gate stack); 在該虛置閘極堆疊的相對側壁上形成閘極間隔物(gate spacers); 形成一層間介電質,使該虛置閘極堆疊以及該些閘極間隔物都在該層間介電質中;以及 移除該虛置閘極堆疊以在該些閘極間隔物之間形成一溝槽(trench),其中該閘極介電質以及該功函數層的形成係延伸至該溝槽內。
- 一種積體電路裝置的形成方法,包括: 在一半導體區上形成一閘極介電質; 在一生產設備的一第一製程腔室中,在該閘極介電質的上方形成一功函數層; 在該生產設備的一第二製程腔室中,在該功函數層的上方沉積一第一氮化鈦層; 在該生產設備的該第二製程腔室中,將該第一氮化鈦層浸置於一含矽氣體,以形成一含矽層,其中該含矽氣體係選自由SiH4 、Si2 H6 、二氯矽烷(dichlorosilane,DCS)和前述之組合所組成之群組; 暴露該含矽層於氧中,以使該含矽層的一部份轉換成為一含氧化矽層(silicon oxide containing layer); 在該含氧化矽層上方形成一第二氮化鈦層;以及 在該第二氮化鈦層上方形成一金屬填充區域。
- 如請求項10之所述之積體電路裝置的形成方法,其中該第一製程腔室和該第二製程腔室係共用相同的一真空環境。
- 如請求項10之所述之積體電路裝置的形成方法,其中浸置該第一氮化鈦層的持續時間係在約180秒至約600秒之間的範圍。
- 如請求項10之所述之積體電路裝置的形成方法,其中暴露該含矽層於氧中包括暴露該含矽層於空氣中。
- 如請求項13之所述之積體電路裝置的形成方法,其中在一室溫下使該含矽層暴露於氧中。
- 一種積體電路裝置,包括: 一半導體區;以及 一閘極堆疊(gate stack)位於該半導體區上,該閘極堆疊包括: 一閘極介電質; 一功函數層位於該閘極介電質的上方; 一第一鈦層位於該功函數層的上方; 一含矽層位於該第一鈦層的上方; 一第二鈦層位於該含矽層的上方;以及 一金屬填充區域位於該第二鈦層的上方。
- 如請求項15之所述之積體電路裝置,其中該含矽層包括矽、氧、氮以及鈦。
- 如請求項15之所述之積體電路裝置,其中該含矽層包括氧化矽。
- 如請求項15之所述之積體電路裝置,其中 該含矽層包括氮化矽。
- 如請求項15之所述之積體電路裝置,其中 該含矽層具有一厚度在約0.1nm至約1.5nm之間的範圍內。
- 如請求項15之所述之積體電路裝置,其中該功函數層包括鈦鋁(TiAl)層。
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